c mos- ic''s -data -book

7/30/2019 C mos- IC''s -Data -Book

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CMOS L

Rev.

This book presents technical data for the broad line of CMOS logic integrated circuits and demonductor’s continued commitment to Metal–Gate CMOS. Complete specifications are provided in theIn addition, a Product Selector Guide and a Handling and Design Guidelines chapter have been incthe user with these circuits.



ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves thwithout further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its ppurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically discincluding without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCIspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, inclvalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent righSCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the bintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation whermay occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indand its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, evenSCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Empl

PUBLICATION ORDERING INFORMATION

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Table of Contents

Chapter 1 — Master Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Alphanumeric Listing of All CMOS Part Numbers with Function and Page Number Information Prov

Chapter 2 — Product Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMOS Selection Guide Sorted by Product Function

Chapter 3 — Reliability Audit Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Explanation of On Semiconductor’s Outgoing Product Performance Audit Program

Chapter 4 — B and UB Series Family Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Explanation of Standardized Specifications for the Product Family

Chapter 5 — CMOS Handling and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Protection Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Propagation Delay and Rise Time versus Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CMOS Latch Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 6 — CMOS Logic Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

See the Master Index for Page Numbering Information

Chapter 7 — CMOS Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Basic Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Optimizing the Long Term Reliability of Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 8 — Equivalent Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 9 — Packaging Information Including Surface Mounts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ON Semiconductor Major Worldwide Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ON Semiconductor Standard Document Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .



ALExIS, Bullet–Proof, CHIPSCRETES, Designer’s, DUOWATT, E–FET, EASY SWITCHER, ECL300, ECECLinPS Plus, ELite, EpiBase, Epicap, EZFET, FULLPAK, GEMFET, ICePAK, L2TMOS, MCCS, MDTL,

MHTL, MiniMOS, MiniMOSORB, Mosorb, MRTL, MTTL, Multi–Pak, ON–Demand, PowerBase,

SCANSWITCH, SENSEFET, SLEEPMODE, SMALLBLOCK, SMARTDISCRETES, SMARTswitc

SuperLock, Surmetic, SWITCHMODE, Thermopad, Thermowatt, TMOS, TMOS & Design Device, TM

UNIT/PAK, Uniwatt, WaveFET, Z–Switch and ZIP R TRIM are trademarks of Semiconductor Compo

(SCILLC).

HDTMOS and HVTMOS are registered trademarks of Semiconductor Components Industries, LLC (SC

All other brand names and product names appearing in this publication are registered trademarks o

respective holders.



CH

Mas



MASTER INDEX

Device Function

MC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . .

MC14008B 4–Bit Full Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14014B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14021B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . .

MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . .

MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14046B Phase–Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14051B 8–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . . .

MC14052B Dual 4–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . .MC14053B Triple 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . .

MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14067B 16–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . . . . . .



Device Function

MC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . .

MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14106B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14490 Hex Contact Bounce Eliminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . .

MC14512B 8–Channel Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . .

MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . .

MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . .

MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . .

MC14528B Dual Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14538B Dual Precision Monostable Multivibrator . . . . . . . . . . . . . . . . . . . . . . . . MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . .

MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . .

MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . .

MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . .

MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . .

MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14562B 128–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14569B Programmable Dual 4–Bit Binary/BCD Down Counter . . . . . . . . . . . . .

MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .



CH

Product Select



CMOS Selection Guide by Function

Device Function

NAND Gates

MC14011B Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14011UB Quad 2–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14093B Quad 2–Input NAND Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14023B Triple 3–Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOR GatesMC14001B Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14001UB Quad 2–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14025B Triple 3–Input NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AND GatesMC14081B Quad 2–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14073B Triple 3–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14082B Dual 4–Input AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Complex Gates

MC14070B Quad Exclusive OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14077B Quad Exclusive NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14572UB Hex Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Inverters/Buffers/Level TranslatorMC14007UB Dual Complementary Pair Plus Inverter . . . . . . . . . . . . . . . . . . . . . . . . . MC14049B Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14049UB Hex Inverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14050B Hex Noninverting Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14069UB Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14503B Hex 3–State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14504B TTL or CMOS to CMOS Hex Level Shifter . . . . . . . . . . . . . . . . . . . . . . MC14584B Hex Schmitt Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Decoders/EncodersMC14028B BCD–to–Decimal/Binary–to–Octal Decoder . . . . . . . . . . . . . . . . . . . . . MC14511B BCD–to–7–Segment Latch/Decoder/Driver . . . . . . . . . . . . . . . . . . . . . . MC14513B BCD–to–7–Segment Latch/Decoder/Driver with Ripple Blanking . . . .MC14543B BCD–to–7–Segment Latch/Decoder/Driver for Liquid Crystals . . . . . .MC14514B 4–Bit Transparent Latch/4–to–16 Line Decoder (High) . . . . . . . . . . . . .MC14515B 4–Bit Transparent Latch/4–to–16 Line Decoder (Low) . . . . . . . . . . . . .MC14532B 8–Bit Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14555B Dual Binary to 1–of–4 Decoder (Active High Outputs) . . . . . . . . . . . . .MC14556B Dual Binary to 1–of–4 Decoder (Active Low Outputs) . . . . . . . . . . . . . .

Multiplexers/Demultiplexers/Bilateral Switches

MC14016B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14066B Quad Analog Switch/Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14551B Quad 2–Channel Analog Multiplexer/Demultiplexer . . . . . . . . . . . . . . .MC14053B T i l 2 Ch l A l M lti l /D lti l



Device Function

OR Gates

MC14071B Quad 2–Input OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flip–Flops/Latches

MC14042B Quad Transparent Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14043B Quad NOR R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14044B Quad NAND R–S Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14076B Quad D–Type Register with Tri–State Outputs . . . . . . . . . . . . . . . . . . . .MC14175B Quad D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14013B Dual D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14027B Dual J–K Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14174B Hex D Flip–Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14099B 8–Bit Addressable Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14598B 8–Bit Bus–Compatible Addressable Latch . . . . . . . . . . . . . . . . . . . . . . .

Shift Registers

MC14015B Dual 4–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14517B Dual 64–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14562B 128–Bit Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14557B 1–to–64 Bit Variable Length Shift Register . . . . . . . . . . . . . . . . . . . . . . . MC14014B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14021B 8–Bit Static Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MC14094B 8–Stage Shift/Store Register with Tri–State Outputs . . . . . . . . . . . . . . .MC14549B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14559B Successive Approximation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Counters

MC14017B Decade Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14018B Presettable Divide–by–N Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14020B 14–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14022B Octal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14024B 7–Stage Ripple Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14029B Presettable Binary/BCD Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . MC14040B 12–Bit Binary Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14060B 14–Bit Binary Counter and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14516B Presettable Binary Up/Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14518B Dual BCD Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14520B Dual Binary Up Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14526B Presettable 4–Bit Binary Down Counter . . . . . . . . . . . . . . . . . . . . . . . . . MC14553B 3–Digit BCD Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14569B Programmable Dual 4–Bit Binary/BCD Counter . . . . . . . . . . . . . . . . . .

Oscillators/TimersMC14521B 24–Stage Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14536B Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC14541B Programmable Oscillator/Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multivibrators



CH

Reliability Audit



Reliability Audit Program

For Logic Integrated Circuits

1.0 INTRODUCTIONThe Reliability Audit Program developed in March 1977

is the ON Semiconductor internal reliability audit which isdesigned to assess outgoing product performance underaccelerated stress conditions. Logic Reliability Engineering

has overall responsibility for RAP, including updating itsrequirements, interpreting its results, administration atoffshore locations, and monthly reporting of results. Thesereports are available at all sales offices. Also available is the

“Reliability and Quality Handbook” wall ON Semiconductor devices (HBD

RAP is a system of environmentaperformed periodically on randomly

standard products. Each sample receiin section 2.0. Frequency of testing isdocument 12MRM15301A.



Pull 500* piece sample from lot following Group A

acceptance.

2.0 RAP TEST FLOW

#One sample per month for FAST, LS, 10H, 10K, MG CMOS, and HSL CMOS.

* PTHB or PTH not required for hermetic products: reduce total sample size to 450 pcs.

**Seal (Fine & Gross Leak) required only for hermetic products.

***PTH to be used when sockets for PTHB are not available.

PTHB

48 HRS

45* 340

PTH***

48 HRS

INITIAL

SEAL**

TEMP CYCLES

40 CYCLES

SCRAP

INTERIMTEST

ADD 460 CYCLES

INTERIM

TEST

ADD 500 CYCLES

FINALINTERIM*

TEST

TEMP CYCLES#

1000 CYCLES

(ADDITIONAL)

FINALELECTRICAL

& SEAL**

(2000 CYCLES)

FINAL

ELECTRICAL

(96 HRS)

FINAL

ELECTRICAL

(48 HRS)

PTH

48 HRS

(ADDITIONAL)

INTERIM

ELECTRICAL

SCRAP

3.0 TEST CONDITIONS AND COMMENTS

PTHB — 15 psig/121°C/100% RH at rated VCC or VEE —to be performed on plastic encapsulated devicesonly.

3. Sampling to include all package ty

4. Device types sampled will be by gelogic I/C product family (CMOS



CH

B and UB Series Fa



The CMOS Devices in this volume which have a B or UBsuffix meet the minimum values for the industry–

standardized* family specification. These standardizedvalues are shown in the Maximum Ratings and ElectricalCharacteristics Tables. In addition to a standard minimumspecification for characteristics the B/UB devices feature:

• 3–18 volt operational limits• Capable of driving two low–power TTL loads or one

low–power Schottky TTL load over the ratedtemperature range

• Direct Interface to High–Speed CMOS• Maximum input current of ± 1 µA at 15 volt power

supply over the temperature range• Parameters specified at 5.0, 10, and 15 volt supply• Noise margins: B Series

1.0 V min @ 5.0 V supply2.0 V min @ 10 V supply2.5 V min @ 15 V supply

UB Series

0.5 V min @ 5.0 V supply1.0 V min @ 10 V supply1.0 V min @ 15 V supply

The industry–standardized maximum ratings are shown atthe bottom of this page. Limits for the static characteristicsare shown in two formats: Table 1 is in the industry formatand Table 2 is in the equivalent ON Semiconductor format.The ON Semiconductor format is used throughout this databook. Additional specification values are shown on theindividual data sheets.

Switching characteristics for the B and UB series devicesare specified under the following conditions:

Load Capacitance, CL, of 50 pFInput Voltage equal to VSS – VDD (Rail–to–Railswing)Input pulse rise and fall times of 20 nsPropagation Delay times measured from 50% point of

input voltage to 50% point of output voltageThree different supply voltages: 5, 10, and 15 V

Exceptions to the B and UB Series FamilySpecification

There are a number of devices which have a B or UB suffixwhose inputs and/or outputs vary somewhat from the family

Devices with specialized inputs,inputs, have unique input specifi

Input VoltageThe input voltage specification

worstcase input voltage to produce an“0”. This “1” or “0” output level is dfrom the supply (VDD) and ground (Vsupply, this deviation is 0.5 V; for a 1for 15 V, 1.5 V. As an example, in a deV supply, the device with the input

guaranteed to switch on or before 3.5 to 1.5 V. Switching and not switching0.5 V of the ideal output level for thesupply. The actual switching level rebetween 1.5 V and 3.5 V.

Noise MarginThe values for input voltages an

deviations lead to the calculated n

margin is defined as the difference beVout (output deviation). As an exampbuffer at VDD = 5.0 volts: VIL = 1.5volts. Therefore, Noise Margin equalsThis figure is useful while cascading With the input to the first stage at a wo(VIL = 1.5 V), the output is guarantee0.5 volts with a 5.0 volt supply. allowable logic 0 for the second stag

volt output provides a 1.0 volt margistage.

Output Drive CurrentDevices in the B Series are capable

of 0.36 mA over the temperature rangThis value guarantees that these CMone low–power Schottky TTL input.

B Series vs UB CMOS

The primary difference between Bdevices is that UB series gates and invwith a single inverting stage betweendecreased gain caused by using a singnoise immunity and a transfer characte

The decreased gain is quite useful w



MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol Parameters Value Unit

VDD DC Supply Voltage – 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

Iin, lout Input or Output Current (DC or Transient), per Pin ± 10 mA

PD Power Dissipation, per Package† 500 mW

Tstg Storage Temperature – 65 to + 150 C

TL Lead Temperature (8–Second Soldering) 260 C

* Maximum Ratings are those values values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

VIL = 1.5 V Vout = 0.5 V Vout

5.0 V

FIRST STAGE

(NONINVERTING BUFFER)

SECOND STAGE

(NONINVERTING BUFFER)VIL = 1.5 V

Figure 1.

Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications

ELECTRICAL CHARACTERISTICS

Limits

Tem VDDTLOW* + 25 C

Parameter Range (Vdc) Conditions Min Max Min Max M

IDD Quiescent

Device Current

Mil 5

10

15

Vin = VSS or VDD

0.25

0.5

1.0

0.25

0.5

1.0

GATES Comm 5

10

15

All valid input

combinations

1.0

2.0

4.0

1.0

2.0

4.0

Mil 5

10

15

VIN = VSS or VDD

1.0

2.0

4.0

1.0

2.0

4.0

BUFFERS,

FLIP–FLOPS

Comm 5

1015

All valid input

combinations

4

816

4.0

8.016.0

Mil 5

10

15

VIN = VSS or VDD

5

10

20

5

10

20

MSI Comm 5

10

All valid input

combinations

20

40

20

40

Table 1. EIA/JEDEC Format for CMOS Industry B and UB Series Specifications (con


Limits

ConditionsVDD(Vdc)TempRangeParameter

+ 25 CTLOW*

ConditionsVDD(Vdc)TempRangeParameter MMaxMinMaxMinConditionsVDD(Vdc)TempRangeParameter

VIL Input

Low Voltage#

B Types

All 5

10

15

VO = 0.5V or 4.5V

VO = 1.0V or 9.0V

VO = 1.5V or 13.5V

|IO| < 1 µA

1.5

3.0

4.0

1.5

3.0

4.0

VIL Input

Low Voltage#

UB Types

All 5

10

15

VO = 0.5V or 4.5V

VO = 1.0V or 9.0V

VO = 1.5V or 13.5V

|IO| < 1 µA

1.0

2.0

2.5

1.0

2.0

2.5

VIH InputHigh Voltage#

B Types

All 510

15

VO = 0.5V or 4.5VVO = 1.0V or 9.0V

VO = 1.5V or 13.5V

|IO| < 1 µA

3.57.0

11.0

3.57.0

11.0

37

1

VIH Input

High Voltage#

UB Types

All 5

10

15

VO = 0.5V or 4.5V

VO = 1.0V or 9.0V

VO = 1.5V or 13.5V

|IO| < 1 µA

4.0

8.0

12.5

4.0

8.0

12.5

4

8

12

IOL Output Low

(Sink) CurrentMil 5

10

15

VO = 0.4V,

VIN = 0 or 5V

VO = 0.5V,VIN = 0 or 10V

VO = 1.5V,

VIN = 0 or 15V

0.64

1.6

4.2

0.51

1.3

3.4

0.

0

2

Com 5

10

15

VO = 0.4V,

VIN = 0 or 5V

VO = 0.5V,

VIN = 0 or 10V

VO = 1.5V,

VIN = 0 or 15V

0.52

1.3

3.6

0.44

1.1

3.0

0.

0

2

IOH Output High(Source) Current

Mil5

10

15

VO = 4.6V,VIN = 0 or 5V

VO = 9.5V,

VIN = 0 or 10V

VO = 13.5V,

VIN = 0 or 15V

– 0.25

– 0.62

– 1.8

– 0.2

– 0.5

– 1.5

– 0

– 0

–

Com

5

10

15

VO = 4.6V,

VIN = 0 or 5V

VO = 9.5V,

VIN = 0 or 10V

VO = 13.5VVIN = 0 or 15V

– 0.2

– 0.5

– 1.4

– 0.16

– 0.4

– 1.2

– 0

–

–

IIN Input Current Mil

Comm

15

15

VIN = 0 or 15V

VIN = 0 or 15V

± 0.1

± 0.3

± 0.1

± 0.3

Ioz 3–State Output

Leakage Current

Mil

Comm

15

15

VIN = 0 or 15V

VIN = 0 or 15V

± 0.4

± 1.6

± 0.4

± 1.6



Table 2. ON Semiconductor Format for CMOS Industry B and UB Series Specificat


VDD – 55 C 25 C

Characteristic Symbol Vdc Min Max Min Max M

Output Voltage “0” LevelVin = VDD or 0

VOL 5.010

15

— —

—

0.050.05

0.05

— —

—

0.050.05

0.05

— —

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

—

—

—

4.

9.

14

Input Voltage B Types “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

1.5

3.0

4.0

—

—

—

“1” Level(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

—

—

—

3

7

1

Input Voltage UB Types “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.0

2.0

2.5

—

—

—

1.0

2.0

2.5

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH

5.0

1015

4.0

8.012.5

—

— —

4.0

8.012.5

—

— —

4

812

Output Drive Current B Gates

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

—

—

—

—

–

– 0

– 0

– 2

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

—

—

—

0.

0

2

Output Drive Current UB Gates(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH5.0

5.0

10

15

– 1.2

– 0.25

– 0.62

– 1.8

—

—

—

—

– 1.0

– 0.2

– 0.5

– 1.5

—

—

—

—

– 0

– 0

– 0

–


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

—

—

—

0.

0

2

Output Drive Current Other Devices


(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)

IOH

5.0

1015

– 0.64

– 1.6 – 4.2

—

— —

– 0.51

– 1.3 – 3.4

—

— —

– 0

– 0 – 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

—

—

—

0.

0

2

Input Current Iin 15 — ± 0.1 — ± 0.1 —

Input Capacitance (Vin = 0) Cin — — — — 7.5 —



HANDLING PRECAUTIONS

All MOS devices have insulated gates that are subject tovoltage breakdown. The gate oxide for ON SemiconductorCMOS devices is about 900 Å thick and breaks down at agate–source potential of about 100 volts. To guard againstsuch a breakdown from static discharge or other voltagetransients, the protection networks shown in Figures 1A and1B are used on each input to the CMOS device.

Static damaged devices behave in various ways,depending on the severity of the damage. The most severelydamaged inputs are the easiest to detect because the inputhas been completely destroyed and is either shorted to VDD,shorted to VSS, or open–circuited. The effect is that thedevice no longer responds to signals present at the damagedinput. Less severe cases are more difficult to detect becausethey show up as intermittent failures or as degradedperformance. Another effect of static damage is that theinputs generally have increased leakage currents.

Although the input protection network does provide agreat deal of protection, CMOS devices are not immune tolarge static voltage discharges that can be generated duringhandling. For example, static voltages generated by a personwalking across a waxed floor have been measured in the4–15 kV range (depending on humidity, surface conditions,etc.). Therefore, the following precautions should beobserved:

1. Do not exceed the Maximum Ratings specified by thedata sheet.

2. All unused device inputs should be connected to VDDor VSS.

3. All low–impedance equipment (pulse generators,etc.) should be connected to CMOS inputs only afterthe device is powered up. Similarly, this type of equipment should be disconnected before power isturned off.

4. Circuit boards containing CMOS devices are merelyextensions of the devices, and the same handlingprecautions apply. Contacting edge connectors wireddirectly to device inputs can cause damage. Plasticwrapping should be avoided. When externalconnections to a PC board are connected to an input of

a CMOS device, a resistor showith the input. This resistor h

damage if the PC board is remcontact with static generating mfactor for the series resistor is thcaused by the time constant resistor and input capacitance. Ninput rise and fall times shoulFigure 2, two possible networseries resistor to reduce Discharge) damage. For conven

added propagation delay and riseries resistance size is given.

5. All CMOS devices should be smaterials that are antistatic. CMbe inserted into conventiostyrofoam, or plastic trays, butoriginal container until ready f

6. All CMOS devices should be bench surface and operat

themselves prior to handling decan be statically charged withsurface. Wrist straps in contactrecommended. See Figure 3 typical work station.

7. Nylon or other static generatincome in contact with CMOS de

8. If automatic handlers are beinstatic electricity may be genera

of the device, the belts, or the build–up by using ionized ahumidifiers. All parts of machcontact with the top, bottom, omust be grounded to metal material.

9. Cold chambers using CO2 foequipped with baffles, and the Ccontained on or in conductive m

10. When lead–straightening ornecessary, provide ground strused and be sure that soldering

INPUT PROTECTION NETWORK

Figure 1a. Input Protection Network

Double Diode

Figure 1b. Input Prot

Triple Dio

VDD VDD

CMOS

INPUTTO CIRCUIT

<1500 Ω

VSS

CMOS

INPUT300 Ω

11. The following steps should be observed during wavesolder operations:a. The solder pot and conductive conveyor system of

the wave soldering machine must be grounded toan earth ground.

b. The loading and unloading work benches should

have conductive tops which are grounded to anearth ground.

c. Operators must comply with precautionspreviously explained.

d. Completed assemblies should be placed inantistatic containers prior to being moved tosubsequent stations.

12. The following steps should be observed duringboard–cleaning operations:

a. Vapor degreasers and baskets must be grounded toan earth ground.

b. Brush or spray cleaning should not be used.c. Assemblies should be placed into the vapor

degreaser immediately upon removal from theantistatic container.

d. Cleaned assemblies should be placed in antistaticcontainers immediately after removal from thecleaning basket.

e. High velocity air movement or application of solvents and coatings should be employed onlywhen assembled printed circuit boards aregrounded and a static eliminator is directed at theboard.

13. The use of static detection metsurveillance is highly recomme

14. Equipment specifications shopresence of CMOS devfamiliarization with this spperforming any kind of mainte

of devices or modules.15. Do not insert or remove CMO

sockets with power applied. Chto be used for testing devices tovoltage transients present.

16. Double check test equipment seof VDD and VSS before condfunctional testing.

17. Do not recycle shipping rails o

causes deterioration of their an

RECOMMENDED FOR READING

“Total Control of the Static in You

Available by writing to:3M Company

Static Control SystemsP.O. Box 2963Austin, Texas 78769–2963

Or by Calling:1–800–328–1368

Figure 2. Networks for Minimizing ESD and Reducing

CMOS Latch Up Susceptibility

TO OFF–BOARD

CONNECTION

R1CMOS

INPUT

OR

OUTPUT

TO OFF–BOARD

CONNECTION

R2

Advantage:

Disadvantage:

Requires minimal board area

R1 > R2 for the same level of

protection, therefore rise and fall

times, propagation delays, and output

drives are severely affected.

Advantage:

Disadvantage:

R2 < R1 for the same

level of protection.

Impact on ac and dc

characteristics is minimize

More board area, higher i

Note: These networks are useful for protecting the following

A

B

digital inputs and outputs

analog inputs and outputs

C

D

3–state outputs

bidirectional (I/O) ports

PROPAGATION DELAY AND RISE TIME

vs. SERIES RESISTANCE

Rt

C kwhere:

R

t

C

k

k

= the maximum allowable series resistance in ohms

= the maximum tolerable propagation delay or rise time in seconds

= the board capacitance plus the driven device’s

= input capacitance in farads= 0.7 for propagation delay calculations

= 2.3 for rise time calculations



Figure 3. Typical Manufacturing Work Station

RESISTOR =1 MEGAOHM

1

2

3

4

5

NOTES: 1. 1/16 inch conductive sheet

top work area.

2. Ground strap.

3. Wrist strap in contact with s

4. Static neutralizer. (Ionized

work.) Primarily for use in

grounding is impractical.

5. Room humidifier. Primarily

the relative humidity is les

building heating and coolin

the air causing the relativ

buildings to be less than ou

POWER SUPPLIES

CMOS devices have low power requirements and theability to operate over a wide range of supply voltages.These two characteristics allow CMOS designs to beimplemented using inexpensive, conventional powersupplies, instead of switching power supplies and powersupplies with cooling fans. In addition, batteries may be usedas either a primary power source or for emergency backup.

The absolute maximum power supply voltage for 14000Series Metal–gate CMOS is 18.0 Vdc. Figure 4 offers someinsight as to how this specification was derived. In thefigure, VS is the maximum power supply voltage and IS isthe sustaining current of the latch–up mode. The value of VS

was chosen so that the secondary breakdown effect may beavoided.

In an ideal system design, a power supply should bedesigned to deliver only enough current to insure properoperation of all devices. The obvious benefit of this typedesign is cost savings; an added benefit is protection against

the possibility of latch–up related protection can be provided by the powvoltage regulator.

CMOS devices can be used with bat

systems. A few precautions should bebattery–operated systems:1. The recommended power supp

observed. For battery backup syin Figure 5, the battery voltagVolts (3 Volts from the minvoltage and 0.7 Volts to accouacross the series diode).

2. Inputs that might go above the b

should either use a series resicurrent to less than 10 mA or usMC14050B high–to–low volta

3. Outputs that are subject to voltor below VSS should be protecteto limit the current to less tclamping diodes.

IDD

LATCH

UP MODE

Figure 5. Battery Backup Interface

POWER SUPPLY

LINE POWER ONLY

SYSTEM

CMOS

SYSTEM

MC14049UB

MC14050B

BATTERY BACKUP

SYSTEM

MC14049UB

MC14050B

BATT

R

CMOS

SYSTEM

INPUTS

All inputs, while in the recommended operating range(VSS < Vin < VDD) can be modeled as shown in Figure 6. Forinput voltages in this range, diodes D1 and D2 are modeledas resistors, representing the reverse bias impedance of the

diodes. The maximum input current is worst case, 1 µA,when the inputs are at VDD or VSS, and VDD = 15.0 V. Thismodel does not apply to inputs with pull–up or pull–downresistors.

Figure 6. Input Model for VSS Vin VDD

VDD

R1

7.5 pF

R1 = R2 = HIGH Z

R2

When left open–circuited, the inputs may self–bias at ornear the typical switchpoint, where both the P–channel andN–channel transistors are conducting, causing excessivecurrent drain Due to the high gain of the inverters (see

Figure 7. Typical Transfer C

for Buffered Devic

5.0

4.0

3.0

2.0

1.0

00 1.0 2.0 3.0 4.0

Vin, INPUT VOLTAG

V o u t ,

O U T P U T V O

L T A G E ( V )

VDD = 5.0 Vd

SINGLE INPUT N

MULTIPLE INPUT

SINGLE INP

MULTIPLE

For these reasons, all unused inputeither to VDD or VSS. For applicationedge connectors, a 100 kilohm resisused, as well as a series resistor forcurrent limiting (Figure 8). The 100 ki

eliminate any static charges that mprinted circuit board. See Figure protection arrangements.

RSFROM

EDGE

CONNECTOR

For input voltages outside of the recommended operatingrange, the CMOS input is modeled as in Figure 9. Theresistor–diode protection network allows the user greaterfreedom when designing a worst case system. The deviceinputs are guaranteed to withstand voltages from VSS – 0.5

V to VDD + 0.5 V and a maximum current of 10 mA. Withthe above input ratings, most designs will require no specialterminations or design considerations.

Figure 9. Input Model for Vin > VDD or Vin < VSS

1.5 k

D2 7.5 pF

D1

Other specifications that should be noted are themaximum input rise and fall times. Figure 10 shows the

oscillations that may result from exceeding the 15 µsmaximum rise and fall time at VDD = 5.0 V, 5 µs at 10 V, or4 µs at 15 V. As the voltage passes through the switchingthreshold region with a slow rise time, any noise that is onthe input is amplified, and passed through to the output,causing oscillations. The oscillation may have a low enoughfrequency to cause succeeding stages to switch, givingunexpected results. If input rise or fall times are expected toexceed 15 µs at 5.0 V, 5 µs at 10 V, or 4 µs at 15 V,

Schmitt–trigger devices such as the MC14093B,MC14584B, MC14106B, HC14, or HC132 arerecommended for squaring–up these slow transitions.

Vin

Vout

VDD

VSS

VOH

VOL

lout = 0µA. The output drives for all buare such that 1 LSTTL load can be temperature range.

CMOS outputs are limited to extvoltages of VSS – 0.5 V Vout

voltages are forced outside of this rangrectifier (SCR) formed by parasititriggered, causing the device to information on this, see the explanatioin this section.

The maximum rated output curren10 mA. The output short–circuit curtypically exceed these limits. Care exceed the maximum ratings found o

For applications that require drivingwhere fast propagation delays are power MOSFETs), two or more outpmay be externally paralleled.

CMOS LATCH UP

Latch up will not be a problem fordesigner should be aware of it, what prevent it.

Figure 11 shows the cross–sectioinverter and Figure 12 shows the parThe circuit formed by the parasitic tris the basic configuration of a silicon SCR. In the latch up condition, transturned ON, each providing the base cuother to remain in saturation, thereby the ON state. Unlike a conventional Sis turned ON by applying a voltage ttransistor, the parasitic SCR is turnvoltage to the emitter of either transithat trigger the SCR are the same poiTherefore, to latch up the CMOS devmust be greater than VDD + 0.5 V orand have sufficient current to trigger tmechanism is similar for the inputs.

Once a CMOS device is latched upis not limited, the device will be destrsuch occurrences are listed below:

1. Insure that inputs and outpumaximum rated values, as follo–0.5 V ≤ Vin or Vout VDD +VSS) |Iin or Iout| 10 mA (unleon the data sheet)



series resistors may be used in plug–in boardapplications).

4. Voltage regulating or filtering should be used in boarddesign and layout to insure that power–supply linesare free of excessive noise.

5. Limit the available power sdevices that are subject to latccan be accomplished with the pnetwork or with a current–limi

Figure 11. CMOS Wafer Cross Section

VDD VDD

P–CHANNEL N–CHANNEL

INPUT

OUTPUTP–CHANNEL

OUTPUT

N–CHANNEL

OUTPUT

VSS

FIELD OXIDE FIELD OXIDE FIELN+ P+ P+ N+ N+ P+

P – WELLN – SUBSTRATE

Figure 12. Latch Up Circuit Schematic

VSS

VSS

N–CHANNEL OUTPUTN–SUBSTRATE RESISTAN

Q1

N+

P–

P–CHANP–WELL RESISTANCE

N–

P+

P–

N+ N–

P+Q2



CH

CMOS Logic Da



MC14001B, MC14011B, MC14023B,MC14025B, MC14071B, MC14073B,MC14081B, MC14082B

The B Series logic gates are constructed with P and N channelenhancement mode devices in a single monolithic structure(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired.• Supply Voltage Range = 3.0 Vdc to 18 Vdc• All Outputs Buffered• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.• Double Diode Protection on All Inputs Except: Triple Diode

Protection on MC14011B and MC14081B• Pin–for–Pin Replacements for Corresponding CD4000 Series B

Suffix Devices

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range –0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

± 10 mA

PD Power Dissipation,

per Package (Note 2.)

500 mW

TA Ambient Temperature Range –55 to +125 °C

Tstg Storage Temperature Range –65 to +150 °C

TL Lead Temperature

(8–Second Soldering)

260 °C

1. Maximum Ratings are those values beyond which damage to the device

may occur.2. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high–impedance circuit. For proper operation, Vin and Vout should be constrained

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Device D

DEVICE INFO

MC14001B Quad 2–In

MC14011B Quad 2–In

MC14023B Triple 3–In

MC14025B Triple 3 In

PDIP–14

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 75

TSSOP–

DT SUFF

CASE 948

XX = Specific

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

SOEIAJ–

F SUFFI

CASE 96

MC14001B Series



LOGIC DIAGRAMS

1

2

5

6

8

9

1213

3

4

10

11

1

2

5

6

8

9

1213

3

4

10

11

1

2

5

6

8

9

1213

3

4

10

11

1

2

5

6

8

9

1213

2 I N P U T

12 9

3 I N P U T

8

34 65

1112 1013

12 98

34 65

1112 1013

12 98

34 65

1112 1013

345

2

101112

9

VDD = PIN 14

VSS = PIN 7

FOR ALL DEVICES

NOR

MC14001B

Quad 2–Input NOR Gate

MC14025B

Triple 3–Input NOR Gate

MC14023B

Triple 3–Input NAND Gate

NAND

MC14011B

Quad 2–Input NAND Gate

OR

MC14071B

Quad 2–Input OR Gate Quad

MC14073B

Triple 3–Input AND Gate Dua

PIN ASSIGNMENTS

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

141 VIN 1 141 VIN 1 141 VIN 1 OUT

MC14023BTriple 3–Input NAND GateMC14001BQuad 2–Input NOR Gate MC14011BQuad 2–Input NAND Gate

Dual 4

MC14081B

Quad 2–Input AND Gate

Triple

MC14071B

Quad 2–Input OR GateMC14073B

Triple 3–Input AND Gate

MC14001B Series



ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD – 55 C 25 C

Characteristic Symbol Vdc Min Max Min Typ (3.) Max M

Output Voltage “0” Level

Vin = VDD or 0

VOL 5.0

1015

—

— —

0.05

0.050.05

—

— —

0

00

0.05

0.050.05

—

— —

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—


(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1

Output Drive Current


(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

–

–


(VOL = 0.5 Vdc)(VOL = 1.5 Vdc)

IOL 5.0

1015

0.64

1.64.2

—

— —

0.51

1.33.4

0.88

2.258.8

—

— —

0.

02

Input Current Iin 15 — ± 0.1 — ±0.00001 ± 0.1 —

Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

0.25

0.5

1.0

—

—

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

—

—

Total Supply Current (4.) (5.)

(Dynamic plus Quiescent,

Per Gate, CL = 50 pF)

IT

5.0

10

15

IT

= (0.3 µA/kHz) f + IDD

/N

IT = (0.6 µA/kHz) f + IDD /N


3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe4. The formulas given are for the typical characteristics only at 25 C.5. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the nu

per package.

MC14001B Series



B–SERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25 C)

Characteristic Symbol

VDD

Vdc Min Typ (7.)

Output Rise Time, All B–Series Gates

tTLH = (1.35 ns/pF) CL + 33 ns


tTLH = (0.40 ns/PF) CL + 20 ns

tTLH

5.0

10

15

—

—

—

100

50

40

Output Fall Time, All B–Series Gates

tTHL = (1.35 ns/pF) CL + 33 ns



tTHL

5.0

10

15

—

—

—

100

50

40

Propagation Delay Time

MC14001B, MC14011B only

tPLH, tPHL = (0.90 ns/pF) CL + 80 ns



All Other 2, 3, and 4 Input Gates




8–Input Gates (MC14068B, MC14078B)


tPLH

, tPHL

= (0.36 ns/pF) CL

+ 62 ns


tPLH, tPHL

5.0

10

15

5.0

10

15

5.0

10

15

—

—

—

—

—

—

—

—

—

125

50

40

160

65

50

200

80

60

6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe

VDD14

CL

VSS7

PULSEGENERATOR

INPUT

OUTPUT

90%50%

10%

10%50%

90%

20 ns 2

tPHL

tTHL

INPUT

OUTPUT

INVERTING

*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to VSS.

90%50%10%

OUTPUT

NON–INVERTING

tTLH

tPLH

*

Figure 1. Switching Time Test Circuit and Waveforms

MC14001B Series

CIRCUIT SCHEMATIC



CIRCUIT SCHEMATICNOR, OR GATES

14

*

7VSS

3, 4, 10, 11

VDD

VSS

VDD

*Inverter omitted in MC14001B

1, 6, 8, 13

2, 5, 9, 12

1, 3, 11

2, 4, 12

VSS

VDD

VSS

VDD

8, 5, 13

MC14001B, MC14071B

One of Four Gates Shown

MC14025B

One of Three Gates

*Inverter omitted

CIRCUIT SCHEMATICNAND, AND GATES

*

*Inverter omitted in

14

*

9, 6, 10

VDD2, 5, 9, 12

1, 6, 8, 13

2, 4, 12

1, 3, 11

VDD

VDD

VSS

8, 5, 13

MC14011B, MC14

One of Four Gates

MC14023B, MC14073B

One of Three Gates Shown

MC14001B Series

TYPICAL B SERIES GATE CHARACTERISTICS



TYPICAL B–SERIES GATE CHARACTERISTICS

N–CHANNEL DRAIN CURRENT (SINK) P–CHANNEL DRAIN CURR

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = –

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00

VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

– 1.0

00

TA = – 55°C

Figure 4. VGS = 10 Vdc Figure 5. VGS = –

16

14

12

10

8.0

6.0

4.0

2.0

05.03.01.0 108.06.04.02.00

00

– 40°C

+ 25°C+ 85°C

+ 125°C

– 1.0 – 3 – 2.0

VDS, DRAIN–TO–SOURCE V

TA

= – 55°C

– 40°C

+ 25°C+ 85°C

+ 125°C

VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) VDS, DRAIN–TO–SOURCE V

18

20

9.07.0 – 5.0 – 3.0 – 1.0 – 6 – 4.0 – 2.0

– 40

– 35

– 30

– 25

– 20

– 15

– 10

– 5.0

– 45

– 50

TA = – 55°C

– 40°C

+ 25°C+ 85°C

– 80 – 70

– 60

– 50

– 40

– 90

– 100

4035

30

25

20

45

50

TA

– 2.0

– 3.0

– 4.0

– 5.0

– 6.0

– 7.0

– 8.0

– 9.0

– 10

I ,

D

D R A I N C U R R E N T ( m A )

I ,

D


I ,

D


I ,

D


A I N C U R R E N T ( m A )

A I N C U R R E N T ( m A )

+ 125°C

MC14001B Series

TYPICAL B SERIES GATE CHARACTERISTICS (cont’d)



TYPICAL B–SERIES GATE CHARACTERISTICS (cont d)

VOLTAGE TRANSFER CHARACTERISTICS

Figure 8. VDD = 5.0 Vdc Figure 9. VDD =

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00

00

Vin, INPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

SINGLE INP

MULTIPLE I

SINGLE

MULTIPL

2.0

6.0

10

8.0

4.0

2.0 6.0 8.04.0

Vin, INPUT VOLTAG

V

,

o u t

O U T P U T V O L T A G E ( V d c )

V

,

o u t


Figure 10. VDD = 15 Vdc

00

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

2.0

6.0

10

8.0

4.0

2.0 6.0 108.04.0


12

14

16

V

,

o u t

O U T P U T V O L T A G E ( V d

c )

DC NOISE MARG

The DC noise margin is defined as t

from an ideal “1” or “0” input level woutput state change(s). The typical values of the input values VIL and Vbe at a fixed voltage VO are givCharacteristics table. VIL and VIH arein Figure 11.

Guaranteed minimum noise margin“0” levels =

1.0 V with a 5.0 V supply



Vout

VO

VO

VDD

VDD Vout

VO

VO

VDD

VDD

MC14001B Series

ORDERING & SHIPPING INFORMATION: ORDERING & SHIPPING INFORMA



ORDERING & SHIPPING INFORMATION:

Device Package Shipping

MC14001BCP PDIP–14 2000 Units per Box

MC14001BD SOIC–14 2750 Units per Box

MC14001BDR2 SOIC–14 2500 Units / Tape & Reel

MC14001BDT TSSOP–14 96 Units per Rail

MC14001BDTR2 TSSOP–14 96 Units per Rail





MC14011BDTEL TSSOP–14 2000 Units / Tape & Reel

MC14011BDTR2 TSSOP–14 50 Units per Rail







ORDERING & SHIPPING INFORMA

Device Package

MC14071BCP PDIP–14

MC14071BD SOIC–14

MC14071BDR2 SOIC–14 250

MC14071BDT TSSOP–14

MC14071BDTR2 TSSOP–14


MC14073BD SOIC–14

MC14073BDR2 SOIC–14 250


MC14081BD SOIC–14

MC14081BDR2 SOIC–14 250


MC14081BDTR2 TSSOP–14 250


MC14082BD SOIC–14

MC14082BDR2 SOIC–14 250

For ordering information on the EIAJ versages, please contact your local ON Semitive.



The UB Series logic gates are constructed with P and N channelenhancement mode devices in a single monolithic structure(Complementary MOS). Their primary use is where low powerdissipation and/or high noise immunity is desired. The UB set of CMOS gates are inverting non–buffered functions.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc•

Linear and Oscillator Applications• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range

• Double Diode Protection on All Inputs• Pin–for–Pin Replacements for Corresponding CD4000 Series UB

Suffix Devices





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA

PD

Power Dissipation,


500 mW



TL Lead Temperature


260 °C

1. Maximum Ratings are those values beyond which damage to the devicemay occur.

2. Temperature Derating:






to the range VSS (Vin or Vout) VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e g

http://onsem

PDIP–14P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 75

XX = Specific

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14001UBCP PDIP–1

MC14001UBD SOIC–1

MC1400

Quad 2–InputMC1401

Quad 2–Input

MC14001UB, MC14011UB

LOGIC DIAGRAMS



MC14001UB

Quad 2–Input

NOR Gate

MC14011UB

Quad 2–Input

NAND Gate

VDD = PIN 14VSS = PIN 7

FOR ALL DEVICES

13

12

9

8

6

5

21 3

4

10

1113

129

86

521 3

4

10

11

PIN ASSIGNMENTS

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

MC14001UBQuad 2–Input NOR Gate

MC14011UBQuad 2–Input NAND Gate





VDD – 55 C 25 C



Vin

= VDD

or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

Vin = 0 or VDD “1” Level VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4

9

14


(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

VIL

5.0

10

15

—

—

—

1.0

2.0

2.5

—

—

—

2.25

4.50

6.75

1.0

2.0

2.5

—

—

—

(VO

= 0.5 Vdc) “1” Level

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

IIH

5.0

10

15

4.0

8.0

12.5

—

—

—

4.0

8.0

12.5

2.75

5.50

8.25

—

—

—

4

8

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 1.2

– 0.25

– 0.62

– 1.8

—

—

—

—

– 1.0

– 0.2

– 0.5

– 1.5

– 1.7

– 0.36

– 0.9

– 3.5

—

—

—

—

–

– 0

– 0

–


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0

0

2

Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 —

Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

0.25

0.5

1.0

—

—

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

—

—



Per Gate CL = 50 pF)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the nu

per package.






VDD

Vdc Min Typ (7.)

Output Rise Time


tTLH = (1.5 ns/pF) CL + 15 nstTLH = (1.1 ns/pF) CL + 10 ns

tTLH

5.0

1015

—

— —

180

9065

Output Fall Time


tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 9.5 ns

tTHL

5.0

10

15

—

—

—

100

50

40





tPLH, tPHL

5.0

10

15

—

—

—

90

50

40



VDD

14

VSS

OUTPUT

CL

INPUT

*

7

PULSEGENERATOR

20 ns

INPUT

OUTPUT

INVERTING

tPHL

90%50%

10%

90%50%

10%

tTHL*All unused inputs of AND, NAND gates must be

connected to VDD.

All unused inputs of OR, NOR gates must be

connected to VSS.


MC14001UB CIRCUIT SCHEMATIC MC14011UB CIRCUIT

(1/4 of Device S



14 103

VDD

6

5

2

1

VSS

4 7 11

12

13

9

8

(1/4 of Device S

2, 5, 9, 12

1, 6, 8, 13

7 V

14 V

Figure 2. Typical Voltage and

Current Transfer Characteristics

Figure 3. Typical Voltage Transfe

Characteristics versus

Temperature

V o u t ,

O U T P U T V O L T A

G E ( V d c )

16

14

12

10

8.0

6.0

4.0

2.0

00 2.0 4.0 6.0 8.0 10 12 14 16

8.0

6.0

4.0

2.0

0

I D ,

D R A I N C U R R E N T

( m A d c )


V o u t ,

O U T P U T V O L T A

G E ( V d c )

16

14

12

10

8.0

6.0

4.0

2.0

00 2.0 4.0 6.0 8.0 10 12 14 16


A I N C U R R E N T ( m A d c

)

– 6.0

– 4.0

– 2.0

0

A I N C U R R E N T ( m A d c

)

4.0

6.0

8.0

10

TA = –55°C

TA = +25°C

TA = +125°C

a

b

c

VGS = –5.0 Vdcb

c

a

c

a

b

c a

b

c

VGS = 1

15 Vdc

VDD = 15 Vdc

TA = +125°CTA = –55°Cab

a

b

TA = +25°C

Unused input

connected to

VSS.

One input only

Both inputs10 Vdc

5.0 Vdc

b a

b a

b a

15 Vdc

10 Vdc

Unused input

connected to

VSS.

VDD = 15 Vdc

ba

a b

a b

5.0 Vdc

10 Vdc



The MC14007UB multi–purpose device consists of threeN–channel and three P–channel enhancement mode devices packagedto provide access to each device. These versatile parts are useful ininverter circuits, pulse–shapers, linear amplifiers, high inputimpedance amplifiers, threshold detectors, transmission gating, andfunctional gating.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4007A or CD4007UB• This device has 2 outputs without ESD Protection. Anti–static

precautions must be taken.





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C


3. Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C





t th V (V V ) V

http://onsem

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14007UBCP PDIP–

MC14007UBD SOIC–

MC14007UBDR2 SOIC–

PDIP–14

P SUFFIX

CASE 64

SOIC–14

D SUFFIX

CASE 751

TSSOP–1

DT SUFF

CASE 948

SOEIAJ–1

F SUFFIX

CASE 96

MC14007UB

PIN ASSIGNMENT



A

B

C

INPUT

INPUT

A

B

C

12

1

3

5

9

2

4

11

10

14

VDD

6 8

13INPUT OUTPUT CONDITION

11

12

13

14

8

9

105

4

3

2

1

7

6

GATEC

S–PC

OUTC

D–PA

VDD

D–NA

S–NC

S–NB

GATEB

S–PB

D–PB

VSS

GATEA

D–NB

D = DRAIN

S = SOURCE

SCHEMATIC

14 13 2 1 11

126

7 8 3 4 5 10 9

VDD = PIN 14

VSS = PIN 7

MC14007UB


55 C 25 C



VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—


10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

VIL

5.0

10

15

—

—

—

1.0

2.0

2.5

—

—

—

2.25

4.50

6.75

1.0

2.0

2.5

—

—

—

(VO = 0.5 Vdc) “1” Level

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

VIH 5.0

10

15

4.0

8.0

12.5

—

—

—

4.0

8.0

12.5

2.75

5.50

8.25

—

—

—

4

8

12



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 5.0

– 1.0

– 2.5

– 10

—

—

—

—

–

– 0

–

–


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

1.0

2.5

10

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

0.25

0.5

1.0

—

—

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

—

—



Per Gate) (CL = 50 pF)

IT 5.0

10

15

IT = (0.7 µA/kHz) f + IDD /6

IT = (1.4 µA/kHz) f + IDD /6

IT = (2.2 µA/kHz) f + IDD /6


IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.

MC14007UB


V




VDD

Vdc Min Typ (8.)

Output Rise Time



tTLH

5.0

1015

—

— —

90

4535

Output Fall Time




tTHL

5.0

10

15

—

—

—

75

40

30

Turn–Off Delay Time

tPLH = (1.5 ns/pF) CL + 35 ns


tPLH = (0.15 ns/pF) CL + 17.5 ns

tPLH

5.0

10

15

—

—

—

60

30

25

Turn–On Delay Time

tPHL = (1.0 ns/pF) CL + 10 ns



tPHL

5.0

10

15

—

—

—

60

30

25

7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as a8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe

VDD = – VGS VDD = VGS

1414VDS = VOH – VDD

VSSVSS7

7

IOHIO

I O H ,

D R A I N C U

R R E N T ( m A d c )

I O L ,

D R A I N C U

R R E N T ( m A d c )

0

– 4.0

– 8.0

– 12

– 16

20

16

12

8.0

4.0

TA = –55°C

TA = +25°C

TA = +125°C

a

b

c

VGS = – 5.0 Vdc b

c

a

– 10 Vdc – 15 Vdc

c

bc

b

a

a

ab

c

a

b c

ab

c5.0

VGS = 15 Vdc

10 Vdc

All unused inputs connected to ground. All unused inputs connect

MC14007UB

VDD20 ns



Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms

PULSE

GENERATOR

500 µF0.01 µF

CERAMIC

14

CL

Vout

VSS7

Vin

ID Vin

Vout

90%50%10%

90%50%10%

tTHL t

tPHL

APPLICATIONS

The MC14007UB dual pair plus inverter, which hasaccess to all its elements offers a number of unique circuitapplications. Figures 1, 5, and 6 are a few examples of thedevice flexibility.

Figure 5. 3–State Buffer

+ VDD

DISABLE 3

INPUT 10

DISABLE 6

12 OUTPUT

11

1

2

9

8

7

INPUT DISABLE OUTPUT

1

0

X

0

0

1

0

1

OPEN

X = Don’t Care

Figure 6. AOI Functions Usi

VDD

14

13

11

10

3

6

B

C

A

9

5

4

8

7

O

Substrates of P–channel devices intern

Substrates of N–channel devices intern

12



The MC14008B 4–bit full adder is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. This device consists of four full adders with fastinternal look–ahead carry output. It is useful in binary addition andother arithmetic applications. The fast parallel carry output bit allowshigh–speed operation when used with other adders in a system.

• Look–Ahead Carry Output• Diode Protection on All Inputs

• All Outputs Buffered• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4008B

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)Symbol Parameter Value Unit



(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C








Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14008BCP PDIP–

MC14008BDR2 SOIC–

MC14008BF SOEIAJ–

1 For ordering information

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14008B

TRUTH TABLE

(One Stage)



BLOCK DIAGRAM

HIGH–SPEED

PARALLEL CARRY14 Cout

13 S4

12 S3

11 S2

B4 15

A4 1

B3 2

A3 3

B2 4

A2 5

ADDER

4

ADDER

3

ADDER

2

C4

C3

C2

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

S3

S4

Cout

B4

VDD

Cin

S1

S2

B2

A3

B3

A4

VSS

A1

B1

A2

PIN ASSIGNMENT

Cin B A Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 10 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

MC14008B


VDD – 55 C 25 C



VDD



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—


10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.9

9.9

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH 5.0

1015

3.5

7.011

—

— —

3.5

7.011

2.75

5.508.25

—

— —

3

71



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0

2Input Current Iin 15 — ± 0.1 — ±0.00001 ± 0.1 —

Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)(CL = 50 pF on all outputs, all

buffers switching)

IT 5.0

10

15

IT = (1.7 µA/kHz) f + IDD




IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14008B


VDD

Vd (8 )



Characteristic Symbol Vdc Min Typ (8.)

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 nstTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,

tTHL 5.0

1015

—

— —

100

5040


Sum in to Sum Out




Sum In to Carry Out


tPLH, tPHL = (0.66 ns/pF) CL + 112 nstPLH, tPHL = (0.5 ns/pF) CL + 85 ns

Carry In to Sum Out




Carry In to Carry Out




tPLH, tPHL

5.0

10

15

5.0

1015

5.0

10

15

5.0

10

15

—

—

—

—

—

—

—

—

—

—

—

—

400

160

115

305

145110

375

155

115

170

75

55


Figure 1. Typical Source Current

Characteristics Test Circuit

Figure 2. Typical S

Characteristics T

VDD = – VGS Vout

16

B4A4

B3

A3

B2

A2

B1

A1

Cin

S4

S3

S2

S1

Cout

IOH

8 VSS

EXTERNAL

POWERSUPPLY

VDD = VGS

16

B4A4

B3

A3

B2

A2

B1

A1

Cin

S4

S3

S2

S1

Cout

8 VSS

MC14008B

VDD

16



Figure 3. Dynamic Power Dissipation Test Circuit and Waveform

20 ns 20 ns

Vin

90%

10%

VDD

VSSPULSE

GENERATOR

16

B4

A4

B3

A3

B2

A2

B1

A1

Cin

S4

S3

S2

S1

Cout

IDD

8 VSSCL

CL

500 µF

PULSE

GENERATOR

VDD

16

B4

A4

B3

A3

B2

A2

B1

A1

Cin

S4

S3

S2

S1

Cout

IDD

8 VSSCL

CL

CL

CL

CL

20 ns 20 ns

Cin

VDD

VSS

VOH

tPLHtPHL

90%50%10%

90%

MC14008B



Figure 5. Logic Diagram

Cin

A1

B1

A2

B2

A3

B3

A4

B4

WORD A + B INPUTS

A1 B4 A1 B4 A1 B4 A1 B4

Cin Cin Cin CinCout Cout Cout CoCHIP

1

CHIP

2

CHIP

3

CHIP

4

TYPICAL APPLICATION



The MC14013B dual type D flip–flop is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each flip–flop has independent Data, (D), DirectSet, (S), Direct Reset, (R), and Clock (C) inputs and complementaryoutputs (Q and Q). These devices may be used as shift registerelements or as type T flip–flops for counter and toggle applications.

• Static Operation• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Logic Edge–Clocked Flip–Flop Design

Logic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive–goingedge of the clock pulse

• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range

• Pin–for–Pin Replacement for CD4013B





(DC or Transient)

–0.5 to VDD + 0.5 V

Iin

, Iout

Input or Output Current


± 10 mA



500 mW



TL Lead Temperature


260 °C






http://onsem

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14013BCP PDIP–

MC14013BD SOIC–

MC14013BDR2 SOIC–

PDIP–14

P SUFFIX

CASE 64

SOIC–14

D SUFFIX

CASE 751

TSSOP–1

DT SUFF

CASE 948

SOEIAJ–1

F SUFFIX

CASE 96

MC14013B

TRUTH TABLE

Inputs Outputs



Clock† Data Reset Set Q Q

0 0 0 0 1

1 0 0 1 0X 0 0 Q Q

X X 1 0 0 1

X X 0 1 1 0

X X 1 1 1 1

X = Don’t Care

† = Level Change

BLOCK DIAGRAM

10

11

9

8

4

3

5

6

12

13

2

1S

S

R

R

D

C

D

C

Q

Q

Q

Q

11

12

13

14

89

105

4

3

2

1

76

RB

CB

QB

QB

VDD

SB

DB

RA

CA

QA

QA

VSS

SA

DA

PIN ASSIGNMENT

No

Change

MC14013B


VDD – 55 C 25 C


Vdc Min Max Min Typ (4.) Max M





Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—


10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.9

9.9

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH 5.0

1015

3.5

7.011

—

— —

3.5

7.011

2.75

5.508.25

—

— —

3

71



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL

= 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

1.0

2.0

4.0

—

—

—

0.002

0.004

0.006

1.0

2.0

4.0

—

—

—




buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14013B


Characteristic Symbol VDD Min Typ (8.)

Output Rise and Fall Time tTLH,




tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns


tTHL 5.0

10

15

—

—

—

100

50

40


Clock to Q, Q




tPLH

tPHL5.0

10

15

—

—

—

175

75

50

Set to Q, Q




5.0

10

15

—

—

—

175

75

50

Reset to Q, QtPLH, tPHL = (1.7 ns/pF) CL + 265 ns



5.0

10

15

—

—

—

225

100

75

Setup Times (9.) tsu 5.0

10

15

40

20

15

20

10

7.5

Hold Times (9.) th 5.0

10

15

40

20

15

20

10

7.5

Clock Pulse Width tWL, tWH 5.0

10

15

250

100

70

125

50

35

Clock Pulse Frequency fcl 5.0

10

15

—

—

—

4.0

10

14

Clock Pulse Rise and Fall Time tTLH

tTHL

5.0

10

15

—

—

—

—

—

—

Set and Reset Pulse Width tWL, tWH 5.0

10

15

250

100

70

125

50

35

Removal Times

Set

trem

5

10

15

80

45

35

0

5

5

Reset 5

10

15

50

30

25

– 35

– 10

– 57. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe9. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.

LOGIC DIAGRAM (1/2 of Device Shown)

MC14013B

20 ns 20 ns

D90%

50%10%

t (H) tsu (L)

VDD

VSS20 ns 20 ns



Figure 1. Dynamic Signal Waveforms

(Data, Clock, and Output)

Figure 2. Dynamic S

(Set, Reset, Clock

C

Q

tsu (H) tsu (L)

th

tWH tWL

90%50%

10%

VDD

VSS

VOH

VOL

tTLH tTHL

tPHLtPLH

90%50%10%

Inputs R and S low.

1

fcl

SET OR

RESET

CLOCK

Q OR Q

90%50%

10%

20 ns90%

5

50%

tPLH

tPHL

tw

20 ns

TYPICAL APPLICATIONS

n–STAGE SHIFT REGISTER

BINARY RIPPLE UP–COUNTER (Divide–by–2n)

MODIFIED RING COUNTER (Divide–by–(n+1))

D

CLOCK

nth21

D

C

Q

Q

D

C

Q

Q

D

C

Q

Q

CLOCK

nth21

D

C

Q

Q

D

C

Q

Q

D

C

Q

Q

T FLIP–FLOP

nth21

D

C

Q

Q

D

C

Q

Q

D

C

Q

Q



The MC14014B and MC14021B 8–bit static shift registers areconstructed with MOS P–channel and N–channel enhancement modedevices in a single monolithic structure. These shift registers findprimary use in parallel–to–serial data conversion, synchronous andasynchronous parallel input, serial output data queueing; and othergeneral purpose register applications requiring low power and/or highnoise immunity.

• Synchronous Parallel Input/Serial Output (MC14014B)•

Asynchronous Parallel Input/Serial Output (MC14021B)• Synchronous Serial Input/Serial Output• Full Static Operation• “Q” Outputs from Sixth, Seventh, and Eighth Stages• Double Diode Input Protection• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• MC14014B Pin–for–Pin Replacement for CD4014B• MC14021B Pin–for–Pin Replacement for CD4021B




Vin, Vout Input or Output Voltage Range(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature(8–Second Soldering)

260 °C



http://onsem

XX = Specific

A = Assemb

WL or L = Wafer L

YY or Y = YearWW or W = Work W

Device Packa

ORDERING INF

MC14014BCP PDIP–

MC14014BD SOIC–

MC14014BDR2 SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14014BF SOEIAJ

MC14014BFEL SOEIAJ

MC14021BCP PDIP

MC14014B, MC14021B

TRUTH TABLE

Q6 Q7 Q8

t Cl k D P/S t 6 t 7 t 8

SERIAL OPERATION:



t Clock DS P/S t=n+6 t=n+7 t=n+8

n 0 0 0 ? ?

n+1 1 0 1 0 ?n+2 0 0 0 1 0

n+3 1 0 1 0 1

X 0 Q6 Q7 Q8

Clock

MC14014B MC14021B DS P/S Pn *Qn

X X 1 0 0

X X 1 1 1

*Q6, Q7, & Q8 are available externally

PARALLEL OPERATION:

X = Don’t Care

LOGIC DIAGRAM

DS

P/S

P1 P2 P3 P6 P7 P7 6 5 14 15

10

11

9

D

C

Q D

C

Q D

C

Q D

C

Q D

C

Q D

CQ Q

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q7

P5

P6

P7

VDD

P/S

C

DS

P4

Q8

Q6

P8

VSS

P1

P2

P3

MC14014B, MC14021B


VDD – 55 C 25 C






Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—


10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.9

9.9

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH 5.0

1015

3.5

7.011

—

— —

3.5

7.011

2.75

5.508.25

—

— —

3

71



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL

= 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

15

—

—

—

0.005

0.010

0.015

5.0

10

15

—

—

—




buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14014B, MC14021B



VDD

Vdc Min Typ (8.)

O t t Ri d F ll Ti t






tTLH,

tTHL 5.0

1015

—

— —

100

5040

Propagation Delay Time (Clock to Q, P/S to Q)

tPHL, tPLH = (1.7 ns/pF) CL + 315 ns



tPLH,

tPHL 5.0

10

15

—

—

—

400

170

115

Clock Pulse Width tWH 5.0

10

15

400

175

135

150

75

40

Clock Frequency fcl 5.0

10

15

—

—

—

3.0

6.0

8.0

Parallel/Serial Control Pulse Width tWH 5.0

10

15

400

175

135

150

75

40

Setup Time

P/S to Clock

tsu 5.0

10

15

200

100

80

100

50

40

Hold Time

Clock to P/S

th 5.0

10

15

20

20

25

– 2.5

– 10

0

Setup Time

Data (Parallel or Serial) to

Clock or P/S

tsu 5.0

10

15

350

80

60

150

50

30

Hold Time

Clock to Ds

th 5.0

10

15

45

35

35

0

0

5

Hold Time

Clock to Pn

th 5.0

10

15

50

45

45

25

20

20

Input Clock Rise Time tr(cl) 5.0

10

15

—

—

—

—

—

—


PULSE PULSE

VDD Vout

P/SC

Q6

VDD

P/SC

Q6

MC14014B, MC14021B

VDD

500 µF ID

0.01 µF



Figure 3. Power Dissipation Test Circuit and Waveform

PULSEGENERATOR 1

P/S

C

P6P7

P8DS

Q8

Q7

Q6

PULSE

GENERATOR 2

µ

CERAMIC

CL

CL

CL

VSS

P5P4P3

P2P1

CLOCK

DATA

50%

1

f

PULSE

GENERATOR 1

PULSE

GENERATOR 2

VDD1

2

22

1 1

VDD

VSS

SW 1

SW 2

CL

Q8

Q7

Q6P/SC

P6

P7P8

DS

P5

P4P3P2P1

20 ns

PARALLEL ORSERIAL DATA

INPUT

CLOCK OR P/S

INPUT

QOUTPUT

90%50%10%

tsu

tWH

90%50%10%

tWH

tPLH

90%50%10%

tTLH

tWL = tWH = 50

SWITCH POSITION 1 = PARALLEL IN

SWITCH POSITION 2 = SERIAL IN



The MC14015B dual 4–bit static shift register is constructed withMOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. It consists of two identical, independent4–state serial–input/parallel–output registers. Each register hasindependent Clock and Reset inputs with a single serial Data input.The register states are type D master–slave flip–flops. Data is shiftedfrom one stage to the next during the positive–going clock transition.Each register can be cleared when a high level is applied on the Resetline. These complementary MOS shift registers find primary use inbuffer storage and serial–to–parallel conversion where low powerdissipation and/or noise immunity is desired.

• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Logic Edge–Clocked Flip–Flop Design —

Logic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive goingedge of the clock pulse.

• Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range.





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C


http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14015BCP PDIP–

MC14015BD SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFICASE 96

TSSOP–

DT SUFF

CASE 94

MC14015B

TRUTH TABLE

C D R Q0 Qn

0 0 0 Qn–1

1 0 1 Q



1 0 1 Qn–1

X 0 No Change No Change

X X 1 0 0

X = Don’t Care

Qn = Q0, Q1, Q2, or Q3, as applicable.

Qn–1 = Output of prior stage.

BLOCK DIAGRAM

14

1

15

6

9

75

4

3

10

13

12

11

2

Q0

Q1

Q2

Q3

Q0

Q1

Q2

Q3

D

CR

R

D

C

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q1B

Q0B

RB

DB

VDD

CA

Q3A

Q2B

Q1A

Q2A

Q3B

CB

VSS

DA

RA

Q0A

MC14015B


VDD – 55 C 25 C



Output Voltage “0” Level VO 5 0 0 05 0 0 05



Output Voltage 0 Level

Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—


10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.9

9.9

14


(VO = 4.5 or .05 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH 5.0

1015

3.5

7.011

—

— —

3.5

7.011

2.75

5.508.25

—

— —

3

71



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—




buffers switching)

IT 5.0

10

15

IT = (1.2 µA/kHz)f + IDD




IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14015B





tTLH,

tTHL 5.0 — 100





10

15

—

—

50

40


Clock, Data to Q




Reset to Q




tPLH,

tPHL

5.0

10

15

5.0

10

15

—

—

—

—

—

—

310

125

90

460

180

120

Clock Pulse Width tWH

5.0

10

15

400

175

135

185

85

55


10

15

—

—

—

2.0

6.0

7.5

Clock Pulse Rise and Fall Times tTLH, tTHL 5.0

10

15

—

—

—

—

—

—

Reset Pulse Width tWH

5.0

10

15

400

160

120

200

80

60

Setup Time tsu 5.0

10

15

350

100

75

100

50

40

7. The formulas given are for typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe

PULSE

GENERATOR

2

CLOCK 50%

1

f

PULSE

GENERATOR

1

500 µF

VDD

ID0.01 µF

CERAMIC

CL

Q0Q1Q2Q3

D

CR

VSS

CL

CL

CL

VDD

MC14015B

DATA

INPUT

tTLH

tsu

90%50

1



Figure 2. Switching Test Circuit and Waveforms

VDD

CL

VSS

PULSE

GENERATOR2

PULSE

GENERATOR

1

Q0

Q1

Q2

Q3

D

CR

CL

CL

CL

CLOCK

INPUT

tTLH tTH

tWH tW

Q0

tTLH

tPLH tPHL

10

tWL = tWH = 50% Duty Cycle

tTLH = tTHL ≤ 20 ns

SYNC

t –

Figure 3. Setup and Hold Time Test Circuit and Waveforms

VDD

CL

VSS

PULSE

GENERATOR

2

PULSEGENERATOR

1

Q0

Q1

Q2Q3

D

CR

CL

CL

CLSYNC

CLOCK

INPUT

DATA

INPUT

50%

tsu

50%

MC14015B

CIRCUIT SCHEMATICS

F E R T

O D O F

N E X T B I T

C L O C K

O 4 B I T S



A T A I N P U T B U

F F E R

R E S E T I N P U T

B U F F E R

C L O C K

I N P U T B U F F

S I N G L E B I T

Q

V D D

V S S

D A T A

I N

C L O C K

R E S E T

V D D

V D D

V D D

R E S E T

I N

C L O C K

I N

C T O

R E S E T

T O 4 B I T S

D A T A T O

F I R S T B I T

MC14015B

LOGIC DIAGRAMS

SINGLE BIT

C C



DATA

RESET

C

C C

C

C

C C

C

C

C

C

COMPLETE DEVICE

D

C

R

D

C

R14

1

15

6

9

7

DATA INPUT BUFFER

CLOCK INPUT BUFFER

RESET INPUT BUFFER

DATA INPUT BUFFER

CLOCK INPUT BUFFER

RESET INPUT BUFFER

5 4 3Q0 Q1 Q2

D

CR

Q

Q

D

CR

Q

Q

D

CR

Q

Q

D

C

111213Q0 Q1 Q2

D

CR

Q

Q

D

CR

Q

Q

D

CR

Q

Q

D

C



The MC14016B quad bilateral switch is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each MC14016B consists of four independentswitches capable of controlling either digital or analog signals. Thequad bilateral switch is used in signal gating, chopper, modulator,demodulator and CMOS logic implementation.


• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Linearized Transfer Characteristics• Low Noise — 12 nV/ √Cycle, f ≥ 1.0 kHz typical• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved

transfer characteristic design causes more parasitic couplingcapacitance than CD4016)

• For Lower RON, Use The HC4016 High–Speed CMOS Device orThe MC14066B

• This Device Has Inputs and Outputs Which Do Not Have ESDProtection. Antistatic Precautions Must Be Taken.





–0.5 to VDD + 0.5 V

Iin Input Current (DC or Transient)

per Control Pin

± 10 mA

ISW Switch Through Current ± 25 mA



500 mW



TL Lead Temperature


260 °C


http://onsem

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14016BCP PDIP–

MC14016BD SOIC–

MC14016BDR2 SOIC–

MC14016BF SOEIAJ–

PDIP–14

P SUFFIX

CASE 64

SOIC–14

D SUFFIX

CASE 751

SOEIAJ–1

F SUFFIX

CASE 96

1 For ordering information

MC14016BFEL SOEIAJ–

MC14016B

PIN ASSIGNMENT

13

14

2

1

CONTROL 1

VDD

OUT 1

IN 1



BLOCK DIAGRAM

CONTROL 1

IN 1

CONTROL 2

IN 2

CONTROL 3

IN 3

CONTROL 4

IN 4

OUT 1

OUT 2

OUT 3

OUT 4

13

1

5

4

6

8

12

11

2

3

9

10

VDD = PIN 14

VSS = PIN 7

Control Switch

0 = VSS Off

1 = VDD On

11

12

8

9

105

4

3

7

6

OUT 4

IN 4

CONTROL 4

IN 3

OUT 3

IN 2

OUT 2

VSS

CONTROL 3

CONTROL 2

LOGIC DIAGRAM

(1/4 OF DEVICE SHOWN)

CONTROL

OUT

MC14016B


VDD – 55 C 25 C

Characteristic Figure Symbol

Vdc Min Max Min Typ (4.) Max

Input Voltage

Control Input

1 VIL 5.0

10

—

—

—

—

—

—

1.5

1 5

0.9

0 9



Control Input 10

15

—

—

—

—

—

—

1.5

1.5

0.9

0.9VIH 5.0

10

15

—

—

—

—

—

—

3.0

8.0

13

2.0

6.0

11

—

—

—

Input Current Control — Iin 15 — ± 0.1 — ±0.00001 ±0.1

Input Capacitance

Control

Switch Input

Switch Output

Feed Through

— Cin

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

5.0

5.0

5.0

0.2

—

—

—

—

Quiescent Current

(Per Package) (5.)2,3 IDD 5.0

10

15

—

—

—

0.25

0.5

1.0

—

—

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

“ON” Resistance

(VC = VDD, RL = 10 kΩ)

(Vin = + 5.0 Vdc)

(Vin = – 5.0 Vdc) VSS = – 5.0 Vdc

(Vin = ± 0.25 Vdc)

4,5,6 RON

5.0

—

—

—

600

600

600

—

—

—

—

—

300

300

280

660

660

660

(Vin = + 7.5 Vdc)

(Vin = – 7.5 Vdc) VSS = – 7.5 Vdc

(Vin = ± 0.25 Vdc) 7.5

—

—

—

360

360

360

—

—

—

240

240

180

400

400

400

(Vin = + 10 Vdc)

(Vin = + 0.25 Vdc) VSS = 0 Vdc

(Vin = + 5.6 Vdc) 10

—

—

—

600

600

600

—

—

—

260

310

310

660

660

660

(Vin = + 15 Vdc)

(Vin = + 0.25 Vdc) VSS = 0 Vdc

(Vin = + 9.3 Vdc) 15

—

—

—

360

360

360

—

—

—

260

260

300

400

400

400

∆ “ON” Resistance

Between any 2 circuits in a commonpackage

(VC = VDD)

(Vin = ± 5.0 Vdc, VSS = – 5.0 Vdc)

(Vin = ± 7.5 Vdc, VSS = – 7.5 Vdc)

— ∆RON

5.0

7.5

—

—

—

—

—

—

15

10

—

—

Input/Output Leakage Current

(VC = VSS)

(Vin = + 7.5, Vout = – 7.5 Vdc)

(Vin = – 7.5, Vout = + 7.5 Vdc)

— —

7.5

7.5

—

—

± 0.1

± 0.1

—

—

± 0.0015

± 0.0015

±0.1

± 0.1

NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe5. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD curren

current out of the switch may contain both VDD and switch input components. The reliability of the device will bMaximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.

MC14016B

ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25 C)

Characteristic Figure Symbol

VDD

Vdc Min Typ (7.)

Propagation Delay Time (VSS = 0 Vdc)

Vin to Vout

(V V R 10 k )

7 tPLH,

tPHL

5.0

10

—

—

15

7.0



(VC = VDD, RL = 10 kΩ) 15 — 6.0

Control to Output

(Vin 10 Vdc, RL = 10 kΩ)

8 tPHZ,

tPLZ,

tPZH,

tPZL

5.0

10

15

—

—

—

34

20

15

Crosstalk, Control to Output (VSS = 0 Vdc)

(VC = VDD, Rin = 10 kΩ, Rout = 10 kΩ,

f = 1.0 kHz)

9 — 5.0

10

15

—

—

—

30

50

100

Crosstalk between any two switches (VSS = 0 Vdc)

(RL = 1.0 kΩ, f = 1.0 MHz,

crosstalk 20log10 Vout1Vout2

)

— — 5.0 — – 80

Noise Voltage (VSS = 0 Vdc)

(VC = VDD, f = 100 Hz)

10,11 — 5.0

10

15

—

—

—

24

25

30

(VC = VDD, f = 100 kHz) 5.0

10

15

—

—

—

12

12

15

Second Harmonic Distortion (VSS = – 5.0 Vdc)

(Vin

= 1.77 Vdc, RMS Centered @ 0.0 Vdc,

RL = 10 kΩ, f = 1.0 kHz)

— — 5.0 — 0.16

Insertion Loss (VC = VDD, Vin = 1.77 Vdc,

VSS = – 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)

Iloss 20log10VoutVin

)

(RL = 1.0 kΩ)

(RL = 10 kΩ)

(RL = 100 kΩ)

(RL = 1.0 MΩ)

12 — 5.0

—

—

—

—

2.3

0.2

0.1

0.05

Bandwidth (– 3.0 dB)(VC = VDD, Vin = 1.77 Vdc, VSS = – 5.0 Vdc,

RMS centered @ 0.0 Vdc)

(RL = 1.0 kΩ)

(RL = 10 kΩ)

(RL = 100 kΩ)

(RL = 1.0 MΩ)

12,13 BW 5.0

—

—

—

—

54

40

38

37

OFF Channel Feedthrough Attenuation

(VSS = – 5.0 Vdc)VoutVin

–50dB)

(RL = 1.0 kΩ)(RL = 10 kΩ)

(RL = 100 kΩ)

(RL = 1.0 MΩ)

(VC = VSS, 20 log10

— — 5.0

—

—

—

—

1250

140

18

2.0

6. The formulas given are for typical characteristics only at 25 C.7 Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe

MC14016B

VC

Vin Vout

IS



Figure 1. Input Voltage Test Circuit

VIL: VC is raised from VSS until VC = VIL.VIL: at VC = VIL: IS = ±10 µA with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.

VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.

Figure 2. Quiescent Power Dissipation

Test CircuitFigure 3. Typical Power Dissip

(1/4 of device sho

PULSE

GENERATOR

VDD

10 k

ID

VDD Vout

VSS Vin

fc

TO ALL

4 CIRCUITS

PD = VDD x ID1.0 M100 k10 k5.0 k

10,000

1000

100

10

1.0

TA = 25°C

fc, FREQUENCY (Hz

, P O W E R D I S S I P A T I O N (

P D

µ W )

CONTROL

INPUT

VDD = 15 V

TYPICAL RON versus INPUT VOLTAGE

, “ O N ” R E S I S T A N C E ( O H M S )

R O N

700

600

500

400

300

200

100


R O N

700

600

500

400

300

200

100

RL = 10 kΩ

TA = 25°C

VC = VDD = 5.0 Vdc

VSS = – 5.0 Vdc

VC = VDD = 7.5 Vdc

VSS = –7.5 Vdc

VC = VDD = 10 Vdc

VC

MC14016B

Vout

Vin



Figure 6. RON Characteristics

Test Circuit

Figure 7. Propagation Delay

and Waveforms

VC

Vin

Vout

RL20 ns

Vin

Vout

tPLH tPHL

50%90%

Figure 8. Turn–On Delay Time Test Circuitand Waveforms

Figure 9. Crosstalk

VC

Vout

Vin

RL CL

VX

20 ns

VC

Vout

Vout

10%

90%10%

90%

90%50%10%

tPZH tPHZ

VDD

VSS

tPLZtPZL

Vin = VDD

Vx = VSS

Vin = VSS

Vx = VDD

VC

Vout

Vin

1 k

OUT QUAN–TECH

35

30

25

2010 Vdc

5.0 Vdc

E V O L T A G E ( n V / C

Y C L E )

15

10

VDD = 15 Vdc

MC14016B

2.0

0

– 2.0

RL = 1 MΩ AND 100 kΩ

– 4.0O N L O S S ( d B )

10 kΩ

1.0 kΩ

– 3 0 dB (RL = 1 0 MΩ )



Figure 12. Typical Insertion Loss/BandwidthCharacteristics

Figure 13. Frequency Res

VC

Vin

+ 2.5 Vdc

0.0 Vdc

– 2.5 Vdc100 M10 M1.0 M100 k10 k

fin, INPUT FREQUENCY (Hz)

– 6.0

– 8.0

– 10

– 12

T Y P I C A L I N S E R

T I 3.0 dB (RL = 1.0 MΩ )

– 3.0 dB (RL = 10 kΩ )

– 3.0 dB (RL = 1.0 kΩ )

Figure 14. ∆V Across Switch

CONTROL

SECTION

OF IC

SOURCE

V

LOAD

ON SWITCH

MC14016B

APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Switch. The 0–to–5V Digital Control signal is used to directly control a 5 Vp–panalog signal.

The digital control logic levels are determined by VDD

The example shows a 5 Vp–p sigmargin at either peak. If voltage trand/or below VSS are anticipated onexternal diodes (Dx) are recommend



g g y DD

and VSS. The VDD voltage is the logic high voltage; the VSSvoltage is logic low. For the example, VDD = +5 V logic highat the control inputs; VSS = GND = 0 V logic low.

The maximum analog signal level is determined by VDDand VSS. The analog voltage must not swing higher thanVDD or lower than VSS.

( x)

B. These diodes should be small signthe maximum anticipated current sur

The absolute maximum potentiaVDD and VSS is 18.0 V. Most parame15 V which is the recommended

between VDD and VSS.

Figure A. Application Example

+ 5 V

VDD VSS

SWITCH

INSWITCH

OUT

5 Vp–p

ANALOG SIGNAL

0–TO–5 V DIGITAL

CONTROL SIGNALS

+ 5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY

5 Vp–p

ANALOG SIGNAL

MC14016B

Figure B. External Germanium or Schottky Clipping Diodes

VDD VDD

Dx

Dx

Dx

Dx

VSS VSS

SWITCH

IN

SWITCH

OUT

The MC14017B is a five stage Johnson decade counter with



The MC14017B is a five–stage Johnson decade counter withbuilt–in code converter. High speed operation and spike–free outputsare obtained by use of a Johnson decade counter design. The tendecoded outputs are normally low, and go high only at theirappropriate decimal time period. The output changes occur on thepositive–going edge of the clock pulse. This part can be used infrequency division applications as well as decade counter or decimaldecode display applications.

• Fully Static Operation

• DC Clock Input Circuit Allows Slow Rise Times• Carry Out Output for Cascading• Divide–by–N Counting• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4017B• Triple Diode Protection on All Inputs





(DC or Transient)

–0.5 to VDD + 0.5 V


(DC or Transient) per Pin± 10 mA



500 mW



TL Lead Temperature


260 °C




http://onsem

A = Assem

WL or L = Wafer

YY or Y = YearWW or W = Work

Device Packag

ORDERING INF

MC14017BCP PDIP–

MC14017BD SOIC–

MC14017BDR2 SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14017BF SOEIAJ–


MC14017B

PIN ASSIGNMENT

13

14

15

16

4

3

2

1

CE

CLOCK

RESET

VDD

Q2

Q0

Q1

Q5

BLOCK DIAGRAMFUNCTIONAL TRUTH TABLE

(Positive Logic)

Clock Decode

Clock Enable Reset Output=n

0 X 0 n

X 1 0 n

X X 1 Q0

0 0 n+1

X 0 n

X 0 n

1 0 n+1

X = Don’t Care. If n < 5 Carry = “1”,

Otherwise = “0”.

CLOCK

CLOCK

ENABLE

RESET

14

13

15 CoutQ9

Q8

Q7

Q6Q5

Q4Q3

Q2

Q1Q0

VDD = PIN 16

VSS = PIN 8

LOGIC DIAGRAM

CLOCK

CLOCK

ENABLE

RESET

Q5 Q1 Q7 Q3 Q9

117621

14

13

15

C

CD

R R

Q

Q

9

10

11

125

8

7

6

Cout

CE

Q8

Q4

Q9

VSS

Q3

Q7

Q6

C

CD

R R

Q

Q

C

CD

R R

Q

Q

C

CD

R R

Q

Q

C

CD

R R

Q

Q

MC14017B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—



“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.9

9.9

14.


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3.

7.

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0.

2.


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14017B



VDD

Vdc Min Typ (8.)




tTLH,

tTHL 5.0

10

—

—

100

50



tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40


Reset to Decode Output


tPLH, tPHL = (0.66 ns/PF) CL + 197 ns


tPLH,

tPHL

5.0

10

15

—

—

—

500

230

175


Clock to Cout




tPLH,

tPHL

5.0

10

15

—

—

—

400

175

125


Clock to Decode Output




tPLH,

tPHL

5.0

10

15

—

—

—

500

230

175


Reset to Cout


tPLH = (0.66 ns/pF) CL + 142 nstPLH = (0.5 ns/pF) CL + 100 ns

tPLH

5.0

1015

—

— —

400

175125

Clock Pulse Width tw(H) 5.0

10

15

250

100

75

125

50

35


10

15

—

—

—

5.0

12

16

Reset Pulse Width tw(H) 5.0

1015

500

250190

250

12595

Reset Removal Time trem 5.0

10

15

750

275

210

375

135

105

Clock Input Rise and Fall Time tTLH,

tTHL

5.0

10

15

No Limit

Clock Enable Setup Time tsu 5.0

10

15

350

150

115

175

75

52

Clock Enable Removal Time trem 5.0

10

15

420

200

140

260

100

70

MC14017B

VDD

Vout

VSSCLOCK

ENABLEQ0

Q1

Q2

Q3

Output

Sink Drive

Decode(S1 to A)



Figure 1. Typical Output Source and Output Sink Characteristics Test Circui

VDD

VSS

S1

S1

A

B

VSS

ID

EXTERNAL

POWER

SUPPLY

RESET

CLOCK Cout

Q4

Q5

Q6

Q7

Q8

Q9

Outputs

Carry

Clock to 5

thru 9

(S1 to B)

VGS = VDD

VDS = Vout

Figure 2. Typical Power Dissipation Test Circuit

VDD

VSS

ID

CLOCK

ENABLE

RESET

CLOCK

Cout

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

500 µF0.01 µF

CERAMIC

PULSE

GENERATOR

fc

CL CL CL CL CL CL CL CL

MC14017B


Figure 3 shows a technique for extending the number of decoded output states for the MC14017Bsequential within each stage and from stage to stage, with no dead time (except propagation delay).



Figure 3. Counter Expansion

RESETCLOCK

CE MC14017B

Q0 Q1 Q8 Q9• • •

9 DECODED

OUTPUTS

CLOCKFIRST STAGE INTERMEDIATE STAGES LAST STAGE

RESETCLOCK

CE MC14017B

Q0Q1 Q8 Q9• • •

RESETCLOCK

CE MC14017B

Q1 Q8• • •

8 DECODED

OUTPUTS

8 DECODED

OUTPUTS

Pcp NcpCLOCK

CLOCK

ENABLEtrem

RESET

20 ns

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

tPHL

tPHLtPLH

tPLH

tPLH

tPLH

tPLH

tPLH

tTHL

tTHL

tPLH

t

tPHL

tPHL

tPHL

50%

tPHL

tPHL

90%10%tTHL

tPHL

trem tsu 20 ns 20 ns

20 ns20 ns

tPLH

90%10% 50%

tTLH

tTLH

tTLH

tTLH

tTLH

tTHL

tTHL

tT

20

t



The MC14018B contains five Johnson counter stages which areasynchronously presettable and resettable. The counters aresynchronous, and increment on the positive going edge of the clock.

Presetting is accomplished by a logic 1 on the preset enable input.Data on the Jam inputs will then be transferred to their respective Qoutputs (inverted). A logic 1 on the reset input will cause all Q outputsto go to a logic 1 state.

Division by any number from 2 to 10 can be accomplished by

connecting appropriate Q outputs to the data input, as shown in theFunction Selection table. Anti–lock gating is included in theMC14018B to assure proper counting sequence.

• Fully Static Operation• Schmitt Trigger on Clock Input• Capable of Driving Two Low–power TTL Loads or One Low–power






(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current(DC or Transient) per Pin

± 10 mA



500 mW



TL Lead Temperature


260 °C




http://onsem

A = Assem

WL or L = Wafer


Device Packag

ORDERING INF

MC14018BCP PDIP–

MC14018BD SOIC–MC14018BDR2 SOIC–

PDIP–16P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14018BF SOEIAJ–


MC14018B

PIN ASSIGNMENT

13

14

15

16

125

4

3

2

1

JAM 5

Q5

C

R

VDD

Q2

JAM 2

JAM 1

Din

Q1



FUNCTIONAL TRUTH TABLE

Preset Jam

Clock Reset Enable Input Qn

0 0 X Qn

0 0 X Dn*

X 0 1 0 1

X 0 1 1 0

X 1 X X 1

*Dn is the Data input for that stage. Stage 1

has Data brought out to Pin 1.

9

10

11

125

8

7

6

JAM 5

JAM 4

PE

Q4

VSS

JAM 3

Q3

Q1

MC14018B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—




10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.9

9.9

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH 5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)

(CL = 50 pF on all outputs, allbuffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14018B


VDDAll Types


Vdc Min Typ (8.)





tTLH, tTHL

5.0

10

15

—

—

—

100

50

40



tTLH, tTHL (0 s/p ) CL 0 s 5 0


Clock to Q




tPLH,

tPHL

5.0

10

15

—

—

—

310

120

85

Reset to Q

tPLH = (0.90 ns/pF) CL + 325 ns

tPLH = (0.36 ns/pF) CL + 132 ns


5.0

10

15

—

—

—

370

150

100Preset Enable to Q




5.0

10

15

—

—

—

370

150

100

Setup Time

Data (Pin 1) to Clock

tsu

5.0

10

15

200

100

80

0

0

0

Jam Inputs to Preset Enable 5.0

10

15

200

100

80

0

0

0

Data (Jam Inputs)–to–Preset

Enable Hold Time

th 5.0

10

15

540

500

480

270

250

240


10

15

400

200

160

200

100

80

Reset or Preset Enable

Pulse Width

tWH 5.0

1015

290

130110

145

6555

Clock Rise and Fall Time tTLH, tTHL 5.0

10

15

No Limit


10

15

—

—

—

2.5

6.5

8.0

7. The formulas given are for the typical characteristics only at 25 C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe

ANY INPUT

20 ns 20 ns

90%50%

VDD

MC14018B

CLOCK

RESET

PRESET ENABLE

JAM 1



TIMING DIAGRAM

(Q5 Connected to Data Input)

JAM 2

JAM 3

JAM 4

JAM 5

Q1

Q2

Q3

Q4

Q5

DON’T CARE

UNTIL PRESET ENABLE

GOES HIGH

LOGIC DIAGRAM

JAM 1 JAM 2 JAM 3732

CLOCK 14

DATA 1

CLOCK

SHAPER

S S SD D D

C C C

Q Q Q

Q

FUNCTION SELECTION

Counter

Mode

Connect

Data Input

(Pin 1) to: Comments

Divide by 10

Divide by 8

Divide by 6Divide by 4

Divide by 2

Q5

Q4

Q3Q2

Q1

No external

components needed.

Divide by 9

Divide by 7

Divide by 5

Divide by 3

Q5 • Q4

Q4 • Q3

Q3 • Q2

Q2 • Q1

Gate package needed

to provide AND

function. Counter

Skips all 1’s state

The MC14020B 14–stage binary counter is constructed with MOS

P–channel and N–channel enhancement mode devices in a single



P channel and N channel enhancement mode devices in a singlemonolithic structure. This part is designed with an input wave shapingcircuit and 14 stages of ripple–carry binary counter. The deviceadvances the count on the negative–going edge of the clock pulse.Applications include time delay circuits, counter controls, andfrequency–dividing circuits.

• Fully Static Operation• Diode Protection on All Inputs


Schottky TTL Load Over the Rated Temperature Range• Buffered Outputs Available from stages 1 and 4 thru 14• Common Reset Line• Pin–for–Pin Replacement for CD4020B





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA

PD Power Dissipation,per Package (Note 3.)

500 mW



TL Lead Temperature


260 °C







high impedancecircuit For proper operation V and V shouldbeconstrained

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14020BCP PDIP–

MC14020BD SOIC–

PDIP–16P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

TSSOP–

DT SUFF

CASE 94

MC14020B

PIN ASSIGNMENT

13

14

15

16

125

4

3

2

1

Q9

Q8

Q10

Q11

VDD

Q6

Q14

Q13

Q12

Q5



TRUTH TABLE

Clock Reset Output State

0 No Change

0 Advance to Next State

X 1 All Outputs are Low

X = Don’t Care

LOGIC DIAGRAM

CLOCK

RESET

11

10

Q1 Q4 Q5 Q129 7 5 1

C

C

R

Q

Q

C

CR

Q

Q

C

C

R

Q

Q

C

CR

Q

Q

C

C

Q6 = PIN 4

Q7 = PIN 6

Q8 = PIN 13

Q9 = PIN 12

Q10 = PIN 14

Q11 = PIN 15

VDD = PIN 16

VSS = PIN 8

9

10

11

8

7

6

Q1

C

R

VSS

Q4

Q7

MC14020B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.9



Vin = 0 or VDD

OH

10

15

9.95

14.95

—

—

9.95

14.95

10

15

—

—

9.9

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH

5.0

1015

3.5

7.011

—

— —

3.5

7.011

2.75

5.508.25

—

— —

3

71



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL

= 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—




buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14020B



VDD

Vdc Min Typ (8.)





tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40Propagation Delay Time tPLH




Clock to Q1




tPLH,

tPHL

5.0

10

15

—

—

—

260

115

80

Clock to Q14

tPHL, tPLH – (1.7 ns/pF) CL + 1735 ns



5.0

10

15

—

—

—

1820

805

560


Reset to Qn


tPHL = (0.66 ns/pF) CL + 122 ns


tPHL

5.0

10

15

—

—

—

370

155

115


10

15

500

165

125

140

55

38


1015

—

— —

2.0

6.08.0


10

15

No Limit

Reset Pulse Width tWL 5.0

10

15

3000

550

420

320

120

80


1015

130

5030

65

2515


MC14020B

500 µF0.01 µF

CERAMIC

PULSE

GENERATOR

VDD

CL

C

R

Q1

Q4Qn

ID PULSE

GENERATOR

VDD

V

C

R

Q1

Q4

Qn



Figure 1. Power Dissipation Test Circuit

and Waveform

Figure 2. Switching Ti

and Wavefo

L

CLCLVSS

R

VDD

VSS

20 ns 20 ns

CLOCK90%50%10%

50% DUTY CYCLE

20 ns

CLOCK

ttPLH

90%50%10%

tTLH tT

Q

Figure 3. Timing Diagram

CLOCK

RESET

Q1

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11Q12

Q13

Q14

819240961 2 4 8 16 32 64 128 256 512 1024 2048

The MC14022B is a four–stage Johnson octal counter with built–in

code converter. High–speed operation and spike–free outputs areobtained by use of a Johnson octal counter design The eight decoded



obtained by use of a Johnson octal counter design. The eight decodedoutputs are normally low, and go high only at their appropriate octaltime period. The output changes occur on the positive–going edge of the clock pulse. This part can be used in frequency divisionapplications as well as octal counter or octal decode displayapplications.

• Fully Static Operation

• DC Clock Input Circuit Allows Slow Rise Times• Carry Out Output for Cascading• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4022B• Triple Diode Protection on All Inputs





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C





li ti f lt hi h th i t d lt t thi

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14022BCP PDIP–

MC14022BD SOIC–

MC14022BDR2 SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

MC14022B

PIN ASSIGNMENT

13

14

15

16

11

125

4

3

2

1

6

Cout

CE

C

R

VDD

Q4

Q5

Q2

Q0

Q1

NC

Q6

LOGIC DIAGRAM

11 1 5 7Q4 Q1 Q6 Q3

12

14

13

CLOCK

CLOCK

ENABLE

RESET15

VSS

VDD

CARRY

CC

DR

Q

Q

CC

DR

Q

Q

CC

DR

Q

Q

CC

DR

Q

Q

BLOCK DIAGRAM FUNCTIONAL TRUTH TAB

(Positive Logic)

Clock

Clock Enable Reset Out

0 X 0

X 1 0

0 0 n

X 0

1 0 nX 0

X X 1 Q

X = Don’t Care. If n < 4 Carry = 1

Otherwise = 0.

1210

5

411

73

12

Cout

Q7

Q6

Q5Q4

Q3Q2

Q1Q0

14

13

15

CLOCK

CLOCK

ENABLE

RESET

VDD = PIN 16

VSS = PIN 8

NC = PIN 6, 9

9

10

11

8

7

6

NC

Q7

Q4

VSS

Q3

NC

NC = NO CONNECTION

MC14022B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

4.95

9.95

—

—

4.95

9.95

5.0

10

—

—

4

9



Vin 0 or VDD 10

15

9.95

14.95

—

9.95

14.95

10

15

—

9

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH

5.0

1015

3.5

7.011

—

— —

3.5

7.011

2.75

5.508.25

—

— —

3

7



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

–

–


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—




buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14022B



VDD

Vdc Min Typ (7.)




tTLH

, tTHL

= (0.55 ns/pF) CL

+ 9.5 ns

tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40



tPLH,

t







tPHL

5.0

10

15

—

—

—

500

230

175


Clock to Cout




tPLH,

tPHL

5.0

10

15

—

—

—

400

175

125


Clock to Decode Output




tPLH,

tPHL

5.0

10

15

—

—

—

275

125

95


Reset to Cout


tPLH = (0.66 ns/pF) CL + 142 ns


tPLH

5.0

10

15

—

—

—

400

175

125


10

15

250

100

75

125

50

35


10

15

—

—

—

5.0

12

16

Reset Pulse Width tWH 5.0

10

15

500

250

190

250

125

95


10

15

750

275

210

375

135

105

Clock Input Rise and Fall Time tTLH, tTHL 5.0

10

15

No Limit

Clock Enable Setup Time tsu 5.0

10

15

350

150

115

175

75

52

Clock Enable Removal Time trem 5.0

10

15

420

200

140

260

100

70

MC14022B

VDD

VSS

VDD

VSS

A

BS1

Q6Q5Q4

Q3Q2

Q1

Q0CLOCK

ENABLE

RESET

Vout

ID

Output

Sink Drive S

Outputs

Cl

(S1 to A)

Carry Clock to Q5thru Q7

(S1 to B)



Figure 1. Typical Output Source and Output Sink Characteristics Test Circui

VSS

Cout

Q7CLOCK

EXTERNAL

POWER

SUPPLY

( )

VGS = VDD

VDS = Vout

Figure 2. Typical Power Dissipation Test Circuit

VDD

VSS

Cout

Q7

Q6

Q5

Q4Q3

Q2

Q1

Q0

CLOCK

CLOCK

ENABLE

RESET

ID

PULSE

GENERATOR

500 µF0.01 µF

CERAMIC

fc

CL CL CL CL CL CL


Figure 3 shows a technique for extending the number of decoded output states for the MC14022Bsequential within each stage and from stage to stage, with no dead time (except propagation delay).

RC

CE MC14022B

RC

CE MC14022B

RC

CE MC14022B

MC14022B

CLOCK

CLOCK

ENABLE

RESET

Q0

WH tWL

trem

tPHL

trel tsu 20 ns20 ns

20 ns 20 ns

tPLH



Figure 4. AC Measurement Definition and Functional Waveforms

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Cout

tPLH

tPLH

tPLH

tPLH

tPLH

tTLHtPLH

tPLH

tPHL

tPHL

tPHL

tPHL

tPHL

tPHL

tTHLtPHL

tPHL

tTLH

tPHL

tTHL

50%

90% 50%10%

tTLH

tTLH

tTLH

tTLH

tT

tT

The MC14024B is a 7–stage ripple counter with short propagation

delays and high maximum clock rates. The Reset input has standardnoise immunity, however the Clock input has increased noisei it d t H t i Th t t f h t t i



immunity due to Hysteresis. The output of each counter stage isbuffered.

• Diode Protection on All Inputs• Output Transitions Occur on the Falling Edge of the Clock Pulse• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power






–0.5 to VDD + 0.5 V



± 10 mA



500 mW




260 °C






high–impedance circuit. For proper operation, Vin

and Vout

should be constrained



either VSS or VDD). Unused outputs must be left open.

http://onsem

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14024BCP PDIP–

MC14024BD SOIC–

MC14024BDR2 SOIC–

MC14024BF SOEIAJ–

PDIP–14

P SUFFIX

CASE 64

SOIC–14

D SUFFIX

CASE 751

SOEIAJ–1

F SUFFIX

CASE 96


1. For ordering information oth SOIC k l

MC14024B

TRUTH TABLE

Clock Reset State

0 0 No Change

0 1 All Outputs Low

1 0 No Change

1 1 All Outputs Low

0 No Change



1 All Outputs Low

0 Advance One Count

1 All Outputs Low

11

12

13

14

8

9

105

4

3

2

1

7

6

NC

Q2

Q1

NC

VDD

NC

Q3

Q6

Q7

RESET

CLOCK

VSS

Q4

Q5

PIN ASSIGNMENT

VDD = PIN 14

VSS = PIN 7

NC = NO CONNECTION

LOGIC DIAGRAM

CLOCK

RESET2

1

12

Q1

11

Q2

4

Q6

3

Q7

C Q

R Q

C Q

R Q

C Q

R Q

C Q

R Q

MC14024B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—


10

15

4.95

9.95

14 95

—

—

—

4.95

9.95

14 95

5.0

10

15

—

—

—

4.9

9.9

14



15 14.95 14.95 15 14.


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH 5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3.

7.

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0.

2.


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14024B







tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40

Propagation Delay TimeClock to Q1


tPLH,tPHL

5.0 — 380





Clock to Q7




Reset to Qn




10

15

5.0

10

15

5.0

10

15

—

—

—

—

—

—

—

—

150

110

1000

400

300

500

250

180


10

15

500

165

125

200

60

40


10

15

600

350

260

375

200

150


10

15

625

190

145

250

75

50

Clock Input Rise and Fall Time tTLH, tTHL 5.0

10

15

—

—

—

—

—

—

Input Pulse Frequency fcl 5.0

10

15

—

—

—

2.5

8.0

12



MC14024B

EXTERNALPOWER

SUPPLY

EXTEPOW

SUP

VDD

VDD

VSS

IOH

VOL = Vout

C

R

Qn

COUNT Qn TO A

LOGIC “1” LEVEL.

VDD VOH

VSS

C

R

Qn



Figure 1. Typical Output Source


Figure 2. Typical O

Characteristics Te

Figure 3. Power Dissipation Test Circuit

VDD

500 µF0.01 µF

CERAMIC

PULSE

GENERATOR

fC

R Q7

Q6

Q5Q4

Q3

Q2

Q1

VSS

ID

CL

CL

CL

CL

CL

CL

CL

MC14024B

5 0 %

1 0 %

%

t T H L

t R 1

t R 2

t R 3

t R 4

t R 5

t R 6

t R 7

V D D

2 5 5

V S S

V D D

V S S

V O H

V O H

V O H

V O H

V O H

V O H

V O H

V O L

V O L

V O L

V O L

V O L

V O L

V O L



t W L

t W H

t r e m

t P L H 1

t T L H

t T L H

t T L H

t T L H

t T L H

t T L H

t P H L 1

t P L H 2

t P H L 2

t P H L 3

t P H L 4

t P H L 5

t P H L 6

t P H L 7

t P L H

3

t P L H 4

t P L H 5

t P L H 6

t P L H 7

5 0 %

5 0 %

5 0 %

5 0 %

5 0 %

5 0 %

5 0 %

9 0 %

9 0 %

1 0 %

1 0 %

1

9 0 %

t T H L

t T H L

t T H L

t T H L

t T H L

1

2

4

8

1 6

3 2

6 4

1 2 8

The MC14027B dual J–K flip–flop has independent J, K, Clock (C),

Set (S) and Reset (R) inputs for each flip–flop. These devices may beused in control, register, or toggle functions.




Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Logic Swing Independent of Fanout• Logic Edge–Clocked Flip–Flop Design —

Logic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive–going

edge of the clock pulse• Capable of Driving Two Low–power TTL Loads or One Low–power






(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW

TA Ambient Temperature Range –55 to +125°C


TL Lead Temperature


260 °C




static voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to this




http://onsem

A = Assem

WL or L = WaferYY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14027BCP PDIP–

MC14027BD SOIC–

MC14027BDR2 SOIC–

PDIP–16P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14027BF SOEIAJ

MC14027B

TRUTH TABLE

Inputs Outputs*

C† J K S R Qn‡ Qn+1 Qn+1

1 X 0 0 0 1 0

X 0 0 0 1 1 0

0 X 0 0 0 0 1

X 1 0 0 1 0 1

1 1 0 0 Qo Qo Qo

X X 0 0 X Qn Qn

No



X X 0 0 X Qn Qn

X X X 1 0 X 1 0

X X X 0 1 X 0 1

X X X 1 1 X 1 1

X = Don’t Care ‡ = Present State† = Level Change * = Next State

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

RB

CB

QB

QB

VDD

SB

JB

KB

RA

CA

QA

QA

VSS

SA

JA

KA

PIN ASSIGNMENT

BLOCK DIAGRAM

10

9

4

5

3

6

7

15

2

1

S

S

R

J

K

C

J Q

Q

Q

Chang

MC14027B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—


15

4.959.95

14.95

— —

—

4.959.95

14.95

5.010

15

— —

—

4.9.

14




(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH 5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1Output Drive Current


(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2

Input Current Iin 15 —±

0.1 —±

0.00001±

0.1 —Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

1.0

2.0

4.0

—

—

—

0.002

0.004

0.006

1.0

2.0

4.0

—

—

—



Per Package)


IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14027B







tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40

Propagation Delay Times**Clock to Q, Q



tPLH,tPHL

5.0

10

—

—

175

75



PLH PHL L

tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 — 50

Set to Q, Q




5.0

10

15

—

—

—

175

75

50

Reset to Q, Q




5.0

10

15

—

—

—

350

100

75

Setup Times tsu 5.0

10

15

140

50

35

70

25

17

Hold Times th 5.0

10

15

140

50

35

70

25

17

Clock Pulse Width tWH, tWL 5.0

10

15

330

110

75

165

55

38


10

15

—

—

—

3.0

9.0

13

Clock Pulse Rise and Fall Time tTLH, tTHL 5.0

10

15

—

—

—

—

—

—

Removal Times

Set

trem

5

10

15

90

45

35

10

5

3

Reset

5

10

15

50

25

20

– 30

– 15

– 10

Set and Reset Pulse Width tWH 5.0

10

15

250

100

70

125

50


MC14027B

20 ns 20 nsVDD

VSS

VDD

VSS

VDD

VSS

90%50%

10%

20 ns 20 ns

tsu

90%50%

10%tsu th

20 ns 20 ns90%

50%10%

C

K

J

20 ns 20 ns




(J, K, Clock, and Output)

Figure 2. Dynamic Sig

(Set, Reset, Clock,

VOH

VOL

tWLtWH1

fcltPLH tPHL

90%50%10%

tTLH

tTHL

Q

Inputs R and S low.

For the measurement of tWH, I/fcl, and PD

the Inputs J and K are kept high.

90%50%

10%ttw

20 ns90%

50%

twtPLH

tPHL

50%Q or Q

CLOCK

SET OR

RESET

LOGIC DIAGRAM

(1/2 of Device Shown)

S

J

K

R

C C

C

C

C

C

C

C

C

C

C

The MC14028B decoder is constructed so that an 8421 BCD codeon the four inputs provides a decimal (one–of–ten) decoded output,while a 3–bit binary input provides a decoded octal (one–of–eight)

htt //



code output with D forced to a logic “0”. Expanded decoding such asbinary–to–hexadecimal (one–of–16), etc., can be achieved by usingother MC14028B devices. The part is useful for code conversion,address decoding, memory selection control, demultiplexing, orreadout decoding.

• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range• Positive Logic Design• Low Outputs on All Illegal Input Combinations• Similar to CD4028B.





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C




static voltages or electric fields However precautions must be taken to avoid

http://onsem

A = Assem


WW or W = Work

Device Packag

ORDERING INF

MC14028BCP PDIP–

MC14028BD SOIC–

MC14028BDR2 SOIC–

PDIP–16P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14028BF SOEIAJ

MC14028B

PIN ASSIGNMENT

13

14

15

16

10

11125

4

3

2

1

7

6C

B

Q1

Q3

VDD

A

D

Q7

Q0

Q2

Q4

Q6

Q5Q9



98 Q8VSS

TRUTH TABLED C B A Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

0 0 0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 1 0 0 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 0 0 0 1 0 0

0 0 1 1 0 0 0 0 0 0 1 0 0 0

0 1 0 0 0 0 0 0 0 1 0 0 0 0

0 1 0 1 0 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 0 1 0 0 0 0 0 0

0 1 1 1 0 0 1 0 0 0 0 0 0 0

1 0 0 0 0 1 0 0 0 0 0 0 0 01 0 0 1 1 0 0 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0 0 0 0 0 0

1 0 1 1 0 0 0 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0 0 0 0 0 0

1 1 0 1 0 0 0 0 0 0 0 0 0 0

1 1 1 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0 0 0 0

BLOCK DIAGRAM

8421

BCD

INPUTS

DECIMALDECODED

OUTPUTS

OCTAL

DECODEDOUTPUTS

3

14

2

15

16

7

4

A

B

C

Q7

Q6

Q5Q4

Q3

Q2

Q1

Q0

3–BIT

BINARY

INPUTS

10

13

12

MC14028B


VDD – 55 C 25 C




Vin = VDD or 0 VOL

5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” LevelVin = 0 or VDD VOH

5.010

15

4.959.95

14.95

— —

—

4.959.95

14.95

5.010

15

— —

—

4.9.

14




p g

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO

= 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL

5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15



IT

= (0.9 µA/kHz) f + IDD


IT(CL) = IT(50 pF) + (CL – 50) Vfk





tTLH tTHL = (1 5 ns/pF) CL + 25 ns

tTLH,

tTHL 5 0 — 100

MC14028B

Inputs B, C, and D

switching in respect

to a BCD code.

All outpu

to respec

f in respe

clock.

20 ns 20 ns

90%50%

10%

1/f

VDD

VSS

20 ns 20 ns

INPUT A

INPUT C

10%

90%50%

VDD

VSS




Inputs A, B, and D low.

Q4

VOH

VOL

tPLH tPHL

tTLH tTHL

50%90%

10%

LOGIC DIAGRAM

Q9

Q8

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

D

C

B

A

MC14028B


Expanded decoding can be performed by using theMC14028B and other CMOS Integrated Circuits. Thecircuit in Figure 2 converts any 4–bit code to a decimal orhexadecimal code. The accompanying table shows the inputbinary combinations, the associated “output numbers” that

go “high” when selected, and the “redefined outputnumbers” needed for the proper code. For example: For thecombination DCBA = 0111 the output number 7 is redefinedfor the 4–bit binary, 4–bit gray, excess–3, or excess–3 gray

d 7 5 4 2 i l Fi 3 h 6 bi

D

MC14028B

D C B A D

Q9 Q0 Q9

15 – 8



codes as 7, 5, 4, or 2, respectively. Figure 3 shows a 6–bitbinary 1–of–64 decoder using nine MC14028B circuits andtwo MC14069UB inverters.

The MC14028B can be used in decimal digit displays,such as, neon readouts or incandescent projection indicators

as shown in Figure 4.

Figure 2. Code Conversion Circ

OUTPUT NUMBER

Cod

O

Hexade

Inputs Output Numbers

D C B A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 3

0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 3 2

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 4 7

0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 5 6

0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 6 4

0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 7 5

1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 8 151 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 9 14

1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 10 12

1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 11 13

1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 12 8

1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 13 9

1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 11

1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 10

4 –

B i t

B i n a r y

4 –

B i t

G r a y

MC14028B

INPUTS

A B C D E F INHIBIT(NO SELECTION)

A B C – D

Q0 Q9MC14028B



Figure 3. Six–Bit Binary 1–of–64 Decoder

A B C DMC14028B

Q0 Q9

A B C DMC14028B

Q0 Q9

A B C DMC14028B

Q0 Q9

A B C DMC14028B

Q0 Q9

A B C DMC14028B

Q0 Q9

A B C DMC14028B

Q0 Q9

A B C DMC14028B

Q0 Q9

A

Q

70 8 15 16 23 24 31 32 39 40 47 48 55 56

*1/6 MC14069UB 64 OUTPUTS (SELECTED OUTPUT IS HIGH)

Figure 4. Decimal Digit Display Application

A

Q9

MC14028B

B

C

DQ8Q7Q6Q5Q4Q3Q2Q1Q0

90

29 1

APPROPRIATE

VOLTAGE

NEONDISPLAY

APPRO

VOL

OR

The MC14029B Binary/Decade up/down counter is constructedwith MOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. The counter consists of type D flip–flopstages with a gating structure to provide toggle flip–flop capability. http://onsem



g g g p gg p p p yThe counter can be used in either Binary or BCD operation. Thiscomplementary MOS counter finds primary use in up/down anddifference counting and frequency synthesizer applications where lowpower dissipation and/or high noise immunity is desired. It is alsouseful in A/D and D/A conversion and for magnitude and signgeneration.

• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Internally Synchronous for High Speed• Logic Edge–Clocked Design — Count Occurs on Positive Going

Edge of Clock• Asynchronous Preset Enable Operation•

Capable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature Range• Pin for Pin Replacement for CD4029B





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW


Tstg

Storage Temperature Range –65 to +150 °C

TL Lead Temperature


260 °C


A = Assem


WW or W = Work

Device Packag

ORDERING INF

MC14029BCP PDIP–

MC14029BD SOIC–

MC14029BDR2 SOIC–

PDIP–16P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14029BF SOEIAJ

MC14029B

TRUTH TABLE

Carry In Up/Down

Preset

Enable Action

1 X 0 No Count

0 1 0 Count Up

0 0 0 Count Down

X X 1 Preset

X = Don’t Care

1

1

1

1

15

4

3

2

1

8

7

6

P0

P3

Q3

PE

VSS

Cout

Q0

Cin

PIN ASSIGN




VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)(VO = 13.5 or 1.5 Vdc)

VIL

5.0

1015

—

— —

1.5

3.04.0

—

— —

2.25

4.506.75

1.5

3.04.0

—

— —

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

1015

—

— —

5.0

1020

—

— —

0.005

0.0100.015

5.0

1020

—

— —



P P k )

IT 5.0

10

15



I (1 70 A/kH ) f I

MC14029B


All Types






tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40


Clk to Q



t t (0 5 / F) C 75

tPLH,

tPHL

5.0

10

15

—

—

200

100

90




Clk to Cout




tPLH,

tPHL 5.0

10

15

—

—

—

250

130

85

Cin to Cout




tPLH,

tPHL 5.0

10

15

—

—

—

175

50

50

PE to Q




tPLH,

tPHL 5.0

10

15

—

—

—

235

100

80

PE to Cout

tPLH, tPHL = (1. 7 ns/pF) CL + 465 nstPLH, tPHL = (0.66 ns/pF) CL + 192 ns


tPLH,

tPHL 5.010

15

— —

—

320145

105

Clock Pulse Width tW(cl) 5.0

10

15

180

80

60

90

40

30


10

15

—

—

—

4.0

8.0

10

Preset Removal TimeThe Preset Signal must be low prior to a positive–going

transition of the clock.

trem 5.010

15

16080

60

8040

30

Clock Rise and Fall Time tr(cl)

tf(cl)

5.0

10

1 5

—

—

—

—

—

—

Carry In Setup Time tsu 5.0

10

15

150

60

40

75

30

20

Up/Down Setup Time 5.010

15

340140

100

17070

50

Binary/Decade Setup Time 5.0

10

320

140

160

70

MC14029B

VDD

ID500 pF 0.01 µF

CERAMIC

PULSE

GENERATOR

PE

CinB/DU/D

CLKP0P1P2

P3 Cout

Q3

Q2

Q1

Q0

C

CL

CL

CL

CL




CL

VDD

VSS

20 ns 20 ns

CLK 50% 90%10%

VARIABLEWIDTH

PROGRAMMABLE

PULSE

GENERATOR

VDD

PECinB/DU/DCLK

P0P1P2

P3 Cout

Q3

Q2

Q1

Q0

CL

VSS

CL

CL

CL

tWtsu trem

1/fcl

50%

50%

tW

Cout ONLY tTLH

90% 90%

20 ns

CARRY IN OR

UP/DOWN

OR BINARY/DECADE

CLOCK

PRESET ENABLE

Q0 OR CARRY OUT

VDD

VSSVDD

VSS

VDD

VSS

VOH

MC14029B

TIMING DIAGRAM

CLOCK

CARRY IN

UP/DOWN

BINARY/DECADEPE

P0

P1

P2



P3

Q0

Q1

Q2Q3

CARRY OUT

COUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 6

Q3 Q2 Q1 Q0

P3 P2 P1 P0 CLK

CoutU/DB/D

Q3 Q2 Q1 Q0

P3 P2 P1 P0 CLK

CoutU/DB/D

Q3 Q2 Q1 Q0

P3 P2 P1 P0 CLK

CoutU/DB/D

Cin

PE

Cin

PE

Cin

PE

MC14029B

MSDMC14029B

MC14029B

LSD

INPUTCLOCK

“1” “2” “3”VDD VDDVDD VDD

CLOCK

Cout 1 (LSD)

Cout 2

Cout 3 (MSD)

MC14029B

LOGIC DIAGRAM

Q 3

7

C A R R Y O U T



4

P 0

1 2

P 1

1 3

P 2

3

P 3

2

Q

1 4

Q 2

1

Q 1

6

Q 0

P E

T E

C L K

P 3

Q 3

Q 3

P E

T E

C L K

P 2

Q 2

Q 2

P E

T E

C L K

P 1

Q 1

Q 1

P E T E C L K

P 0

Q 0

Q 0

The MC14040B 12–stage binary counter is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. This part is designed with an input wave shapingcircuit and 12 stages of ripple–carry binary counter. The deviceadvances the count on the negative–going edge of the clock pulse.Applications include time delay circuits, counter controls, andf d i i i it

http://onsem



frequency–driving circuits.

• Fully Static Operation• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc


• Common Reset Line• Pin–for–Pin Replacement for CD4040B





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C



This device contains protection circuitry to guard against damage due to highstatic voltages or electric fields. However, precautions must be taken to avoid




A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14040BCP PDIP–

MC14040BD SOIC–

C C

PDIP–16

P SUFFICASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

TSSOP–

DT SUFF

CASE 94

MC14040B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q9

Q8

Q10

Q11

VDD

Q1

C

R

Q7

Q5

Q6

Q12

VSS

Q2

Q3

Q4



TRUTH TABLE


0 No Change

0 Advance to next state

X 1 All Outputs are low

X = Don’t Care

LOGIC DIAGRAM

CLOCK10

RESET11

Q1 Q2 Q3 Q109 7 6 14

Q4 = PIN 5

Q5 = PIN 3

Q6 = PIN 2

Q7 = PIN 4

Q8 = PIN 13

Q9 = PIN 12

VDD = PIN 16

VSS = PIN 8

C Q

RC Q

C Q

RC Q

C Q

RC Q

C Q

RC Q

C

RC

98 Q1VSS

MC14040B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” LevelVin = 0 or VDD

VOH 5.010

15

4.959.95

14.95

— —

—

4.959.95

14.95

5.010

15

— —

—

4.9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9 0 or 1 0 Vdc)

VIL

5.0

10

—

—

1.5

3 0

—

—

2.25

4 50

1.5

3 0

—

—



(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

10

15

—

3.0

4.0

—

4.50

6.75

3.0

4.0

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14040B



VDD

Vdc Min Typ (8.)


TTLH, TTHL = (1.5 ns/pF) CL + 25 ns

TTLH, TTHL = (0.75 ns/pF) CL + 12.5 ns

TTLH, TTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40

Propagation Delay TimeClock to Q1




tPLH,tPHL

5.0

10

15

—

—

—

260

115

80

Clock to Q12



Clock to Q12




5.0

10

15

—

—

—

1625

720

500


Reset to Qn


tPHL = (0.86 ns/pF) CL + 182 ns


tPHL

5.0

10

15

—

—

—

370

155

115


10

15

385

150

115

140

55

38


10

15

—

—

—

2.1

7.0

10.0Clock Rise and Fall Time tTLH, tTHL 5.0

10

15

No Limit


10

15

960

360

270

320

120

80


10

15

130

50

30

65

25

15


PULSEGENERATOR

PULSE

GENERATOR500 µF

0.01 µF

CERAMIC

VDD

CL

CL

C

ID

Q1Q2

Qn

C

R

VDD

V

Q1

Q2

Qn

C

R

MC14040B

CLOCK

RESET

Q1

Q2

Q3

Q4

Q5

Q6

Q7

1 2 4 8 16 32 64 128 256 512 1024 204




Q7

Q8

Q9

Q10

Q11

Q12


TIME–BASE GENERATOR

A 60 Hz sinewave obtained through a 1.0 Megohmresistor connected directly to a standard 120 Vac power lineis applied to the clock input of the MC14040B. By selecting

outputs Q5, Q10, Q11, and Q12 accomplished. The MC14012B doutputs, produces a single output pulsecounter. The resulting output frequen

VDD

VSS

120 Vac

60 Hz

1.0 M

≥ 20 pF

MC14040BC

R Q12

Q11

Q10

Q5

1/2

MC14012B

1/2

MC14012B

1.0 P

The MC14042B Quad Transparent Latch is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each latch has a separate data input, but all fourlatches share a common clock. The clock polarity (high or low) used tostrobe data through the latches can be reversed using the polarityinput. Information present at the data input is transferred to outputs Qand Q during the clock level which is determined by the polarity input.

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When the polarity input is in the logic “0” state, data is transferredduring the low clock level, and when the polarity input is in the logic“1” state the transfer occurs during the high clock level.

• Buffered Data Inputs• Common Clock• Clock Polarity Control• Q and Q Outputs• Double Diode Input Protection• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power






(DC or Transient)

–0.5 to VDD + 0.5 V


± 10 mA



500 mW



TL Lead Temperature


260 °C



A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14042BCP PDIP–

MC14042BD SOIC–

MC14042BDR2 SOIC–

PDIP–16

P SUFFICASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14042BF SOEIAJ–


MC14042B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q2

D2

D3

Q3

VDD

Q1

Q1

Q2

D0

Q0

Q0

Q3

VSS

D1

POLARITY

CLOCK



TRUTH TABLE

Clock Polarity Q

0 0 Data

1 0 Latch

1 1 Data

0 1 Latch

LOGIC DIAGRAM

CLOCK

POLARITY

VDD = PIN 16

VSS = PIN 8

5

6

4

7

13

14D3

D2

D1

D0 LATCH

1

LATCH

2

LATCH

3

LATCH

4

Q2

Q3

Q3

Q2

Q1

Q1

Q0

Q0

12

2

3

10

9

11

1

15

MC14042B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” LevelVin = 0 or VDDVOH 5.010

15

4.959.95

14.95

— —

—

4.959.95

14.95

5.010

15

— —

—

4.9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(V 13 5 or 1 5 Vdc)

VIL

5.0

10

15

—

—

1.5

3.0

4 0

—

—

2.25

4.50

6 75

1.5

3.0

4 0

—

—



(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 —

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

1.0

2.0

4.0

—

—

—

0.002

0.004

0.006

1.0

2.0

4.0

—

—

—



Per Package)

(CL = 50 pF on all outputs allbuffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14042B







tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40

Propagation Delay Time, D to Q, Q



tPLH,

tPHL 5.010

15

— —

—

22090

60

Propagation Delay Time, Clock to Q, Q



( / F) C

tPLH,

tPHL 5.0

10

—

—

220

90




Clock Pulse Width tWH

5.0

10

15

300

100

80

150

50

40

Clock Pulse Rise and Fall Time tTLH,

tTHL 5.0

10

15

—

—

—

—

—

—

Hold Time th5.0

10

15

100

50

40

50

25

20

Setup Time tsu

5.0

10

15

50

30

25

0

0

0


VDD

VSS

PULSE

GENERATOR 1

16

5

6

4

7

13

14

CLOCK

POLARITY

D0

D1

D2

D3 Q3

Q3

Q2

Q2

Q1

Q1

Q0

Q0

15

1

12

11

9

10

3

2

8For Power Dissipation test, each output

1f

20 ns

DATA INPUT

Q OUTPUT

Q OUTPUT

tPLH

tTLH

tTHL

90%50%

90%

10%

90%

10%50%

tPHL

MC14042B

NOTE: CL connected to output under test.

PULSE

GENERATOR 1

PULSE

GENERATOR 2

VDD

16

5

6

4

7

13

14

CLOCK

POLARITY

D0

D1

D2

D3 Q3

Q3

Q2Q2

Q1

Q1

Q0

Q0

VSS8

15

1

1211

9

10

3

2



Figure 2. AC Test Circuit and Timing Diagram

(Clock to Output)

20* ns 20 ns

90%

10%

50%

tWH

20 ns

90%50%

tsu th

tPLH

90%

50%10%

CLOCK INPUT

P.G. 1

DATA INPUTP.G. 2

Q OUTPUT

*Input clock rise time is 20 ns except for maximum rise time test.

Quad R–S Latches

The MC14043B and MC14044B quad R–S latches are constructedwith MOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. Each latch has an independent Q outputand set and reset inputs. The Q outputs are gated through three–statebuffers having a common enable input. The outputs are enabled with al i l “1” hi h th bl i t l i l “0” l

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logical “1” or high on the enable input; a logical “0” or lowdisconnects the latch from the Q outputs, resulting in an open circuit atthe Q outputs.

• Double Diode Input Protection• Three–State Outputs with Common Enable• Outputs Capable of Driving Two Low–power TTL Loads or One

Low–Power Schottky TTL Load Over the Rated Temperature Range• Supply Voltage Range = 3.0 Vdc to 18 Vdc




(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C






high–impedancecircuit.For proper operation,Vin and Vout shouldbeconstrained

XX = Specific

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packa

ORDERING INF

MC14043BCP PDIP–

MC14043BD SOIC–

MC14043BDR2 SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14043BF SOEIAJ

MC14043BFEL SOEIAJ

MC14044BCP PDIP

MC14043B, MC14044B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

S2

NC

S3

R3

VDD

Q1

Q2

R2

S0

R0

Q0

Q3

VSS

R1

S1

E

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

R2

Q0

R3

S3

VD

Q1

Q2

S2

R0

S0

NC

Q3

VSS

S1

R1

E

MC14043B MC14044B



MC14043B

TRUTH TABLE

MC14044B

S R E Q

HighImpedance

X X 0

No Change

0

0

0

0

1

1

1

R3

S3

R2

S2

R1

S1

R0

S04

3

6

7

12

11

14

15

Q3

Q2

Q1

Q02

9

10

1

S3

R3

S2

R2

S1

R1

S0

R04

3

6

7

12

11

14

15

Q3

Q2

Q1

Q013

9

10

1

VDD = PIN 16

VSS = PIN 8NC = PIN 13

NC = NO CONNECTION

MC14043B, MC14044B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH

5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—



“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

1.0

2.0

4.0

—

—

—

0.002

0.004

0.006

1.0

2.0

4.0

—

—

—



Per Package)

(CL = 50 pF on all outputs allbuffers switching)

IT 5.0

10

15




Three–State Output Leakage

Current

ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 —


IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14043B, MC14044B



VDD

Vdc Min Typ (8.)

Output Rise Time

tTLH = (1.35 ns/pF) CL + 32.5 ns



tTLH

5.0

10

15

—

—

—

100

50

40

Output Fall Time

tTHL = (1.35 ns/pF) CL + 32.5 ns



tTHL

5.0

10

15

—

—

—

100

50

40


tPLH = (0.90 ns/pF) CL + 130 ns



tPLH

5.0

10

15

—

—

—

175

75

60



tPLH (0.26 ns/pF) CL + 47 ns 15 60

tPHL = (0.90 ns/pF) CL + 130 ns



tPHL 5.0

10

15

—

—

—

175

75

60

Set, Set Pulse Width tW 5.0

10

15

200

100

70

80

40

30

Reset, Reset Pulse Width tW 5.0

10

15

200

100

70

80

40

30

Three–State Enable/Disable Delay tPLZ,

tPHZ,

tPZL,

tPZH

5.0

10

15

—

—

—

150

80

55


AC WAVEFORMS

MC14043B MC14044

20 ns 20 ns

90%

10%

RESET

SET

Q

tPHL tPLH

20 ns 20 ns

50%

90%50%

10%

tTHL tTLH

90%50%

10%

VDD

VSS

VDD

VSS

VOH

VOL

RESET

SET

Q

20 ns 20 ns

90%

10%50%

20 ns

50%

tTLH

50%9

tPLH

MC14043B, MC14044B

THREE–STATE ENABLE/DISABLE DELAYS

Set, Reset, Enable, and Switch Conditions for 3–State Tests

MC14043B MC14044B

Test Enable S1 S2 Q S R S R

tPZH Open Closed A VDD VSS VSS VDD

tPZL Closed Open B VSS VDD VDD VSS

tPHZ Open Closed A VDD VSS VSS VDD

tPLZ Closed Open B VSS VDD VDD VSS

TO

OUTPUT

UNDERTEST



ENABLE

QA

QB

50%

tPZH

10%

tPZL

tPHZ

tPLZ

10%

90%

VDD

VSS

VDD

VOL

VOH

VSS

The MC14046B phase locked loop contains two phase comparators,a voltage–controlled oscillator (VCO), source follower, and zener

diode. The comparators have two common signal inputs, PCAin andPCBin. Input PCAin can be used directly coupled to large voltagesignals, or indirectly coupled (with a series capacitor) to small voltagesignals. The self–bias circuit adjusts small voltage signals in the linearregion of the amplifier. Phase comparator 1 (an exclusive OR gate)provides a digital error signal PC1out, and maintains 90° phase shift ath f b PCA d PCB i l (b h 50%

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the center frequency between PCAin and PCBin signals (both at 50%duty cycle). Phase comparator 2 (with leading edge sensing logic)provides digital error signals, PC2out and LD, and maintains a 0°

phase shift between PCAin and PCBin signals (duty cycle isimmaterial). The linear VCO produces an output signal VCO outwhose frequency is determined by the voltage of input VCO in and thecapacitor and resistors connected to pins C1A, C1B, R1, and R2. Thesource–follower output SFout with an external resistor is used wherethe VCOin signal is needed but no loading can be tolerated. The inhibitinput Inh, when high, disables the VCO and source follower tominimize standby power consumption. The zener diode can be used toassist in power supply regulation.

Applications include FM and FSK modulation and demodulation,frequency synthesis and multiplication, frequency discrimination,tone decoding, data synchronization and conditioning,voltage–to–frequency conversion and motor speed control.

• Buffered Outputs Compatible with MHTL and Low–Power TTL• Diode Protection on All Inputs• Supply Voltage Range = 3.0 to 18 V• Pin–for–Pin Replacement for CD4046B

• Phase Comparator 1 is an Exclusive Or Gate and is Duty Cycle Limited• Phase Comparator 2 switches on Rising Edges and is not Duty Cycle

Limited




Vin Input Voltage Range (All Inputs) –0.5 to VDD + 0.5 V

Iin DC Input Current, per Pin ± 10 mA



500 mW

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14046BCP PDIP–

MC14046BDW SOIC–

MC14046BDWR2 SOIC–

1. For ordering information the SOIC packages, pleaON S i d t

PDIP–16

P SUFFI

CASE 64

SOIC–1

DW SUFF

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14046BF SOEIAJ–


MC14046B

PIN ASSIG

5

4

3

2

1

8

7

6

VCOout

PCBin

PC1out

LD

VSS

C1B

C1A

INH

BLOCK DIAGRAM

PCAin

PCBin

VCOin

INH

14

3

9

5

VDD = PIN 16

VSS = PIN 8

2 PC1out

13 PC2out1 LD

4 VCOout

11 R112 R26 C1A7 C1B

10 SFout

15 ZENERVSS

SELF BIAS

CIRCUIT

PHASE

COMPARATOR 1

PHASE

COMPARATOR 2

VOLTAGE

CONTROLLEDOSCILLATOR

(VCO)

SOURCE FOLLOWER




VDD – 55 C 25 C

Characteristic Symbol Vdc Min Max Min Typ Max MOutput Voltage “0” Level

Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4

9

14

Input Voltage . “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH 5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 1.2

– 0.25

– 0.62

– 1.8

—

—

—

—

– 1.0

– 0.2

– 0.5

– 1.5

– 1.7

– 0.36

– 0.9

– 3.5

—

—

—

—

–

– 0

– 0

–


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0

0

2


Input Capacitance Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package) Inh = PCAin = VDD,

Zener = VCOin = 0 V, PCBin = VDD

or 0 V, Iout = 0 µA

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—

Total Supply Current (5.)

(Inh = “0”, fo = 10 kHz, CL = 50 pF,

R1 = 1.0 MΩ, R2 = RSF = ∞,

and 50% Duty Cycle)

IT 5.0

10

15




MC14046B

ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25°C)

VMinimum

Characteristic Symbol Vdc

Device Typical

Output Rise Time




tTLH

5.0

10

15

—

—

—

180

90

65

Output Fall TimetTHL = (1.5 ns/pF) CL + 25 ns

tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 9.5 ns

tTHL

5.0

10

15

—

—

—

100

50

37

PHASE COMPARATORS 1 and 2

Input Resistance — PCAin Rin 5.0

10

1.0

0.2

2.0

0.4



10

15

0.2

0.1

0.4

0.2

— PCBin Rin 15 150 1500

Minimum Input Sensitivity

AC Coupled — PCAin

C series = 1000 pF, f = 50 kHz

Vin 5.0

10

15

—

—

—

200

400

700

DC Coupled — PCAin, PCBin — 5 to 15 See Noise Immu

VOLTAGE CONTROLLED OSCILLATOR (VCO)

Maximum Frequency

(VCOin = VDD, C1 = 50 pF

R1 = 5.0 kΩ, and R2 = ∞)

fmax 5.0

10

15

0.5

1.0

1.4

0.7

1.4

1.9

Temperature — Frequency Stability(R2 = ∞ )

— 5.010

15

— —

—

0.120.04

0.015

Linearity (R2 = ∞ )

(VCOin = 2.5 V ± 0.3 V, R1 > 10 kΩ)

(VCOin = 5.0 V ± 2.5 V, R1 > 400 kΩ)

(VCOin = 7.5 V ± 5.0 V, R1 ≥ 1000 kΩ)

—

5.0

10

15

—

—

—

1.0

1.0

1.0

Output Duty Cycle — 5 to 15 — 50

Input Resistance — VCOin Rin 15 150 1500

SOURCE–FOLLOWER

Offset Voltage

(VCOin minus SFout, RSF > 500 kΩ)

— 5.0

10

15

—

—

—

1.65

1.65

1.65

Linearity

(VCOin = 2.5 V ± 0.3 V, RSF > 50 kΩ)

(VCOin = 5.0 V ± 2.5 V, RSF > 50 kΩ)

(VCOin = 7.5 V ± 5.0 V, RSF > 50 kΩ)

—

5.0

10

15

—

—

—

0.1

0.6

0.8

ZENER DIODE

Zener Voltage (Iz = 50 µA) VZ — 6.7 7.0

Dynamic Resistance (Iz = 1.0 mA) RZ — — 100

6 The formula given is for the typical characteristics only

MC14046B

PHASE COMPARATOR 1

Input Stage

PCAin

X X

PCBin

00 01

11 10

PC1out 0 1

PHASE COMPARATOR 2

Input Stage

X X 00 00 00



Figure 1. Phase Comparators State Diagrams

PCAin PCBin

PC2out 0 13–State

Output Disconnected

LD (Lock Detect) 0 01

Refer to Waveforms in Figure 3.

00

01 10

11

00

10 01

11

00

01

11

Characteristic Using Phase Comparator 1 Using Phase

No signal on input PCAin. VCO in PLL system adjusts to center

frequency (f0).

VCO in PLL system a

frequency (fmin).

Phase angle between PCAin and PCBin. 90° at center frequency (f0), approaching

0 and 180° at ends of lock range (2fL)

Always 0 in lock (po

Locks on harmonics of center frequency. Yes N

Signal input noise rejection. High L

Lock frequency range (2fL). The frequency range of the input signal on which the loop will stay

initially in lock; 2fL = full VCO frequency range = fmax – fmin.

Capture frequency range (2fC). The frequency range of the input signal on which the loop will lock

out of lock.

Depends on low–pass filter characteristics

(see Figure 3). fC fL

fC

Center frequency (f0). The frequency of VCOout, when VCOin = 1/2 VDD

VCO output frequency (f) 1

MC14046B

Typical Low–Pass Filters

PCAin

@ FREQUENCY f′

PCBin

14

3PHASE

COMPARATOR

EXTERNAL

LOW–PASS

FILTER

VCO2 OR 13

PC1out

OR

PC2out

VCOin

9

9 10

4

EXTERNAL

÷ N

COUNTER

R1 R2

11 12 6 7CIA CIB

CI

SFou

RSF

(a) R3 (a) R3Typically:

6N

SOURCE

FOLLOWER



NOTE: Sometimes R3 is split into two series resistors each R3 ÷ 2. A capacitor CC is then placed from the midpoint

CC should be such that the corner frequency of this network does not significantly affectωn. In Figure B, the r

damping, R4 (0.1)(R3) for optimum results.

Waveforms

(a)

INPUTOUTPUT

C22fC

1 2 fL

R3 C2

(a)

INPUTOUTPUT

R4

C2

R4 C26N

fmax –

(R3

3,000 ) C2

∆ f = fmax – fmin

Definitions: N = Total division ratio in feedback loop

Kφ = VDD / π for Phase Comparator 1Kφ = VDD /4 π for Phase Comparator 2

KVCO2 fVCOVDD – 2 V

2 fr10

for a typical design ωn (at phase detector input)

ζ 0.707

LOW–PASS FIL

Filter A

nK KVCONR3C2

N n2K KVCO

F(s) 1R3C2S 1

n NC

0.5 n

F(s)S(R

PCAin

PCBin

PC1out

VCOin

VDD

VSS

VOH

VOL

VOH

VOLVOH

VOL

PCAin

PCBin

PC2out

LD

Phase Comparator 1 Phase Comp

The MC14049B Hex Inverter/Buffer and MC14050B NoninvertingHex Buffer are constructed with MOS P–Channel and N–Channel

enhancement mode devices in a single monolithic structure. Thesecomplementary MOS devices find primary use where low powerdissipation and/or high noise immunity is desired. These devicesprovide logic level conversion using only one supply voltage, VDD.

The input–signal high level (VIH) can exceed the VDD supplyvoltage for logic level conversions. Two TTL/DTL loads can be drivenwhen the devices are used as a CMOS–to–TTL/DTL converter (VDD

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= 5.0 V, VOL 0.4 V, IOL ≥ 3.2 mA).Note that pins 13 and 16 are not connected internally on these

devices; consequently connections to these terminals will not affectcircuit operation.

• High Source and Sink Currents• High–to–Low Level Converter• Supply Voltage Range = 3.0 V to 18 V• VIN can exceed VDD

• Meets JEDEC B Specifications• Improved ESD Protection On All Inputs




Vin Input Voltage Range

(DC or Transient)

–0.5 to +18.0 V

Vout Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin Input Current(DC or Transient) per Pin

± 10 mA

Iout Output Current


± 45 mA



(Plastic)

(SOIC)

825

740

mW



TL Lead Temperature


260 °C

XX = Specific

A = Assemb

WL or L = Wafer L

YY or Y = YearWW or W = Work W

Device Packa

ORDERING INF

MC14049BCP PDIP–

MC14049BD SOIC–

MC14049BDR2 SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14049BF SOEIAJ

MC14050BCP PDIP–

TSSOP–

DT SUFF

CASE 94

MC14049B, MC14050B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

OUTE

NC

INF

OUTF

NC

IND

OUTD

INE

OUTB

INA

OUTA

VDD

VSS

INC

OUTC

INB



LOGIC DIAGRAMMC14049B

14 15

11

9

7

5

3

12

10

6

4

2

NC = PIN 13, 16

VSS = PIN 8

VDD = PIN 1

MC14050B

14 15

11

9

7

5

3

12

10

6

4

2

NC = PIN 13, 16

VSS = PIN 8

VDD = PIN 1

MC14049B, MC14050B


VDD – 55 C + 25 C




Vin = VDD

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0

VOH 5.0

1015

4.95

9.9514.95

—

— —

4.95

9.9514.95

5.0

1015

—

— —

4.

9.14


(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level VIH



(VO = 0.5 Vdc)

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7



(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

10

15

– 1.6

– 1.6

– 4.7

—

—

—

– 1.25

– 1.30

– 3.75

– 2.5

– 2.6

– 10

—

—

—

–

–

– 3


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

3.75

10

30

—

—

—

3.2

8.0

24

6.0

16

40

—

—

2

6

1


Input Capacitance (Vin = 0) Cin — — — — 10 20 —

Quiescent Current (Per Package) IDD 5.0

10

15

—

—

—

1.0

2.0

4.0

—

—

—

0.002

0.004

0.006

1.0

2.0

4.0

—

—

—



per package)


buffers switching

IT 5.0

10

15




4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe5. The formulas given are for the typical characteristics only at + 25 C6. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

Where: IT is in µA (per Package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency and k = 0.002.

MC14049B, MC14050B

AC SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = + 25 C)


VDD

Vdc Min Typ (8.)

Output Rise Time


tTLH = (0.25 ns/pF) CL + 37.5 ns


tTLH

5.0

10

15

—

—

—

100

50

40




tTHL5.0

10

15

—

—

—

40

20

15


tPLH = (0.33 ns/pF) CL + 63.5 ns

tPLH = (0.19 ns/pF) CL + 30.5 ns


tPLH

5.0

10

15

—

—

—

80

40

30





tPHL = (0.1 ns/pF) CL + 15 nstPHL = (0.05 ns/pF) CL + 12.5 ns

tPHL

5.0

1015

—

— —

40

2015

7. The formulas given are for the typical characteristics only at 25 C.8. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential per

MC14049B MC14050B MC14049B MCVDD

VSS

VDD

VSS

1

8

1

8

IOLIOHVOH VOL

VDS = VOH – VDD

VDD

VSS

1

8

IOLVOL

VDD = VOL

I O

H ,

O U T P U T S O U R C E C U R R N T ( m A d c )

I O L ,

O U T P U T S I N K C U R R E N T ( m A d c )

– 50

– 40

– 30

– 20

– 10

0

– 10 – 8.0 – 6.0 – 4.0 – 2.0 0

VDS DRAIN–TO–SOURCE VOLTAGE (Vdc)

VGS = 5.0 Vdc

VGS = 10 Vdc

MAXIMUM CURRENT LEVELVGS = 15 Vdc

160

120

80

40

00 2.0 4.0 6

VDS DRAIN–TO–SOURCE V

MAXIMUM CU

VGS = 5.0 Vdc

MC14049B, MC14050B

P D ,

M A X I M U M

P O W E R D I S S I P A T I O N ( m W )

P

E R P A C K A G E

1200

1100

1000

900825800740700

600

500

400

300

200

100

0175150125100755025

TA, AMBIENT TEMPERATURE (°C)

175 mW (P)120 mW (D)

(P) PDIP

(D) SOIC



Figure 3. Ambient Temperature Power Derating

tPHL


PULSE

GENERATOR

VDD

VSS8

1

CL

VoutVin

#

#Invert on MC14049B only

20 ns

90%

50%

10%

90%

50%

10%

90%50%

10%

tTHL

tPHL

tPLH

tTLH

OUTPUTMC14049B

OUTPUT

MC14050B

INPUT

The MC14049UB hex inverter/buffer is constructed with MOSP–channel and N–channel enhancement mode devices in a single

monolithic structure. This complementary MOS device finds primaryuse where low power dissipation and/or high noise immunity isdesired. This device provides logic–level conversion using only onesupply voltage, VDD. The input–signal high level (VIH) can exceed theVDD supply voltage for logic–level conversions. Two TTL/DTLLoads can be driven when the device is used as CMOS–to–TTL/DTLconverters (VDD = 5.0 V, VOL 0.4 V, IOL ≥ 3.2 mA). Note that pins13 and 16 are not connected internally on this device; consequently

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PDIP 16



13 and 16 are not connected internally on this device; consequentlyconnections to these terminals will not affect circuit operation.

• High Source and Sink Currents• High–to–Low Level Converter• Supply Voltage Range = 3.0 V to 18 V• Meets JEDEC UB Specifications• VIN can exceed VDD

• Improved ESD Protection on All Inputs




Vin Input Voltage Range

(DC or Transient)

–0.5 to +18.0 V

Vout Output Voltage Range

(DC or Transient)

–0.5 to VDD +0.5 V

Iin Input Current


± 10 mA

Iout Output Current


+45 mA



Plastic

SOIC

825

740

mW



TL Lead Temperature


260 °C

2 Maximum Ratings are those values beyond which damage to the device

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14049UBCP PDIP–

MC14049UBD SOIC–

C C

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

TSSOP–DT SUFF

CASE 94

MC14049UB

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

OUTE

NC

INF

OUTF

NC

IND

OUTD

INE

OUTB

INA

OUTA

VDD

VSS

INC

OUTC

INB

NC = NO CONNECTION

LOGIC DIAGRAM

MC14049UB

14 15

11

9

7

5

3

12

10

6

4

2

NC = PIN 13, 16

VSS = PIN 8

VDD = PIN 1

CIRCUIT

(1/6 OF CI

MC140



VDD = PIN 1


V – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14Input Voltage “0” Level

(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

VIL

5.0

10

15

—

—

—

1.0

2.0

2.5

—

—

—

2.25

4.50

6.75

1.0

2.0

2.5

—

—

—

“1” Level

(VO = 0.5 Vdc)

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

VIH

5.0

10

15

4.0

8.0

12.5

—

—

—

4.0

8.0

12.5

2.75

5.50

8.25

—

—

—

4

8

12

Output Drive Current(VOH = 2.5 Vdc) Source

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH5.0

10

15

– 1.6

– 1.6

– 4.7

—

—

—

– 1.25

– 1.3

– 3.75

– 2.5

– 2.6

– 10

—

—

—

–

–

– 3


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

3.75

10

30

—

—

—

3.2

8.0

24

6.0

16

40

—

—

—

2

6

1


Input Capacitance (Vin = 0) Cin — — — — 10 20 —

Quiescent Current(Per Package)

IDD 5.010

15

— —

—

1.02.0

4.0

— —

—

0.0020.004

0.006

1.02.0

4.0

— —

—

MC14049UB



VDD

Vdc Min Typ (8.)

Output Rise Time



tTLH = (0.27 ns/pF) CL + 26.5 ns

tTLH

5.0

10

15

—

—

—

100

50

40




tTHL 5.0

10

15

—

—

—

40

20

15




tPLH = (0.11 ns/pF) CL + 24.5 ns

tPLH

5.0

10

15

—

—

—

80

40

30

Propagation Delay Time tPHL





tPHL = (0.12 ns/PF) CL + 9 nstPHL = (0.11 ns/pF) CL + 4.5 ns

tPHL

5.0

1015

—

— —

30

1510


Figure 1. Typical Voltage Transfer Characteristics versus Temperature

V o u t ,


18

15

10

5

1815105Vin, INPUT VOLTAGE (Vdc)

VDD = 5 Vdc

VDD = 15 Vdc

– 55°C

+125°C

VDD = 10 Vdc

MC14049UB

VDD

VSS

1

8

IOHVOH

VDS = VOH – VDD

VDD

VSS

1

8

IOL

VD

P U T S O U R C E C U R R N T ( m A d

c )

T P U T S I N K C U R R E N T ( m A d c )

– 30

– 20

– 10

0

VGS = 5.0 Vdc

VGS = 10 Vdc

160

120

80

MAXIMUM CU



Figure 2. Typical Output Source Characteristics Figure 3. Typical Output Sink

I O H

, O U T

I O

L ,

O U T

– 50

– 40

– 10 – 8.0 – 6.0 – 4.0 – 2.0 0

VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc)

MAXIMUM CURRENT LEVELVGS = 15 Vdc

40

00 2.0 4.0 6.

VDS, DRAIN–TO–SOURCE VO

VGS = 5.0 Vdc

Figure 4. Ambient Temperature Power Derating

P D ,

M A X I M U M

P O W E R D I S S I P A T I O N ( m W )

P

E R P A C K A G E

1200

1100

1000

900825800740700

600

500

400

300

200

100

0175150125100755025


175 mW (P)120 mW (D)

(P) PDIP

(D) SOIC

PULSE

GENERATOR

VD

VSS8

1

Vin

20 ns

90%

50%

10%

90%

50%

10%

tTHL

tPHL

OUTPUT

INPUT

Figure 5. Switching Ti

and Wavefo

The MC14051B, MC14052B, and MC14053B analog multiplexersare digitally–controlled analog switches. The MC14051B effectivelyimplements an SP8T solid state switch, the MC14052B a DP4T, andthe MC14053B a Triple SPDT. All three devices feature low ONimpedance and very low OFF leakage current. Control of analogsignals up to the complete supply voltage range can be achieved.

• Triple Diode Protection on Control Inp ts

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• Triple Diode Protection on Control Inputs

• Switch Function is Break Before Make• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V

Note: VEE must be VSS

• Linearized Transfer Characteristics• Low–noise – 12 nV/ √Cycle, f ≥ 1.0 kHz Typical• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053• For 4PDT Switch, See MC14551B

• For Lower RON, Use the HC4051, HC4052, or HC4053 High–SpeedCMOS Devices

MAXIMUM RATINGS (Note 1.)


VDD DC Supply Voltage (Referenced

to VEE, VSS ≥ VEE)

–0.5 to +18.0 V


(DC or Transient) (Referen–

ced to VSS for Control Inputsand VEE for Switch I/O)

–0.5 to VDD + 0.5 V


per Control Pin

± 10 mA




500 mW



TL Lead Temperature


260 °C

XX = Specif

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

TSSOP–

DT SUFF

CASE 94

ORDERING INF

MC14051B, MC14052B, MC14053B

MC14051B

8–Channel Analog

Multiplexer/Demultiplexer

MC14052B

Dual 4–Channel Analog


MC140

Triple 2–Chan

Multiplexer/De

VDD = PIN 16

VSS = PIN 8

VEE = PIN 7

INHIBIT

A

BC

X0

X1

X2

X3X4

X5

X6

X7

X

4

2

5

112

15

14

13

910

11

6

CONTROLS

SWITCHES

IN/OUT

COMMON

OUT/IN

3

4

2

51

11

15

14

129

10

6

CONTROLS

SWITCHES

IN/OUT

13

3

COMMONS

OUT/IN

X

Y

VDD = PIN 16

VSS = PIN 8

VEE = PIN 7

3

51

2

13

12

910

11

6

CONTROLS

SWITCHES

IN/OUT

VDD = P

VSS =

VEE =

INHIBIT

A

BX0

X1

X2

X3Y0

Y1

Y2Y3

INHIB

A

BC

X0

Y0

Y1Z0

Z1

X1



Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.

PIN ASSIGMENT

MC14051B MC14052B MC

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

X3

X0

X1

X2

VDD

C

B

A

X7

X

X6

X4

VSS

VEE

INH

X5

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

X0

X

X1

X2

VDD

B

A

X3

Y3

Y

Y2

Y0

VSS

VEE

INH

Y1 5

4

3

2

1

8

7

6

Z

Z1

Y0

Y1

VSS

VEE

INH

Z0

MC14051B, MC14052B, MC14053B


– 55 C 25 C

Characteristic Symbol VDD Test Conditions Min Max Min Typ (3.) Max

SUPPLY REQUIREMENTS (Voltages Referenced to VEE)

Power Supply Voltage

Range

VDD — VDD – 3.0 ≥ VSS ≥ VEE 3.0 18 3.0 — 18

Quiescent Current Per

Package

IDD

5.0

10

15

Control Inputs:

Vin = VSS or VDD,

Switch I/O: VEE VI/O

VDD, and ∆Vswitch

500 mV (4.)

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

Total Supply Current

(Dynamic Plus

Quiescent, Per Package

ID(AV) 5.0

10

15

TA = 25 C only (The

channel component,

(Vin – Vout)/Ron, is

not included.)

(0.07 µA/kHz) f + IDD

Typical (0.20 µA/kHz) f + IDD




CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)

Low–Level Input Voltage VIL 5.010

15

Ron = per spec,Ioff = per spec

— —

—

1.53.0

4.0

— —

—

2.254.50

6.75

1.53.0

4.0

High–Level Input Voltage VIH 5.0

10

15

Ron = per spec,

Ioff = per spec

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ± 0.00001 ± 0.1

Input Capacitance Cin — — — — 5.0 7.5

SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)Recommended

Peak–to–Peak Voltage

Into or Out of the Switch

VI/O — Channel On or Off 0 VDD 0 — VDD

Recommended Static or

Dynamic Voltage Across

the Switch (4.) (Figure 5)

∆Vswitch — Channel On 0 600 0 — 600

Output Offset Voltage VOO — Vin = 0 V, No Load — — — 10 —

ON Resistance Ron 5.0

1015

∆Vswitch 500 mV (4.)

Vin = VIL or VIH(Control), and Vin =

0 to VDD (Switch)

—

— —

800

400220

—

— —

250

12080

1050

500280

∆ON Resistance Between

Any Two Channels in the

Same Package

∆Ron 5.0

10

15

—

—

—

70

50

45

—

—

—

25

10

10

70

50

45

Off–Channel Leakage

Current (Figure 10)

Ioff 15 Vin = VIL or VIH

(Control) Channel to

Channel or Any One

Channel

— ± 100 — ± 0.05 ± 100

Capacitance, Switch I/O CI/O — Inhibit = VDD — — — 10 —

Capacitance, Common O/I CO/I — Inhibit = VDD

(MC14051B) 60

MC14051B, MC14052B, MC14053B

ELECTRICAL CHARACTERISTICS (5.) (CL = 50 pF, TA = 25 C) (VEE VSS unless otherwise indicated)


VDD – VEE

Vdc

Typ (6.)

All Types

Propagation Delay Times (Figure 6)

Switch Input to Switch Output (RL = 10 kΩ)MC14051

tPLH, tPHL = (0.17 ns/pF) CL + 26.5 nstPLH, tPHL = (0.08 ns/pF) CL + 11 ns

tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns

tPLH, tPHL

5.010

15

3515

12

MC14052tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns



5.0

10

15

30

12

10

MC14053

tPLH, tPHL = (0.17 ns/pF) CL + 16.5 nstPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns


5.010

15

258.0

6.0

Inhibit to Output (R 10 kΩ V V ) t t



Inhibit to Output (RL = 10 kΩ, VEE = VSS)

Output “1” or “0” to High Impedance, orHigh Impedance to “1” or “0” LevelMC14051B

tPHZ, tPLZ,

tPZH, tPZL

5.0

10

15

350

170

140

MC14052B 5.010

15

300155

125

MC14053B 5.010

15

275140

110

Control Input to Output (RL = 10 kΩ, VEE = VSS)MC14051B

tPLH, tPHL

5.0

1015

360

160120

MC14052B 5.010

15

325130

90

MC14053B 5.0

1015

300

12080

Second Harmonic Distortion(RL = 10KΩ, f = 1 kHz) V in = 5 VPP

— 10 0.07

Bandwidth (Figure 7)(RL = 1 kΩ, Vin = 1/2 (VDD –VEE) p–p, CL = 50pF

20 Log (Vout /Vin) = – 3 dB)

BW 10 17

Off Channel Feedthrough Attenuation (Figure 7)RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p

fin = 4.5 MHz — MC14051B

fin = 30 MHz — MC14052B

fin = 55 MHz — MC14053B

— 10 – 50

Channel Separation (Figure 8)

(RL = 1 kΩ, Vin = 1/2 (VDD –VEE) p–p,

fin = 3.0 MHz

— 10 – 50

MC14051B, MC14052B, MC14053B

IN/OUT

LEVEL

CONVERTED

CONTROL

VDD

VDD VDDVDD

OUT/IN

VEE

IN/OUT OUT/IN



Figure 1. Switch Circuit Schematic

VEECONTROL

TRUTH TABLE

Control Inputs

Select ON Switches

Inhibit C* B A MC14051B MC14052B MC14053B

0 0 0 0 X0 Y0 X0 Z0 Y0 X0

0 0 0 1 X1 Y1 X1 Z0 Y0 X1

0 0 1 0 X2 Y2 X2 Z0 Y1 X0

0 0 1 1 X3 Y3 X3 Z0 Y1 X1

0 1 0 0 X4 Z1 Y0 X0

0 1 0 1 X5 Z1 Y0 X1

0 1 1 0 X6 Z1 Y1 X0

0 1 1 1 X7 Z1 Y1 X1

1 x x x None None None

*Not applicable for MC14052x = Don’t Care

16 VDD

8 VSS 7 VEE

BINARY TO 1–OF–4

DECODER WITH

INHIBIT

LEVEL

CONVERTER

INH 6

A 10

B 9

X0 12

X1 14

BINARY T

DECOD

INH

LEVEL

CONVERTER

16 VDD

8 VSS 7 VEE

INH 6A 11B 10

C 9

Figure 2. MC14051B Funct

INH 6A 11B 10

C 9

X0 13

X1 14

X2 15

X3 12

X4 1

X5 5

X6 2

X7 4

8 VSS 7 VEE

16 VDD

BINAR

DECLEVEL

CONVERTER

MC14051B, MC14052B, MC14053B

TEST CIRCUITS

Figure 5. ∆V Across Switch Figure 6. Propagation

Control and Inhibi

CONTROL

SECTION

OF IC

SOURCE

V

ON SWITCH

PULSE

GENERATOR

INH

A

BC

VDD

LOAD



Figure 7. Bandwidth and Off–Channel

Feedthrough Attenuation

Figure 8. Channel

(Adjacent Channels Us

INH

AB

C

VSS

Vin

RL CL = 50 pF

Vout

VDD – VEE

2

INH

AB

C

OFF

ON

VinVDD – VEE

2

INH

AB

C

R1

RL CL = 50 pF

Vout

CONTROL

SECTION

OF IC

OFF

OTH

CHA

COMMON

A, B, and C inputs used to turn ON

or OFF

the switch under test.

MC14051B, MC14052B, MC14053B

Figure 11. Channel Resistance (RON) Test Circuit

VDD

VEE = VSS

10 k

VDD

KEITHLEY 160

DIGITAL

MULTIMETER

1 kΩ

RANGE X–Y

PLOTTER

TYPICAL RESISTANCE CHARACTERISTICS

M S )

350

300

M S )

350

300



Figure 12. VDD = 7.5 V, VEE = – 7.5 V Figure 13. VDD = 5.0 V, V

R O N ,

“ O N ” R E S I S T A N C E ( O

H M

250

200

150

100

0

50

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10

Vin, INPUT VOLTAGE (VOLTS)

TA = 125°C

25°C

– 55°C R O N ,

“ O N ” R E S I S T A N C E ( O

H M

250

200

150

100

0

50

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.

Vin, INPUT VOLTAGE (

Figure 14. VDD = 2.5 V, VEE = – 2.5 V

R O N ,

“ O N ” R E S I S T A N C E ( O H M S )

700

600

500

400

300

200

0

100

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10


TA = 125°C

25°C

– 55°C

Figure 15. Comparison at 2

R O N ,

“ O N ” R E S I S T

A N C E ( O H M S )

350

300

250

200

150

100

0

50

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.


TA = 25°C

VDD

MC14051B, MC14052B, MC14053B


Figure A illustrates use of the on–chip level converterdetailed in Figures 2, 3, and 4. The 0–to–5 V Digital Controlsignal is used to directly control a 9 Vp–p analog signal.

The digital control logic levels are determined by VDDand VSS. The VDD voltage is the logic high voltage; the VSSvoltage is logic low. For the example, VDD = + 5 V = logic

high at the control inputs; VSS = GND = 0 V = logic low.The maximum analog signal level is determined by VDD

and VEE. The VDD voltage determines the maximumrecommended peak above VSS. The VEE voltagedetermines the maximum swing below VSS. For theexample, VDD – VSS = 5 V maximum swing above VSS;VSS – VEE = 5 V maximum swing below VSS. The exampleshows a ± 4.5 V signal which allows a 1/2 volt margin at each

peak. If voltage transients above VDDanticipated on the analog channels, exrecommended as shown in Figure B. Tsmall signal types able to absorb the current surges during clipping.

The absolute maximum potentia

VDD and VEE is 18.0 V. Most paramet15 V which is the recommended

between VDD and VEE.Balanced supplies are not required

be greater than or equal to VEE. For V, VSS = + 5 V, and VEE – 3 V is accbelow.




+ 5 V – 5 V

VDD VSS VEE

9 Vp–p

ANALOG SIGNAL


CONTROL SIGNALS

SWITCH

I/O

INHIBIT,

A, B, C

COMMON

O/I

9 Vp–p

ANALOG SIGNAL

+ 5 V

EXTERNALCMOS

DIGITAL

CIRCUITRY

MC14051B

MC14052B

MC14053B


VDD VDD

VEE VEE

DX DX

DX DX

ANALOG

I/O

COMMON

O/I

POSSIBLE SUPPLY CONNECTIONS

MC14051B, MC14052B, MC14053B

ORDERING & SHIPPING INFORMATION:

Device Package Shipping


MC14051BD SOIC–16 48 Units per Rail



MC14051BDTEL TSSOP–16 2000 Units / Tape & Reel

MC14051BDTR2 TSSOP–16 2500 Units / Tape & Reel

MC14051BF SOEIAJ–16 See Note 7.

MC14051BFEL SOEIAJ–16 See Note 7.


MC14052BD SOIC–16 48 Units per Rail

ORDERING & SHIPPING INFORMA


MC14053BD SOIC–16

MC14053BDR2 SOIC–16 250


MC14053BDTEL TSSOP–16 200

MC14053BDTR2 TSSOP–16 250

MC14053BF SOEIAJ–16

MC14053BFEL SOEIAJ–16

7. For ordering information on the EIApackages, please contact your local Oresentative.





MC14052BDTR2 TSSOP–16 2500 Units / Tape & Reel

MC14052BF SOEIAJ–16 See Note 7.

MC14052BFEL SOEIAJ–16 See Note 7.

The MC14060B is a 14–stage binary ripple counter with an on–chip

oscillator buffer. The oscillator configuration allows design of eitherRC or crystal oscillator circuits. Also included on the chip is a resetfunction which places all outputs into the zero state and disables theoscillator. A negative transition on Clock will advance the counter tothe next state. Schmitt trigger action on the input line permits veryslow input rise and fall times. Applications include time delay circuits,counter controls, and frequency dividing circuits.

• Fully static operation

http://onsem

PDIP–16

P SUFFI

CASE 64



• Diode Protection on All Inputs• Supply Voltage Range = 3.0 V to 18 V• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range• Buffered Outputs Available from Stages 4 Through 10 and

12 Through 14• Common Reset Line• Pin–for–Pin Replacement for CD4060B





(DC or Transient)

–0.5 to VDD + 0.5 V


± 10 mA



500 mW



TL Lead Temperature


260 °C



A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14060BCP PDIP–

MC14060BD SOIC–

C C

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

TSSOP–

DT SUFF

CASE 94

MC14060B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

RESET

Q9

Q8

Q10

VDD

OUT 2

OUT 1

CLOCK

Q6

Q13

Q12

VSS

Q4

Q7

Q5

Q14



TRUTH TABLE


L No Change

L Advance to next state

X H All Outputs are low

X = Don’t Care

LOGIC DIAGRAM

OUT 2

OUT 1

CLOCK

RESET12

11

10

9 Q4 Q5 Q1257 1

C Q

RC Q

C Q

RC Q

C Q

RC Q

C Q

RC Q

C

C

Q6 = PIN 4

Q7 = PIN 6

Q8 = PIN 14

Q9 = PIN 13

Q10 =

MC14060B


VDD – 55 C 25 C


Min Max Min Typ (4.)

Max M


Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—


10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4

9

14


(VO = 4.5 or 0.5 V)

(VO = 9.0 or 1.0 V)

(VO = 13.5 or 1.5 V)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 V) “1” Level

(VO = 1.0 or 9.0 V)

(VO = 1.5 or 13.5 V)

VIH 5.0

10

15

3.5

7.0

11.0

—

—

—

3.5

7.0

11.0

2.75

5.50

8.25

—

—

—

3

7

1




(VO = 4.5 Vdc) (For Input 11

(VO = 9.0 Vdc) and Output 10)

(VO = 13.5 Vdc)

VIL

5.0

10

15

—

—

—

1.0

2.0

2.5

—

—

—

2.25

4.50

6.75

1.0

2.0

2.5

—

—

—

(VO = 0.5 Vdc) “1” Level

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

VIH 5.0

10

15

4.0

8.0

12.5

—

—

—

4.0

8.0

12.5

2.75

5.50

8.25

—

—

—

4

8

1


(VOH = 2.5 V) (Except Source

(VOH = 4.6 V) Pins 9 and 10)(VOH = 9.5 V)

(VOH = 13.5 V)

IOH

5.0

5.010

15

– 3.0

– 0.64 – 1.6

– 4.2

—

— —

—

– 2.4

– 0.51 – 1.3

– 3.4

– 4.2

– 0.88 – 2.25

– 8.8

—

— —

—

–

– –

–

(VOL = 0.4 V) Sink

(VOL = 0.5 V)

(VOL = 1.5 V)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0

0

2


Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

1015

—

— —

5.0

1020

—

— —

0.005

0.0100.015

5.0

1020

—

— —



Per Package)

(CL = 50 pF on all outputs,

all buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14060B

SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25 C)


VDD

Vdc Min Typ (7.)

Output Rise Time (Counter Outputs) tTLH 5.0

10

15

—

—

—

40

25

20

Output Fall Time (Counter Outputs) tTHL 5.0

10

15

—

—

—

50

30

20


Clock to Q4

tPLH

tPHL

5.0

10

15

—

—

—

415

175

125

Clock to Q14 5.0

10

15

—

—

—

1.5

0.7

0.4

Clock Pulse Width twH 5.0

10

100

40

65

30

15 30 20

Clock Pulse Frequency fφ 5.0

10

15

—

—

—

5

14

17

Clock Rise and Fall Time tTLH

tTHL

5.0

10

15

No Limit

Reset Pulse Width tw 5.0

10

15

120

60

40

40

15

10


Reset to On

tPHL 5.0

10

15

—

—

—

170

80

60


PULSE

GENERATOR

ID

VDD

500 µF 0.01 µF

CLOCK

NC

NC

Q4

Q5

QnR

OUT1

OUT2

VSS CL

CL

CL

PULSE

GENERATOR

VDD

CLOCK

NCNC

Q4

Q5

QnR

OUT1OUT2

VSS

20 ns

CLOCK

t

90%50%

10%

MC14060B

Figure 3. Oscillator Circuit Using RC Configuration

CLOCK 11

RESET

RS Ctc

Rtc

10 OUT 1 9 OUT 2

f 12.3RtcCtc

if 1 kHz ≤ f ≤ 100 kHz

and 2Rtc < RS < 10Rtc

(f in Hz, R in ohms, C in farads)

The formula may vary for other frequenc

maximum value for the resistors in 1 MΩ.

TYPICAL RC OSCILLATOR CHARACTERISTICS

4.0

8.0

( % )

VDD = 15 V

Y ( k H z )

100

50

20

VDD



Figure 4. RC Oscillator Stability Figure 5. RC Oscillator Fre

Function of RTC an

– 8.0

– 12

– 16

– 4.0

0

1251007550250 – 25 – 55


F R E Q U E N C Y D E V I A T I O N

1.0 V

5.0 V

RTC = 56 kΩ

C = 1000 pF

RS = 0, f = 10.15 kHz @ VDD = 10, TA = 25°C

RS = 120 kΩ, f= 7.8 kHz @ VDD = 10V, TA = 25°C

f , O S C I L L A T O R F R E Q U E N C Y

10

5

2

1

0.5

0.2

0.11.0 k 10 kRTC, RESISTANCE (OH

0.0001 0.001C, CAPACITANCE (µ

f AS A FUNCTION

OF C

(RTC = 56 kΩ)

(RS = 120 k)

Figure 6. Typical Crystal Oscillator Circuit

CLOCK

11

RESET 9 OUT 210 OUT 1

18M

RO

CS CT

Characteristic

500

Ci

Crystal Characteristics

Resonant Frequency

Equivalent Resistance, RS

5

External Resistor/Capacitor Values

RO

CT

CS

Frequency StabilityFrequency Changes as a

Function of VDD (TA = 25 C)

V Ch f 5 0 V 10V

The MC14066B consists of four independent switches capable of

controlling either digital or analog signals. This quad bilateral switchis useful in signal gating, chopper, modulator, demodulator andCMOS logic implementation.

The MC14066B is designed to be pin–for–pin compatible with theMC14016B, but has much lower ON resistance. Input voltage swingsas large as the full supply voltage can be controlled via eachindependent control input.

• Triple Diode Protection on All Control Inputs

http://onsem

PDIP–14

P SUFFIX



• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Linearized Transfer Characteristics• Low Noise — 12 nV/ √Cycle, f ≥ 1.0 kHz typical• Pin–for–Pin Replacement for CD4016, CD4016, MC14016B• For Lower RON, Use The HC4066 High–Speed CMOS Device

MAXIMUM RATINGS (Voltages Referenced to VSS

) (Note 2.)




(DC or Transient)

–0.5 to VDD + 0.5 V


per Control Pin

± 10 mA



500 mW



TL Lead Temperature


260 °C





t ti lt g l t i fi ld H ti m t b t k t id

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14066BCP PDIP–

MC14066BD SOIC–

MC14066BDR2 SOIC–

CASE 64

SOIC–14

D SUFFIX

CASE 751

TSSOP–1

DT SUFFCASE 948

SOEIAJ–1

F SUFFIX

CASE 96

MC14066B

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT 4

IN 4

CONTROL 4

CONTROL 1

VDD

IN 3

OUT 3

IN 2

OUT 2

OUT 1

IN 1

VSS

CONTROL 3

CONTROL 2

LOGIC DIAGRAM AND TRU

(1/4 OF DEVICE SHOW

BLOCK DIAGRAM

CONTROL 113



IN/OUT

CONTROL

IN 4

CONTROL 4

IN 3

CONTROL 3

IN 2

CONTROL 2

IN 1

CONTROL 1OUT 1

OUT 2

OUT 3

OUT 4

1

5

4

6

8

12

11

2

3

9

10

VDD = PIN 14

VSS = PIN 7

Control Switch

0 = VSS OFF

1 = VDD ON

Logic Diagram

VSS ≤ V

VSS ≤ Vo

CIRCUIT SCHEMATIC

(1/4 OF CIRCUIT SHOWN)

VDDVDDVDD

VDDVDD VDD VDD

VSS

MC14066B


– 55 C 25 C




Range

VDD — 3.0 18 3.0 — 18


Package

IDD 5.0

1015

Control Inputs:

Vin = VSS or VDD,Switch I/O: VSS VI/O

VDD, and


—

— —

0.25

0.51.0

—

— —

0.005

0.0100.015

0.25

0.51.0


(Dynamic Plus Quiescent,

Per Package

ID(AV) 5.0

10

15

TA = 25 C only The

channel component,


not included.)


Typical (0.20 µA/kHz) f + IDD


CONTROL INPUTS (Voltages Referenced to VSS)

Low Level Input Voltage VIL 5 0 Ron per spec 1 5 2 25 1 5




15

Ron = per spec,Ioff = per spec

— —

—

1.53.0

4.0

— —

—

2.254.50

6.75

1.53.0

4.0


10

15

Ron = per spec,

Ioff = per spec

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

Input Leakage Current Iin 15 Vin = 0 or VDD — ± 0.1 — ±0.00001 ± 0.1


SWITCHES IN AND OUT (Voltages Referenced to VSS)

Recommended Peak–to–

Peak Voltage Into or Out

of the Switch



Dynamic Voltage Across

the Switch (5.) (Figure 1)




10

15

∆Vswitch 500 mV (5.),

Vin

= VIL

or VIH(Control), and Vin =

0 to VDD (Switch)

—

—

—

800

400

220

—

—

—

250

120

80

1050

500

280


Any Two Channels

in the Same Package

∆Ron 5.0

10

15

—

—

—

70

50

45

—

—

—

25

10

10

70

50

45


Current (Figure 6)



Channel or Any One

Channel

— ±100 — ± 0.05 ±100

Capacitance, Switch I/O CI/O — Switch Off — — — 10 15

Capacitance, Feedthrough

(Switch Off)

CI/O — — — — 0.47 —

MC14066B

ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25 C unless otherwise noted.)

Characteristic SymbolVDDVdc Min Typ (7.)

Propagation Delay Times VSS = 0 Vdc

Input to Output (RL = 10 kΩ)




tPLH, tPHL

5.0

10

15

—

—

—

20

10

7.0

Control to Output (RL = 1 kΩ) (Figure 2)Output “1” to High Impedance

tPHZ5.0

10

15

—

—

—

40

35

30

Output “0” to High Impedance tPLZ 5.0

10

15

—

—

—

40

35

30

High Impedance to Output “1” tPZH 5.0

10

15

—

—

—

60

20

15



High Impedance to Output “0” tPZL 5.0

10

15

—

—

—

60

20

15

Second Harmonic Distortion VSS = – 5 Vdc

(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,

RL = 10 kΩ, f = 1.0 kHz)

— 5.0 — 0.1

Bandwidth (Switch ON) (Figure 3) VSS = – 5 Vdc

(RL = 1 kΩ, 20 Log (Vout /Vin) = – 3 dB, CL = 50 pF,

Vin = 5 Vp–p)

— 5.0 — 65

Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc

(Vin = 5 Vp–p, RL = 1 kΩ, fin = 1.0 MHz) (Figure 3)

— 5.0 — – 50

Channel Separation (Figure 4) VSS = – 5 Vdc

(Vin = 5 Vp–p, RL = 1 kΩ, fin = 8.0 MHz)

(Switch A ON, Switch B OFF)

— 5.0 — – 50

Crosstalk, Control Input to Signal Output (Figure 5)

VSS = – 5 Vdc

(R1 = 1 kΩ, RL = 10 kΩ, Control tTLH = tTHL = 20 ns)

— 5.0 — 300


MC14066B

TEST CIRCUITS

Figure 1. ∆V Across Switch Figure 2. Turn–On Delay T

and Waveform

CONTROL

SECTION

OF IC

SOURCE

V

LOAD

ON SWITCH

Vout

Vout

VC

VC

Vout

Vin20 ns

90

5tPZH

tPZL90%

10%



and Waveform

Figure 3. Bandwidth and


Figure 4. Channel S

Vout

CLRL

VDD VSS

VC

Vin

VDD

– VSS

2

VDD – VSS

2

Vin

VDD

VSS

Vin

1 kV

out

RL CL = 50 pF

VC = VDD FOR BANDWIDTH TEST

VC = VSS FOR FEEDTHROUGH TEST

OFF CH

CONTROL

SECTION

OF IC10 k

MC14066B

Figure 7. Channel Resistance (RON) Test Circuit

VDD

VSS

10 k

VDD

KEITHLEY 160

DIGITAL

MULTIMETER

1 kΩ

RANGE X–Y

PLOTTER


350 350



Figure 8. VDD = 7.5 V, VSS = – 7.5 V Figure 9. VDD = 5.0 V, V

R O N


350

300

250

200

150

100

0

50

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10


TA = 125°C

25°C – 55°C R

O N


350

300

250

200

150

100

0

50

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.


R O N , “ O

N ” R E S I S T A N C E ( O H M S )

700

600

500

400

300

200

100

TA = 125°C

25°C

– 55°C R O N , “ O

N ” R E S I S T A N C E ( O H M S )

350

300

250

200

150

100

50

TA = 25°C

VDD

MC14066B


Figure A illustrates use of the Analog Switch. The 0–to–5 volt digital control signal is used to directly control a5 volt peak–to–peak analog signal.

The digital control logic levels are determined by VDDand VSS. The VDD voltage is the logic high voltage, the VSSvoltage is logic low. For the example, VDD = + 5 V = logic

high at the control inputs; VSS = GND = 0 V = logic low.The maximum analog signal level is determined by VDDand VSS. The analog voltage must not swing higher thanVDD or lower than VSS.

The example shows a 5 volt peak–to–peak signal whichallows no margin at either peak. If voltage transients above

VDD and/or below VSS are anticichannels, external diodes (Dx) are rein Figure B. These diodes should be sto absorb the maximum anticipated clipping.

The absolute maximum potentia

VDD and VSS is 18.0 volts. Most paramto 15 volts which is the recommended

between VDD and VSS.

+ 5 V




VDD VSS

5 Vp–p

ANALOG SIGNAL


CONTROL SIGNALS

SWITCH

IN

MC14066B

SWITCH

OUT

5 Vp–p

ANALOG SIGNAL+ 5 V

EXTERNAL

CMOS

DIGITAL

CIRCUITRY


VDD VDD

VSS VSS

DX DX

DX DX

SWITCH

IN

SWITCH

OUT

The MC14067 multiplexer/demultiplexer is a digitally controlled

analog switch featuring low ON resistance and very low leakagecurrent. This device can be used in either digital or analogapplications.

The MC14067 is a 16–channel multiplexer/demultiplexer with aninhibit and four binary control inputs A, B, C, and D. These controlinputs select 1–of–16 channels by turning ON the appropriate analogswitch (see MC14067 truth table.)

• Low OFF Leakage Current•

Matched Channel Resistance• L Q i t P C ti

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CASE 70



Matched Channel Resistance• Low Quiescent Power Consumption• Low Crosstalk Between Channels• Wide Operating Voltage Range: 3 to 18 V• Low Noise• Pin for Pin Replacement for CD4067B



VDD DC Supply Voltage Range – 0.5 to + 18.0 V


(DC or Transient)

– 0.5 to VDD + 0.5 V

Iin Input Current (DC or Transient),

per Control Pin

± 10 mA

Isw Switch Through Current ± 25 mA



500 mW

TA Ambient Temperature Range – 55 to + 125 C

Tstg Storage Temperature Range – 65 to + 150 C

TL Lead Temperature


260 C



Device Packa

ORDERING INF

MC14067BCP PDIP–2

MC14067BDW SOIC–


SOIC–2

DW SUFF

CASE 75

A = Asse

WL or L = Wafe

YY or Y = Year

WW or W = Work

MC14067B

MC14067 TRUTH TABLE

Control InputsSelected

A B C D Inh Channel

X X X X 1 None

0 0 0 0 0 X0

1 0 0 0 0 X1

0 1 0 0 0 X2

1 1 0 0 0 X3

0 0 1 0 0 X4

1 0 1 0 0 X5

0 1 1 0 0 X6

1 1 1 0 0 X7

0 0 0 1 0 X8

1 0 0 1 0 X9

0 1 0 1 0 X10

1 1 0 1 0 X11

0 0 1 1 0 X12

1 0 1 1 0 X130 1 1 1 0 X14



0 1 1 1 0 X14

1 1 1 1 0 X15

X3

X5

X6

X7

X

X1

X2

X4 X11

X10

X9

X8

VDD

INHIBIT

X15

X14

5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

13

11

12

21

22

23

24

D

C

X13

X12

B

VSS

A

X0

MC14067B

PIN ASSIGNMENT

MC14067B

MC14067B

16–Channel Analog


CONTROLS

SWITCHES

IN/OUT

COMMON

OUT/IN

2122

23

2

3

4

5

6

7

9

13

8

14

11

10

15

1

INHIBIT

A

B

C

D

X0

X1

X2

X3

X4

X5

X6

X7

X8

X9X10

X

VDD = PIN 24



16

17

18

19

20 X11

X12

X13

X14

X15

DD

VSS = PIN 12

MC14067 FUNCTIONAL DIAGRAM

1–OF–16 DECODER

INHIBITABCD

X15X14X13X12X11X10X9X8X7X6X5X4X3X2X1X0

CONTROL

INPUTS

X

IN/OUTX

OUT/IN

MC14067B


– 55°C 25 C


SUPPLY REQUIREMENTS (Voltages Referenced to VSS)


Range

VDD — 3.0 18 3.0 — 18


Package

IDD 5.0

1015

Control Inputs: Vin =

VSS or VDD,Switch I/O: VSS VI/O

VDD, and


—

— —

5.0

1020

—

— —

0.005

0.0100.015

5.0

1020


(Dynamic Plus

Quiescent,

Per Package

ID(AV) 5.0

10

15

TA = 25 C only (The

channel component,


not included.)

(0.07 µA/kHz) f + IDTypical (0.20 µA/kHz) f + ID

(0.36 µA/kHz) f + ID

CONTROL INPUTS — INHIBIT, A, B, C, D (Voltages Referenced to VSS)


10

15

Ron = per spec,

Ioff = per spec

—

—

1.5

3.0

4 0

—

—

2.25

4.50

6 75

1.5

3.0

4 0



15 — 4.0 — 6.75 4.0


10

15

Ron = per spec,

Ioff = per spec

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—



SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y (Voltages Referenced to VSS)

Recommended Peak–to– Peak Voltage Into or

Out of the Switch



Dynamic Voltage

Across the Switch (4.)

(Figure 1)




1015


Vin = VIL or VIH(Control), and Vin

0 to VDD (Switch)

—

— —

800

400220

—

— —

250

12080

1050

500280


Any Two Channels

in the Same Package

∆Ron 5.0

10

15

—

—

—

70

50

45

—

—

—

25

10

10

70

50

45


Current (Figure 2)



Channel or Any One

Channel

— ± 100 — ± 0.05 ±100

Capacitance, Switch I/O CI/O — Inhibit = VDD — — — 10 —

Capacitance, Common O/I CO/I — Inhibit = VDD

MC14067B

ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25 C)


VDD – VSS

Vdc Typ (5.)

Propagation Delay Times

Channel Input–to–Channel Output (RL = 200 kΩ)

MC14067B

tPLH, tPHL

(Figure 3) 5.0

10

15

35

15

12

Control Input–to–Channel OutputChannel Turn–On Time (RL = 10 kΩ)

MC14067B

tPZH, tPZL

(Figure 4) 5.0

10

15

240

115

75

Channel Turn–Off Time (RL = 300 kΩ)

MC14067B

tPHZ, tPLZ

(Figure 4) 5.0

10

15

250

120

75

Any Pair of Address Inputs to OutputMC14067B

tPLH, tPHL



MC14067B

5.0

10

15

280

115

85

Second Harmonic Distortion

(RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p)

— 10 0.3

ON Channel Bandwidth

[RL = 1 kΩ, Vin = 1/2 (VDD – VSS) p–p(sine–wave)]

20 Log10 (Vout /Vin) = – 3 dB MC14067B

BW

(Figure 5) 10 15Off Channel Feedthrough Attenuation

[RL = 1 kΩ, Vin = 1/2 (VDD –VSS) p–p(sine–wave)]

fin = 20 MHz – MC14067B

—

(Figure 5)

10 – 40

Channel Separation

[RL = 1 kΩ, Vin = 1/2 (VDD –VSS) p–p (sine–wave)]

fin = 20 MHz

—

(Figure 6)

10 – 40

Crosstalk, Control Inputs–to–Common O/I

(R1 = 1 kΩ, RL = 10 kΩ,

Control tr

= tf= 20 ns, Inhibit = V

SS)

—

(Figure 7)

10 30


MC14067B

Figure 1. ∆V Across Switch Figure 2. Off Channel Leaka

CONTROL

SECTION

OF IC

SOURCE

V

LOAD

ON SWITCH

CONTROL

SECTION

OF IC

OFF CHANN

OTHER

CHANNEL(S

A

V

PULSEGENERATOR

VC

ABC



Figure 3. Propagation Delay Test Circuit

and Waveforms Vin to Vout

Figure 4. Turn–On and Dela

Test Circuit and Wave

VDD

Vout

CL = 50 pFRL

Vin

ABCD

INH

Vin

Vout

20 ns 20 nsVDD

VSS

50%

10%

tPLH tPHL

90%50%

CD

INH R

Vin

VDD VSS

20 ns90%

50%10

Vout

Vout

VC

50%

50%

tPZH, tPZL

MC14067B



Figure 6. Channel S

(Adjacent Channels Us

A, B, and C inputs used to turn ON or OFF


ABCD

INH

Vin

RL CL = 50 pF

Vout

VDD

RL

Vin

ABCD

INH OFF

ON

VC

ABC



Figure 7. Crosstalk, Control to Common O/I

CD

INH RL CL = 50 pF

Vout

R1

VDD

VSS

10 k

KEITHLEY 160

DIGITAL

MULTIMETER

X–Y

PLOTTER

1 kΩ

RANGE

VDD

VAVB

ABCD

INH

CL Vout

Vout

VB

VA

tPHL

MC14067B


Figure 10. VDD = 7.5 V, VSS = – 7.5 V Figure 11. VDD = 5.0 V,

R O N ,


350

300

250

200

150

100

0

50

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10


TA = 125°C

25°C

– 55°C R O N ,


350

300

250

200

150

100

0

50

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.




Figure 12. VDD = 2.5 V, VSS = – 2.5 V

R O N ,

“ O N ” R E S I S

T A N C E ( O H M S )

700

600

500

400

300

200

0

100

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.2 4.0 6.0 8.0 10


TA = 125°C

25°C

– 55°C

Figure 13. Comparison at 2

R O N ,

“ O N ” R E S I S

T A N C E ( O H M S )

350

300

250

200

150

100

0

50

– 8.0 – 10 – 6.0 – 4.0 – 2.0 0 0.


TA = 25°C

VD

MC14067B


Figure A illustrates use of the AnalogMultiplexer/Demultiplexer. The 0–to–5 volt Digital Controlsignal is used to directly control a 5 Vp–p analog signal.

The digital control logic levels are determined by VDDand VSS. The VDD voltage is the logic high voltage; the VSSvoltage is logic low. For the example. VDD = + 5 V = logichigh at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by VDDand VSS. The analog voltage must swing neither higher thanVDD nor lower than VSS. The example shows a 5 Vp–p

signal which allows no margin at etransients above VDD and/or below Vthe analog channels, external diodes (as shown in Figure B. These diodes stypes able to absorb the maximum antiduring clipping.

The absolute maximum potential diand VSS is 18.0 volts. Most paramete15 V which is the recommended between VDD and VSS.

+ 5 V

VDD VSS




5 Vp–p

ANALOG SIGNAL


CONTROL SIGNALS

SWITCH

I/O

MC14067B

COMMON

O/I

5 Vp–p

ANALOG SIGNAL+ 5 V

EXTERNAL

CMOS

DIGITALCIRCUITRY


VDD VDD

VSS VSS

DX DX

DX DX

SWITCH

I/O

COMMON

O/I

The MC14069UB hex inverter is constructed with MOS P–channeland N–channel enhancement mode devices in a single monolithicstructure. These inverters find primary use where low power

dissipation and/or high noise immunity is desired. Each of the sixinverters is a single stage to minimize propagation delays.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range• Triple Diode Protection on All Inputs• Pin–for–Pin Replacement for CD4069UB• Meets JEDEC UB Specifications

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CASE 64







(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C










A = Assemb

WL or L = Wafer LYY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14069UBCP PDIP–

MC14069UBD SOIC–


SOIC–14

D SUFFIX

CASE 751

TSSOP–1

DT SUFF

CASE 948

SOEIAJ–1

F SUFFIX

CASE 96

MC14069UB

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT 5

IN 5

OUT 6

IN 6

VDD

OUT 4

IN 4

OUT 2

IN 2

OUT 1

IN 1

VSS

OUT 3

IN 3

CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN

LOGIC DIAGRAM

1 2

VDD = PIN 14

VDD



13

11

9

5

3

12

10

8

6

4VDD PIN 14

VSS = PIN 7

VSS

OUTPUTINPUT*

*Double diode protection on allinputs not shown.


PULSE

GENERATOR

VDD

VSS7

INPUT

OUTPUT

CL

14

20 ns

tTHL

OUTPUT

INPUT

tPHL

90%50%10%

90%50%10%

MC14069UB


S mbo VDD – 55 C 25 C

Characteristic l



Vin = VDD

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

Vin = 0 “1” Level VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 Vdc)

(VO = 9.0 Vdc)

(VO = 13.5 Vdc)

VIL

5.0

10

15

—

—

—

1.0

2.0

2.5

—

—

—

2.25

4.50

6.75

1.0

2.0

2.5

—

—

—

“1” Level

(VO = 0.5 Vdc)

(VO = 1.0 Vdc)

(VO = 1.5 Vdc)

VIH

5.0

10

15

4.0

8.0

12.5

—

—

—

4.0

8.0

12.5

2.75

5.50

8.25

—

—

—

4

8

12


(VOH = 4 6 Vdc)

IOH

5.0

5 0

– 3.0

– 0 64

—

—

– 2.4

– 0 51

– 4.2

– 0 88

—

—

–

– 0



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

5.0

10

15

– 0.64

– 1.6

– 4.2

—

—

—

– 0.51

– 1.3

– 3.4

– 0.88

– 2.25

– 8.8

—

—

—

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

0.25

0.5

1.0

—

—

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

—

—



Per Gate) (CL = 50 pF)

IT 5.0

10

15

IT = (0.3 µA/kHz) f + IDD /6

IT = (0.6 µA/kHz) f + IDD /6

IT = (0.9 µA/kHz) f + IDD /6

Output Rise and Fall Times (5.)

(CL = 50 pF)tTLH, tTHL = (1.35 ns/pF) CL + 33 ns



tTLH,

tTHL 5.010

15

— —

—

— —

—

— —

—

10050

40

200100

80

— —

—

Propagation Delay Times (5.)

(CL = 50 pF)




tPLH,

tPHL

5.0

10

15

—

—

—

—

—

—

—

—

—

65

40

30

125

75

55

—

—

—


5. The formulas given are for the typical characteristics only at 25 C.6. To calculate total supply current at loads other than 50 pF:

I (C ) I (50 pF) + (C 50) Vfk

Quad Exclusive “OR” and “NOR” Gates

The MC14070B quad exclusive OR gate and the MC14077B quadexclusive NOR gate are constructed with MOS P–channel andN–channel enhancement mode devices in a single monolithicstructure. These complementary MOS logic gates find primary usewhere low power dissipation and/or high noise immunity is desired.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc• All Outputs Buffered• Capable of Driving Two Low–Power TTL Loads or One Low–Power


• Double Diode Protection on All Inputs• MC14070B — Replacement for CD4030B and CD4070B Types

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p yp• MC14077B — Replacement for CD4077B Type





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C







to the range VSS (Vi or V ) VDD

XX = Specific

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC140XXBCP PDIP–

MC140XXBD SOIC–

MC140XXBDR2 SOIC–

MC140XXBF SOEIAJ–

SOIC–14

D SUFFIX

CASE 751

SOEIAJ–1

F SUFFIXCASE 96

MC140XXBFEL SOEIAJ–



MC14070B, MC14077B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4

9

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7


(VOH = 4.6 Vdc)

IOH

5.0

5.0

– 3.0

– 0.64

—

—

– 2.4

– 0.51

– 4.2

– 0.88

—

—

–

–



(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

10

15

– 1.6

– 4.2

—

—

– 1.3

– 3.4

– 2.25

– 8.8

—

—

–

–


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0

0

2

Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1


Cin — — — — 5.0 7.5

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

0.25

0.5

1.0

—

—

—

0.0005

0.0010

0.0015

0.25

0.5

1.0



Per Package)


buffers switching)

IT 5.0

10

15




Output Rise and Fall Times (5.)

(CL = 50 pF)




tTLH,

tTHL

5.0

10

15

—

—

—

—

—

—

—

—

—

100

50

40

200

100

80

Propagation Delay Times (5.)

(CL = 50 pF)

tPLH, tPHL = (0.90 ns/pF) CL + 130ns



tPLH,

tPHL

5.0

10

15

—

—

—

—

—

—

—

—

—

175

75

55

350

150

110

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe5 The formulas given are for the typical characteristics only at 25 C

The MC14076B 4–Bit Register consists of four D–type flip–flops

operating synchronously from a common clock. OR gatedoutput–disable inputs force the outputs into a high–impedance statefor use in bus organized systems. OR gated data–disable inputs causethe Q outputs to be fed back to the D inputs of the flip–flops. Thus theyare inhibited from changing state while the clocking process remainsundisturbed. An asynchronous master root is provided to clear all fourflip–flops simultaneously independent of the clock or disable inputs.

• Three–State Outputs with Gated Control Lines• Fully Independent Clock Allows Unrestricted Operation for the Two

Modes: Parallel Load and Do Nothing• Asynchronous Master Reset

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• Four Bus Buffer Registers• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–Power TTL Loads or One Low–Power






(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C




A = Assem

WL or L = Wafer


Device Packag

ORDERING INF

MC14076BCP PDIP–

MC14076BD SOIC–

MC14076BDR2 SOIC–

SOIC–1

D SUFFI

CASE 751

MC14076B

PIN ASSIGNMENT

13

14

15

16

9

10

11125

4

3

2

1

8

7

6D2

D1

D0

R

VDD

A

B

D3

Q1

B

A

VSS

C

Q3Q2

Q0

OUTPUT

DISABLE

DATA

DISABLE

BLOCK DIAGRAM

15

14

3RESET

D0

Q0



14

13

12

11

10

9

7

2

1

4

5

6

D0

D1

D2

D3

B

A

CLOCK

B

A

DATA

DISABLE

OUTPUT

DISABLE

VDD = PIN 16

VSS = PIN 8

Q1

Q2

Q3

FUNCTION TABLE

Inputs

Data DisableData Out ut

Reset Clock A B D Q

1 X X X X 0

0 0 X X X Qn

0 1 X X Qn

0 X 1 X Qn

0 0 0 0 0

0 0 0 1 1When either output disable A or B (or both) is (are) high the

output is disabled to the high–impedance state; however

MC14076B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1


(VOH = 4.6 Vdc)

(VOH = 9 5 Vdc)

IOH

5.0

5.0

10

– 3.0

– 0.64

1 6

—

—

– 2.4

– 0.51

1 3

– 4.2

– 0.88

2 25

—

—

–

– 0

0



(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

10

15

– 1.6

– 4.2

—

—

– 1.3

– 3.4

– 2.25

– 8.8

—

—

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2



Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15




Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 —


IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14076B



VDD

Vdc Min Typ (7.)





tTLH, tTHL

5.0

10

15

—

—

—

100

50

40


Clock to Q




tPLH, tPHL

5.0

10

15

—

—

—

300

125

90

Reset to Q




5.0

10

15

—

—

—

300

125

90

3–State Propagation Delay, Output “1” or “0”

to High Impedance

tPHZ, tPLZ 5.0

10

15

—

—

—

150

60

45

3–State Propagation Delay, High Impedance

to “1” or “0” Level

tPZH, tPZL 5.0

10

15

—

—

200

80

60



15 — 60


10

15

260

110

80

130

55

40


10

15

370

150

110

185

75

55Data Setup Time tsu 5.0

10

15

30

10

4

15

5

2

Data Hold Time th 5.0

10

15

130

60

50

65

30

25

Data Disable Setup Time tsu 5.0

10

15

220

80

50

110

40

25Clock Pulse Rise and Fall Time tTLH, tTHL 5.0

10

15

—

—

—

—

—

—


10

15

—

—

—

3.6

9.0

12




The MC14093B Schmitt trigger is constructed with MOS

P–channel and N–channel enhancement mode devices in a singlemonolithic structure. These devices find primary use where low powerdissipation and/or high noise immunity is desired. The MC14093Bmay be used in place of the MC14011B quad 2–input NAND gate forenhanced noise immunity or to “square up” slowly changingwaveforms.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–Power TTL Loads or One Low–Power


• Triple Diode Protection on All Inputs• Pin–for–Pin Compatible with CD4093• Can be Used to Replace MC14011B

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CASE 64

SOIC–14

D SUFFIX



Can be Used to Replace MC14011B• Independent Schmitt–Trigger at each Input





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C





A = Assemb

WL or L = Wafer LYY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14093BCP PDIP–

MC14093BD SOIC–

MC14093BDR2 SOIC–

D SUFFIX

CASE 751

TSSOP–1

DT SUFF

CASE 948

SOEIAJ–1

F SUFFIX

CASE 96

MC14093B

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

LOGIC DIAGRAM

4

3

65

2

1



1311


10

12

98

EQUIVALENT CIRCUIT SCHEMATIC


MC14093B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Q i C I 5 0 0 25 0 0005 0 25



Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

0.25

0.5

1.0

—

—

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

—

—



Per Package)


IT 5.0

10

15




Hysteresis Voltage VH† 5.0

10

15

0.3

1.2

1.6

2.0

3.4

5.0

0.3

1.2

1.6

1.1

1.7

2.1

2.0

3.4

5.0

0

1

1

Threshold Voltage

Positive–Going VT+ 5.0

10

15

2.2

4.6

6.8

3.6

7.1

10.8

2.2

4.6

6.8

2.9

5.9

8.8

3.6

7.1

10.8

2

4

6

Negative–Going VT– 5.010

15

0.92.5

4.0

2.85.2

7.4

0.92.5

4.0

1.93.9

5.8

2.85.2

7.4

02

4


IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14093B



VDD

Vdc Min Typ (7.)

Output Rise Time tTLH 5.0

10

15

—

—

—

100

50

40

Output Fall Time tTHL 5.0

10

15

—

—

—

100

50

40

Propagation Delay Time tPLH, tPHL 5.0

10

15

—

—

—

125

50

40

7. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential per

PULSE

GENERATOR

VDD

OUTPUT

CLVSS7

14

INPUT

20 ns

tPHL

OUTPUT

INPUT

90%

90%50%10%




LVSS7 OUTPUT

tTHL

50%10%

Vout

Vin

VH VDD

VSS

VDD

VSS

(a) Schmitt Triggers will square up

(a) inputs with slow rise and fall times.

(b) A Schmitt trigger offers

(b) noise immunity in gate

VH

Vout

Vin

Figure 2. Typical Schmitt Trigger Applications

MC14093B


VDS, DRAIN VOLTAGE (Vdc)

– 10 – 8.0 – 6.0 – 4.0 – 2.0 0

0

– 2.0

– 4.0

– 6.0

– 8.0

– 10

I O H ,

D R A I N C U R R E N T ( m A

d c )

Figure 4. Typical Ou

VDS, DRAIN VOLTAG

0 2.0 4.0 6

10

8.0

6.0

4.0

2.0

0

I O L ,

D R A I N C U R R E N T ( m A

d c )

14

7

VGS

Vout

IOH

All unused inputs

connected to ground.All unused inputs

connected to ground.

VGS

VGS = – 5.0 Vdc

c

b

a

c

b c b

a a

– 15 Vdc – 10 Vdc

a TA = –55°C

b TA = +25°C

b TA = +125°C

a b c

a

b

c

ab

c

5.

15 Vdc

VGS = 10






Characteristics Tes

V o u t ,


VDD

00 VDDVT– VT+

VH


Figure 5. Typical Transfer Characteristics

The MC14094B combines an 8–stage shift register with a data latchfor each stage and a three–state output from each latch.

Data is shifted on the positive clock transition and is shifted from theseventh stage to two serial outputs. The QS output data is for use inhigh–speed cascaded systems. The Q′S output data is shifted on thefollowing negative clock transition for use in low–speed cascadedsystems.

Data from each stage of the shift register is latched on the negativetransition of the strobe input. Data propagates through the latch whilestrobe is high.

Outputs of the eight data latches are controlled by three–statebuffers which are placed in the high–impedance state by a logic Lowon Output Enable.

• Three–State Outputs

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CASE 64

SOIC–1

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• Capable of Driving Two Low–Power TTL Loads or One Low–PowerSchottky TTL Load Over the Rated Temperature Range

• Input Diode Protection• Data Latch•

Dual Outputs for Data Out on Both Positive andNegative Clock Transitions• Useful for Serial–to–Parallel Data Conversion• Pin–for–Pin Compatible with CD4094B





–0.5 to VDD + 0.5 V



± 10 mA



500 mW




260 °C

Device Packag

ORDERING INF

MC14094BCP PDIP–1

MC14094BD SOIC–1

C C

D SUFFI

CASE 75

TSSOP–

DT SUFFCASE 94

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work W

SOEIAJ–

F SUFFI

CASE 96

MC14094B

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q7

Q6

Q5

OUTPUTENABLE

VDD

QS

Q′S

Q8

Q1

CLOCK

DATA

STROBE

VSS

Q4

Q3

Q2

PIN ASSIGNMENT

OutputParallel Outputs Serial Outputs

Clock Enable Strobe Data Q1 QN QS* Q′S

0 X X Z Z Q7 No Chg.

0 X X Z Z No Chg. Q7

1 0 X No Chg. No Chg. Q7 No Chg.



1 1 0 0 QN –1 Q7 No Chg.

1 1 1 1 QN –1 Q7 No Chg.

1 1 1 No Chg. No Chg. No Chg. Q7

Z = High Impedance X = Don’t Care

* At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and QS.

MC14094B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.9

9.9

14Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1


(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2




(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0

2


Input Capacitance(Vin = 0) Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15


IT = (14 µA/kHz) f + IDD

IT = (140 µA/kHz) f + IDD

3–State Output Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 —


IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14094B



VDD

Vdc Min Typ (8.)





tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40


Clock to Serial out QS

tPLH

, tPHL

= (0.90 ns/pF) CL

+ 305 ns


tPLH, tPHL = (0.26 ns/pF) C L + 82 ns

tPLH,

tPHL

5.0

10

15

—

—

—

350

125

95

Clock to Serial out Q’S




5.0

10

15

—

—

—

230

110

75

Clock to Parallel out




5.0

10

15

—

—

—

420

195

135

Strobe to Parallel out


tPLH, tPHL = (0.36 ns/pF) C L + 127 ns

tPLH tPHL (0 26 ns/pF) CL + 87 ns

5.0

10

15

—

—

—

290

145

100



tPLH, tPHL = (0.26 ns/pF) CL + 87 ns 15 100

Output Enable to Output

tPHZ, tPZL = (0.90 ns/pF) CL + 95 ns

tPHZ, tPZL = (0.36 ns/PF) CL + 57 ns

tPHZ, tPZL = (0.26 ns/pF) CL + 42 ns

tPHZ,

tPZL

5.0

10

15

—

—

—

140

75

55

tPLZ, tPZH = (0.90 ns/pF) CL + 180 nstPLZ, tPZH = (0.36 ns/pF) CL + 77 ns

tPLZ, tPZH = (0.26 ns/pF) CL + 57 ns

tPLZ,tPZH5.010

15

— —

—

22595

70

Setup Time

Data in to Clock

tsu 5.0

10

15

125

55

35

60

30

20

Hold Time

Clock to Data

th 5.0

10

15

0

20

20

– 40

– 10

0

Clock Pulse Width, High tWH 5.0

1015

200

10083

100

5040

Clock Rise and Fall Time tr(cl)

tf(cl)

5

10

15

—

—

—

—

—

—


10

15

—

—

—

2.5

5.0

6.0

Strobe Pulse Width tWL 5.0

10

15

200

80

70

100

40

35


MC14094B

3–STATE TEST CIRCUIT

FOR tPHZ AND tPZH

VSS

FOR tPLZ AND tPZL

VDD

1 k

OUTPUT

50 pF

O.E.

CLOCK

ST

DATA

REGISTER STAGE 1

BLOCK DIAGRAM

LATCH 1 3–STATE BUFFER

2

SERIAL

DATA IN

CLOCK CLOCK STROBE

CLOCK

CLOCK CLOCK

CLOCK

STROBE STROBE

STROBE

*



15

OUTPUT

ENABLE

2

3

4

5

6

7

8

REGISTER STAGE 2

REGISTER STAGE 3

REGISTER STAGE 4

REGISTER STAGE 5

REGISTER STAGE 6

REGISTER STAGE 7

REGISTER STAGE 8

LATCH 2

LATCH 3

LATCH 4

LATCH 5

LATCH 6

LATCH 7

LATCH 8

3–STATE BUFFER

3–STATE BUFFER

3–STATE BUFFER

3–STATE BUFFER

3–STATE BUFFER

3–STATE BUFFER

3–STATE BUFFER

CLOCK CLOCK STROBE STROBECLOCK

CLOCK CLOCK

CLOCK

CLOCK

CLOCK

STROBE

STROBE

CLOCK

STROBE

3

1 *Input Protection Diodes

*

*

*

MC14094B

10

DYNAMIC TIMING DIAGRAM

3

15

CLOCK

2 DATA IN

1 STROBE

OUTPUT

ENABLE

N Q1 Q7

9 QS

Q′S

tWH

50%

tsu

th

tWL

50%

tr

50% 50%

tPZHtPHZtPHLtPLHtPLH tPLZ

10%

90%90%90%

10%10%

50%

50%

50

50%

tPHLtPLHtTHLtTLH

tPLH



The MC14099B is an 8–bit addressable latch. Data is entered inserial form when the appropriate latch is addressed (via address pinsA0, A1, A2) and write disable is in the low state. For the MC14099B

the input is a unidirectional write only port.The data is presented in parallel at the output of the eight latchesindependently of the state of Write Disable, Write/Read or ChipEnable.

A Master Reset capability is available on both parts.

• Serial Data Input• Parallel Output• Master Reset•

Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–PowerSchottky TTL Load over the Rated Temperature Range

• MC14099B pin for pin compatible with CD4099B

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(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C




static voltages or electric fields. However, precautions must be taken to avoidapplications of any voltage higher than maximum rated voltages to this

high impedancecircuit For proper operation V and V shouldbeconstrained

Device Packag

ORDERING INF

MC14099BCP PDIP–1

MC14099BDW SOIC–1


MC14099BF SOEIAJ–

MC14099BFEL SOEIAJ

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work W

SOEIAJ–

F SUFFI

CASE 96

DW SUFF

CASE 751



MC14099B



VDD

Vdc Min Typ (8.)





tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40


Data to Output Q

tPHL,

tPLH 5.0

1015

—

— —

200

7550

Write Disable to Output Q 5.0

10

15

—

—

—

200

80

60

Reset to Output Q 5.0

10

15

—

—

—

175

80

65

CE to Output Q (MC14599B only) 5.0

1015

—

— —

225

10075

Propagation Delay Time, MC14599B only

Chip Enable, Write/Read to Data

tPHL,

tPLH 5.0

10

—

—

200

80



15 — 65

Address to Data 5.0

10

15

—

—

—

200

90

75

Pulse WidthsReset

tw(H)tw(L) 5.0

10

15

150

75

50

75

40

25

Write Disable 5.0

10

15

320

160

120

160

80

60

Set Up Time

Data to Write Disable

tsu

5.0

10

15

100

50

35

50

25

20

Hold Time

Write Disable to Data

th5.0

10

15

150

75

50

75

40

25

Set Up Time

Address to Write Disable

tsu 5.0

10

15

100

80

40

45

30

10

Removal Time

Write Disable to Address

trem 5.0

1015

0

00

– 80

– 40 – 40

MC14099B

RESET

DATA

WRITE

DISABLE

A0

A1

A2 7

6

5

4

3

2

ADDRESS

DECODER

TO

OTHER

LATCHES ZERO

SELECT

OTHER LATCHES

EACH LATCH

MC14099BFUNCTION DIAGRAM



A2

(M.S.B.)

7

TRUTH TABLE

Write

Disable Reset

Addressed

Latch

Unaddressed

Latches

0 0 Data Qn*

0 1 Data Reset

1 0 Qn* Qn*

1 1 Reset Reset

*Qn is previous state of latch.†Reset to zero state.

CAUTION: To avoid unintentional data changes in

Disable must be active (high) during

address inputs A0, A1, and A2.

MC14099B

SWITCHING WAVEFORMS

DATA OR

WRITE DISABLE

OUTPUT Q

RESET

OUTPUT Q

VDD

VSS

VDD

VSS

tPHL

50%

tTLH tTHL

90%

50%

10%

50%

tPLH tPHL

ADDRESS

WRITE

DISABLE

DATA 50%

50%

50%

tsu tw(L)

tsutw(H)



OUTPUT Q

The MC14106B hex Schmitt Trigger is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. These devices find primary use where low power

dissipation and/or high noise immunity is desired. The MC14106Bmay be used in place of the MC14069UB hex inverter for enhancednoise immunity or to “square up” slowly changing waveforms.

• Increased Hysteresis Voltage Over the MC14584B• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement for CD40106B and MM74C14•

Can Be Used to Replace the MC14584B or MC14069UB


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P SUFFIX

CASE 64

SOIC–14

D SUFFIX

CASE 751






(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C








Unused inputs must always be tied to an appropriate logic voltage level (e.g.,either VSS or VDD). Unused outputs must be left open.

A = Assemb

WL or L = Wafer L

YY or Y = Year

WW or W = Work W

Device Packag

ORDERING INF

MC14106BCP PDIP–

MC14106BD SOIC–

MC14106BDR2 SOIC–

MC14106BDT TSSOP–

TSSOP–1

DT SUFF

CASE 948

MC14106BDTR2 TSSOP–

MC14106B

LOGIC DIAGRAM

13 12

10

8

6

4

2

11

9

5

3

1

VDD = PIN 14

VSS = PIN 7

EQUIVALENT CIRCUIT SCHEMATIC




MC14106B



VDD

Vdc Min Typ (7.)


10

15

—

—

—

100

50

40


10

15

—

—

—

100

50

40


15

— —

—

12550

40


PULSE

GENERATOR INPUT

OUTPUT

VDD

VSS7 CL

14

20 ns

INPUT

OUTPUT

tPHL

90%50%

10%

90%50%

10%

tf tr




V o u t

, O U T P U T V O L T A G E ( V d c )

VDD

0VDD0


VT– VT+

VH


MC14106B

Figure 3.

(b) A Schmitt trigger offers max

noise immunity in gate applica

Vin Vout

VH

Vin

Vout

VDD

VSS

VDD

VSS

Vin

Vout

VH

(a) Schmitt Triggers will square up

inputs with slow rise and fall times.

APPLICATIONS

VDD VDD



Figure 4. Monostable Multivibrator

R

C

Vout

tw

Rs Rs

C

R

Useful as Pushbutton/Keyboard Debounce Circuit.

MC14106B

Figure 5. Astable Multivibrator

C

R

1f

t1

t2

* t1 RClnVT

VT –

* t2 RClnVDD – VT –

VDD – VT

1f

RClnVDD – VT –

VDD – VT

VT

VT –

*t1 + t2 tPHL + tPLH

Figure 6. Integrato

R AVin

C

VSS

VT+

VDD

Vin

VSS

VT+

VDD

A

VSS

VT+

VDD

Vout

Useful in discriminating against short puls

C

Vin

Vin



Figure 7. Differentiator Figure 8. Positive Edge Time D

R

– EDGE + EDGE

VDD

+EDGE

– EDGE

tw

tw = RC lnVDD

VT+

Useful as an edge detector circuit.

C C

R R

Vin

The MC14174B hex type D flip–flop is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Data on the D inputs which meets the setup timerequirements is transferred to the Q outputs on the positive edge of theclock pulse. All six flip–flops share common clock and reset inputs.The reset is active low, and independent of the clock.

• Static Operation• All Inputs and Outputs Buffered• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load over the Rated Temperature Range• Functional Equivalent to TTL 74174


http://onsem

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751



( g SS) ( )



Vin, Vout Input or Output Voltage Range(DC or Transient) –0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature(8–Second Soldering) 260°C







to the range VSS (Vin or Vout) VDD.Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14174BCP PDIP–

MC14174BD SOIC–

MC14174BDR2 SOIC–

1. For ordering information

SOEIAJ–

F SUFFI

CASE 96

MC14174BF SOEIAJ–


MC14174B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q4

D4

D5

VDD

C

Q3

D3

D1

D0

Q0

R

VSS

Q2

D2

Q1

Q5

BLOCK DIAGRAM

9

1

3

4

6

2

7

CLOCK

RESET

D0

D1

D2

Q2

5Q1

Q0



6

11

13

14

10

15

D2

D3

D4

D5

VDD = PIN 16

VSS = PIN 8

Q3

Q4 12

Q5

TRUTH TABLE

(Positive Logic)

Inputs Output

Clock Data Reset Q

0 1 0

1 1 1

X 1 Q

X X 0 0

X = Don’t Care

No

Change

MC14174B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1


(VOH = 2.5 Vdc) Source(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.05.0

10

15

– 3.0 – 0.64

– 1.6

– 4.2

— —

—

—

– 2.4 – 0.51

– 1.3

– 3.4

– 4.2 – 0.88

– 2.25

– 8.8

— —

—

—

– – 0

– 0

– 2


(VOL = 0.5 Vdc)

IOL 5.0

10

0.64

1.6

—

—

0.51

1.3

0.88

2.25

—

—

0.

0



(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14174B


VDDAll Types


Min Typ (8.)





tTLH, tTHL

5.0

10

15

—

—

—

100

50

40

Propagation Delay Time — Clock to Q


tPLH

, tPHL

= (0.36 ns/pF) CL

+ 64 ns


tPLH, tPHL

5.0

10

15

—

—

—

210

85

65

Propagation Delay Time — Reset to Q




tPHL

5.0

10

15

—

—

—

250

100

75


10

15

150

90

70

75

45

35

Reset Pulse Width

tWL 5.0

1015

200

10080

100

5040


10

15

—

—

—

7.0

12

15.5


10

—

—

—

—



10

15

—

—

Data Setup Time tsu 5.0

10

15

40

20

15

20

10

0

Data Hold Time th 5.0

10

15

80

40

30

40

20

15


10

15

250

100

80

125

50

40


MC14174B

FUNCTIONAL BLOCK DIAGRAM

TIMING DIAGRAM



MC14175B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D2

D3

Q3

VDD

C

Q2

Q2

D0

Q0

Q0

R

VSS

Q1

Q1

D1

Q3

BLOCK DIAGRAM

9

1

4

5

2

7

10

CLOCK

RESET

D0

D1

3

Q1

Q0

6

Q0

Q1

Q2



5

12

13

15

D1

D2

D3

VDD = PIN 16

VSS = PIN 8

Q3

Q2 11

Q3 14

TRUTH TABLE

Inputs OutputsClock Data Reset Q Q

0 1 0 1

1 1 1 0

X 1 Q Q

X X 0 0 1

X = Don’t Care

No

Change

MC14175B


VDD – 55 C 25 C




Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1


(VOH = 2.5 Vdc) Source(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.05.0

10

15

– 3.0 – 0.64

– 1.6

– 4.2

— —

—

—

– 2.4 – 0.51

– 1.3

– 3.4

– 4.2 – 0.88

– 2.25

– 8.8

— —

—

—

– – 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2



( OL )


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk




MC14175B

FUNCTIONAL BLOCK DIAGRAM

TIMING DIAGRAM



The MC14490 is constructed with complementary MOSenhancement mode devices, and is used for the elimination of

extraneous level changes that result when interfacing with mechanicalcontacts. The digital contact bounce eliminator circuit takes an inputsignal from a bouncing contact and generates a clean digital signalfour clock periods after the input has stabilized. The bounce eliminatorcircuit will remove bounce on both the “make” and the “break” of acontact closure. The clock for operation of the MC14490 is derivedfrom an internal R–C oscillator which requires only an externalcapacitor to adjust for the desired operating frequency (bounce delay).The clock may also be driven from an external clock source or the

oscillator of another MC14490 (see Figure 5).NOTE: Immediately after power–up, the outputs of the MC14490are in indeterminate states.

• Diode Protection on All Inputs• Six Debouncers Per Package• Internal Pullups on All Data Inputs

http://onsem

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751



• Can Be Used as a Digital Integrator, System Synchronizer, or DelayLine

• Internal Oscillator (R–C), or External Clock Source• TTL Compatible Data Inputs/Outputs• Single Line Input, Debounces Both “Make” and “Break” Contacts• Does Not Require “Form C” (Single Pole Double Throw) Input

Signal• Cascadable for Longer Time Delays• Schmitt Trigger on Clock Input (Pin 7)• Supply Voltage Range = 3.0 V to 18 V

• Chip Complexity: 546 FETs or 136.5 Equivalent Gates





(DC or Transient)

–0.5 to VDD + 0.5 V

Iin Input Current


± 10 mA

PD Power Dissipation 500 mW

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14490DW SOIC–

MC14490DWR2 SOIC–

MC14490F SOEIAJ–

1. For ordering information the SOIC packages, plea

MC14490FEL SOEIAJ–

MC14490P PDIP–

SOEIAJ–

F SUFFICASE 96

MC14490

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Din

Cout

Bin

VDD

OSCout

Fin

Eout

Dout

Cin

Bout

Ain

VSS

OSCin

Fout

Ein

Aout

BLOCK DIAGRAM

Ain 1

OSCin 7

+VDD

φ1OSCILLATOR

AND

TWO PHASE

DATA

SHIFT LOAD

4–BIT STATIC SHIFT REGISTER1/2–BIT

DELAY

φ1 φ2φ1 φ2



OSCout 9

Bin 14

Cin 3

Din 12

Ein 5

Fin 10

φ2

TWO–PHASE

CLOCK GENERATORφ1 φ2

φ1 φ2

φ1 φ2

φ1 φ2

φ1 φ2

2 B

13 C

4 D

11 E

6 F

IDENTICAL TO ABOVE STAGE





MC14490


VDD – 55 C 25 C


Min Max Min Typ (4.) Max M


VOL 5.01015

— — —

0.050.050.05

— — —

000

0.050.050.05

— — —


VOH 5.01015

4.959.9514.95

— — —

4.959.9514.95

5.01015

— — —

4.9.14

Input Voltage “0” Level(VO = 4.5 or 0.5 Vdc)(VO = 9.0 or 1.0 Vdc)(VO = 13.5 or 1.5 Vdc)

VIL5.01015

— — —

1.53.04.0

— — —

2.254.506.75

1.53.04.0

— — —

(VO = 0.5 or 4.5 Vdc) “1 Level”(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH 5.01015

3.57.011

— — —

3.57.011

2.755.508.25

— — —

371

Output Drive CurrentOscillator Output Source

(VOH = 2.5 V)

(VOH = 4.6 V)(VOH = 9.5 V)(VOH = 13.5 V)

IOH

5.0

5.01015

– 0.6

– 0.12 – 0.23 – 1.4

—

— — —

– 0.5

– 0.1 – 0.2 – 1.2

– 1.5

– 0.3 – 0.8 – 3.0

—

— — —

– 0

– 0 – 0 –

Debounce Outputs(VOH = 2.5 V)(VOH = 4.6 V)(VOH = 9.5 V)(VOH = 13.5 V)

5.05.01015

– 0.9 – 0.19 – 0.6

1.8

— — — —

– 0.75 – 0.16 – 0.5 – 1.5

– 2.2 – 0.46 – 1.2 – 4.5

— — — —

– 0 – 0 – 0 –



Oscillator Output Sink(VOL = 0.4 V)

(VOL = 0.5 V)(VOL = 1.5 V)

IOL

5.01015

0.360.94.2

— — —

0.30.753.5

0.92.310

— — —

0.02

Debounce Outputs(VOL = 0.4 V)(VOL = 0.5 V)(VOL = 1.5 V)

5.01015

2.64.012

— — —

2.23.310

4.09.035

— — —

128

Input CurrentDebounce Inputs (Vin = VDD)

IIH 15 — 2.0 — 0.2 2.0 —

Input Current Oscillator — Pin 7(Vin = VSS or VDD)

Iin 15 — ± 620 — ± 255 ± 400 —

Pullup Resistor Source CurrentDebounce Inputs(Vin = VSS)

IIL 5.01015

175340505

3757401100

140280415

190380570

255500750

7142


Quiescent Current(Vin = VSS or VDD, Iout = 0 µA)

ISS 5.01015

— — —

150280840

— — —

4090

225

100225650

— — —


MC14490

SWITCHING CHARACTERISTICS(5.)

(CL = 50 pF, TA = 25 C)


VDD

Vdc Min Typ (6.)

Output Rise Time

All Outputs

tTLH 5.0

10

15

—

—

—

180

90

65

Output Fall Time Oscil lator Output

tTHL

5.0

10

15

—

—

—

100

50

40

Debounce Outputs tTHL 5.0

1015

—

— —

60

3020


Oscillator Input to Debounce Outputs

tPHL 5.0

10

15

—

—

—

285

120

95

tPLH 5.0

10

15

—

—

—

370

160

120

Clock Frequency (50% Duly Cycle)

(External Clock)

fcl 5.0

10

15

—

—

—

2.8

6

9

Setup Time (See Figure 1) tsu 5.0

10

15

100

80

60

50

40

30

Maximum External Clock Input

Rise and Fall Time

Oscillator Input

tr, tf 5.0

10

15

No Limit

O ill t F f t



Oscillator Frequency

OSCout

Cext ≥ 100 pF*

Note: These equations are intended to be a design guide.

Laboratory experimentation may be required. Formulas

are typically ± 15% of actual frequencies.

fosc, typ

5.0

10

15


*POWER–DOWN CONSIDERATIONS

Large values of Cext may cause problems when powering down the MC14490 because of the amount capacitor. When a system containing this device is powered down, the capacitor may discharge throug

diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited toturn–off time of the power supply must not be faster than t = (VDD – VSS) Cext / (10 mA). For exampV and Cext = 1µF, the power supply must turn off no faster than t = (15 V) (1µF)/10 mA = 1.5 ms. This isbecause power supplies are heavily filtered and cannot discharge at this rate.

When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain dpossibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.

OSCin

Aout

VDD

0 V50%

90%

50% 10%t

D1 DCext

tPLH

VDD

MC14490

THEORY OF OPERATIONThe MC14490 Hex Contact Bounce Eliminator is

basically a digital integrator. The circuit can integrate bothup and down. This enables the circuit to eliminate bounce onboth the leading and trailing edges of the signal, shown in thetiming diagram of Figure 3.

Each of the six Bounce Eliminators is composed of a4–1/2–bit register (the integrator) and logic to compare theinput with the contents of the shift register, as shown inFigure 4. The shift register requires a series of timing pulsesin order to shift the input signal into each shift registerlocation. These timing pulses (the clock signal) arerepresented in the upper waveform of Figure 3. Each of thesix Bounce Eliminator circuits has an internal resistor asshown in Figure 4. A pullup resistor was incorporated ratherthan a pulldown resistor in order to implement switchedground input signals, such as those coming from relaycontacts and push buttons. By switching ground, rather thana power supply lead, system faults (such as shorts to groundon the signal input leads) will not cause excessive currentsin the wiring and contacts. Signal lead shorts to ground aremuch more probable than shorts to a power supply lead.

When the relay contact is closed, (see Figure 4) the lowlevel is inverted, and the shift register is loaded with a highon each positive edge of the clock signal. To understand the

After some time period of N clock opened and at N+1 a low is loaded intN+1, when the input bounces low, alAt N+2 nothing happens because thelow and all bits of the shift register aand thereafter the input signal is a higpositive edge of N+ 6 the output goes lows being shifted into the shift regis

Assuming the input signal is long through the Bounce Eliminator, the olonger or shorter than the clean inpuone clock period.

The amount of time distortion beoutput signals is a function of the characteristics on the edges of the inpfrequency. Since most relay contacwhen making as compared to breakicounting bounce period, will be greatof the input signal than on the trailing signal will be shorter than the input sedge bounce is included in the overal

The only requirement on the clockobtain a bounce free output signal is tdo not occur while the input signa



p g goperation, we assume all bits of the shift register are loadedwith lows and the output is at a high level.

At clock edge 1 (Figure 3) the input has gone low and ahigh has been loaded into the first bit or storage location of the shift register. Just after the positive edge of clock 1, theinput signal has bounced back to a high. This causes the shiftregister to be reset to lows in all four bits — thus starting thetiming sequence over again.

During clock edges 3 to 6 the input signal has stayed low.Thus, a high has been shifted into all four shift register bitsand, as shown, the output goes low during the positive edgeof clock pulse 6.

It should be noted that there is a 3–1/2 to 4–1/2 clockperiod delay between the clean input signal and outputsignal. In this example there is a delay of 3.8 clock periodsfrom the beginning of the clean input signal.

p gReferring to Figure 3, a false state is seat the beginning of the input signal. low three times before it finally settlestate. The first three low pulses are ref

If the user has an available clockfrequency, it may be used by connecinput (pin 7). However, if an externalthe user can place a small capacitorinput and output pins in order to starsource (as shown in Figure 4). Thoscillator output pin may then be MC14490 Bounce Eliminator packagMC14490, a large number of signals cthe requirement of only one small caHex Bounce Eliminator packages.

OSCin OR OSCout

NN + 5N + 3N + 1654321

MC14490

Figure 4. Typical “Form A” Contact Debounce Circuit

(Only One Debouncer Shown)

1/2 BIT

DELAY

OSCILLATOR

AND

TWO–PHASE

CLOCK GENERATOR

Cext

OSCout

OSCin

“FORM A”

CONTACT

Ain1

9

7φ1

φ2

DATA

SHIFT LOAD

4–BIT STATIC SHIFT REGISTER

φ1 φ2

φ1 φ2

+VDD PULLUP RESISTOR

(INTERNAL)

OPERATING CHARACTERISTICS

The single most important characteristic of the MC14490is that it works with a single signal lead as an input, makingit directly compatible with mechanical contacts (Form A

and B).The circuit has a built–in pullup resistor on each input.

The worst case value of the pullup resistor (determined fromthe Electrical Characteristics table) is used to calculate thecontact wetting current. If more contact current is required,an external resistor may be connected between VDD and theinput.

paralleled standard gates or by the Mbuffers.

The clock input circuit (pin 7) has S

such that proper clocking will occurclock edges, eliminating any need foaddition, other MC14490 oscillator from a single oscillator output buffereFigure 5). Up to six MC14490s maybuffer.

The MC14490 is TTL compatible



Because of the built–in pullup resistors, the inputs cannotbe driven with a single standard CMOS gate when VDD is

below 5 V. At this voltage, the input should be driven with

the outputs. When VDD is at 4.5 V, thsink 1.6 mA at 0.4 V. The inputs can

a result of the internal input pullup re

FROM CONTACTS MC14490TO SYSTEM

LOGIC

OSCin OSCout

Cext1/6 MC14050

97

OSCin 7 9 OSCout

NO CONNECTIO

FROM

CONTACTS

TO SYSTEM

LOGICMC14490

NO CONNECTIO9 OSCoutOSCin 7

FROM CONTACTS MC14490TO SYSTEM

LOGIC

MC14490


ASYMMETRICAL TIMING

In applications where different leading and trailing edgedelays are required (such as a fast attack/slow release timer.)Clocks of different frequencies can be gated into theMC14490 as shown in Figure 6. In order to produce a slowattack/fast release circuit leads A and B should beinterchanged. The clock out lead can then be used to feedclock signals to the other MC14490 packages where the

asymmetrical input/output timing is required.

IN OUT

OSCout

MC14011B

OSCin

A B

fC/NEXTERNAL

CLOCK÷ N

fC

MC14490

MULTIPLE TIMING SIGNALS

As shown in Figure 8, the Bounce Ebe connected in series. In this configdelayed by four clock periods relativeThis configuration may be used to gesignals such as a delay line, for progroperations.

One application of the above is sho

it is required to have a single pulsoperation (make) of the push button only requires the series connectiEliminator circuits, one inverter, and to generate the signal AB as shown insignal AB is four clock periods in leswitched to the A output, the pulse Aupon release or break of the contact. additional parts many different pulses

be generated.

14

1

B.E. 2

B.E. 1Ain



Figure 6. Fast Attack/Slow Release Circuit

LATCHED OUTPUT

The contents of the Bounce Eliminator can be latched byusing several extra gates as shown in Figure 7. If the latchlead is high the clock will be stopped when the output goeslow. This will hold the output low even though the input hasreturned to the high state. Any time the clock is stopped theoutputs will be representative of the input signal four clock

periods earlier.

IN OUT

OSCout

MC14011B

OSCin

MC14490

CLOCK

10

5

12

3

7OSCin CLOCK

B.E. 6

B.E. 5

B.E. 4

B.E. 3

Bin

Cin

Din

Ein

Fin

MC14490

Figure 9. Single Pulse Output Circuit

IN

IN

A

OUT

OUT

B

A

BAB

A ≡ ACTIVE LOW

B ≡ ACTIVE LOW

BE 2

BE 1

OSCin OR

OSCout

INPUT

A

B



Figure 10. Multiple Output Signal Timing Diagram

C

D

E

F

AB

AB



MC14503B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

IN 5

OUT 6

IN 6

VDD

OUT 4

IN 4

OUT 5

IN 2

OUT 1

IN 1

DIS A

VSS

OUT 3

IN 3

OUT 2

DIS B

LOGIC DIAGRAMTRUTH TABLE

Appropriate

DisableInn Input Outn

0 0 0

1 0 1

X 1 High

Impedance

X = Don’t Care

DISABLE B

15

12

14

2

4

6

IN 5

IN 6

IN 1

IN 2

IN



6

10

1

IN 3

IN 4

DISABLE A

VDD = PIN 16

VSS = PIN 8

CIRCUIT DIAGRAM

* INn

*DISABLE

* INPUT VSS

VDD

OUTn

ONE OF TWO/FOUR BUFFERS



MC14503B


VDDAll Type


VCC Typ (8.)

Output Rise Time


tTLH = (0.3 ns/pF) CL + 8.0 ns

tTLH = (0.2 ns/pF) CL + 8.0 ns

tTLH

5.0

10

15

45

23

18

Output Fall Time


tTHL = (0.3 ns/pF) CL + 8.0 nstTHL = (0.2 ns/pF) CL + 8.0 ns

tTHL

5.0

1015

45

2318

Turn–Off Delay Time, all Outputs




tPLH

5.0

10

15

75

35

25

Turn–On Delay Time, all Outputs




tPHL

5.0

10

15

75

35

25

3–State Propagation Delay Time

Output “1” to High Impedance

tPHZ 5.0

10

15

75

40

35

Output “0” to High Impedance tPLZ 5.0

10

15

80

40

35

High Impedance to “1” Level tPZH 5.0

10

65

25



0

15

5

20

High Impedance to “0” Level tPZL 5.0

10

15

100

35

25


Figure 1. Switching Time Test Circuit and Waveforms(tTLH, tTHL, tPHL, and tPLH)

PULSE

GENERATOR

DISABLE

INPUT

INPUT

VDD

16

VSS CL

OUTPUT

20 ns

tTLH

tPLH

90%5OUTPUT

INPUT

tPLH

90%50%

MC14503B

Figure 2. 3–State AC Test Circuit and Waveforms

(tPLZ, tPHZ, tPZH, tPZL)

PULSEGENERATOR

DISABLE INPUT

16

VSS

OUTPUT

20 ns 20 nsVDD

50%90%

VDD

1 k

8

INPUT

tPHZ, tPZH CIRCUIT

PULSEGENERATOR

DISABLE INPUT

VSS8

16

INPUT

CL

VDD

VSS

VOH

VOL

≈ VOL + 0.05 V

≈ VOH – 0.15 V

10%

90%

10%

90%

10%

tPLZ

tPHZ tPZH

tPZL

OUTPUT FOR tPZH, tPZL CIRCUIT

OUTPUT FOR tPHZ, tPLZ CIRCUIT

DISABLE INPUT



MC14504B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Eout

MODE

Fin

Fout

VDD

Din

Dout

Ein

Bout

Ain

Aout

VCC

VSS

Cin

Cout

Bin

LOGIC DIAGRAM

INPUT

VDD

OUTPUTLEVEL

SHIFTER

MODE

VCC

TTL/CMOS



MODEMODE SELECT

Mode Select

Input Logic

Levels

Output Logic

Levels

1 (VCC) TTL CMOS

0 (VSS) CMOS CMOS

1/6 of package shown.

MC14504B


V V – 55 C 25 C

Characteristic Symbol Vdc Vdc Min Max Min Typ (4.) Max

Output Voltage “0” LevelVin = 0 V

“ ”

VOL — — —

5.0101 5

— — —

0.050.050.05

— — —

000

0.050.050.05

eveVin = VCC

VOH — — —

5.01015

4.959.9514.95

— — —

4.959.9514.95

5.01015

— — —

Input Voltage “0” Level(VOL = 1.0 Vdc) TTL–CMOS(VOL = 1.5 Vdc) TTL–CMOS(VOL = 1.0 Vdc) CMOS–CMOS(VOL = 1.5 Vdc) CMOS–CMOS(VOL = 1.5 Vdc) CMOS–CMOS

VIL5.05.05.05.010

1015101515

— — — — —

0.80.81.51.53.0

— — — — —

1.31.3

2.252.254.5

0.80.81.51.53.0

Input Voltage “1” Level(VOH = 9.0 Vdc) TTL–CMOS(VOH = 13.5 Vdc) TTL–CMOS(VOH = 9.0 Vdc) CMOS–CMOS(VOH = 13.5 Vdc) CMOS–CMOS

(VOH = 13.5 Vdc) CMOS–CMOS

VIH5.05.05.05.0

10

10151015

15

2.02.03.63.6

7.1

— — — —

—

2.02.03.53.5

7.0

1.51.5

2.752.75

5.5

— — — —

—

Output Drive Current(VOH = 2.5 Vdc) Source(VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)

IOH — — — —

5.05.01015

– 3.0 –0.64 – 1.6 – 4.2

— — — —

– 2.4 –0.51 – 1.3 – 3.4

– 4.2 – 0.88 – 2.25 – 8.8

— — — —


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL — ——

5.01015

0.641.64.2

— ——

0.511.33.4

0.882.258.8

— ——



( OL ) 15 4.2 3.4 8.8

Input Current Iin — 15 — ± 0.1 — ±0.00001 ± 0.1

Input Capacitance (Vin = 0) Cin — — — — — 5.0 7.5

Quiescent Current(Per Package)CMOS–CMOS Mode

IDD orICC

— — —

5.01015

— — —

0.050.100.20

— — —

0.00050.00100.0015

0.050.100.20

Quiescent Current(Per Package)TTL–CMOS Mode

IDD 5.05.05.0

5.01015

— — —

0.51.02.0

— — —

0.00050.00100.0015

0.51.02.0

Quiescent Current

(Per Package)TTL–CMOS Mode

ICC 5.0

5.05.0

5.0

1015

—

— —

5.0

5.05.0

—

— —

2.5

2.52.5

5.0

5.05.0


MC14504B


VCC VDDLimit

Characteristic Symbol Shifting Mode Vdc

Vdc Min Typ (5

Propagation Delay, High to Low tPHL TTL – CMOS

VDD > VCC

5.0

5.0

10

15

—

—

140

140

CMOS – CMOS

VDD > VCC

5.0

5.0

10

10

15

15

—

—

—

120

120

70

CMOS – CMOS

VCC > VDD

10

15

15

5.0

5.0

10

—

—

—

185

185

175Propagation Delay, Low to High tPLH TTL – CMOS

VDD > VCC

5.0

5.0

10

15

—

—

170

160

CMOS – CMOS

VDD > VCC

5.0

5.0

10

10

15

15

—

—

—

170

170

100

CMOS – CMOS

VCC > VDD

10

15

15

5.0

5.0

10

—

—

—

275

275

145

Output Rise and Fall Time tTLH, tTHL ALL —

— —

5.0

1015

—

— —

100

5040




MC14504B

Figure 1. Input Switchpoint CMOS to CMOS Mode Figure 2. Input Switchpoint TT

20151050

VDD, SUPPLY VOLTAGE (Vdc)

7

6

5

4

3

2

1

0

V S p ,

I N P

U T S W I T C H P O I N T V O L T A G E ( V d c )

1050

VDD, SUPPLY VOLTA

7

6

5

4

3

2

1

0

V S p ,

I N P

U T S W I T C H P O I N T V O L T A G E ( V d c )

VCC = 10 V

VCC = 5 V

VCC

=

, S U P P L Y V O L T A G E ( V d c )

20

15

10

, S U P P L Y V O L T A G E ( V d c )

20

15

10



Figure 3. Operating Boundary CMOS to CMOS Mode Figure 4. Operating Boundary T

V D D

5

0

1050

VCC, SUPPLY VOLTA

V D D

5

0

20151050

VCC, SUPPLY VOLTAGE (Vdc)



MC14511B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.1

9.1

14.1

—

—

—

4.1

9.1

14.1

4.57

9.58

14.59

—

—

—

4

9

14

Input Voltage # “0” Level(VO = 3.8 or 0.5 Vdc)

(VO = 8.8 or 1.0 Vdc)

(VO = 13.8 or 1.5 Vdc)

VIL5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 3.8 Vdc)

(VO = 1.0 or 8.8 Vdc)

(VO = 1.5 or 13.8 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1

Output Drive Voltage

(IOH = 0 mA) Source

(IOH = 5.0 mA)(IOH = 10 mA)

(IOH = 15 mA)

(IOH = 20 mA)

(IOH = 25 mA)

VOH

5.0 4.1

—3.9

—

3.4

—

—

— —

—

—

—

4.1

—3.9

—

3.4

—

4.57

4.244.12

3.94

3.70

3.54

—

— —

—

—

—

4

—3

—

3

—

(IOH = 0 mA)

(IOH = 5.0 mA)

(IOH = 10 mA)

(IOH = 15 mA)

(IOH = 20 mA)

10 9.1

—

9.0

—

8.6

—

—

—

—

—

9.1

—

9.0

—

8.6

9.58

9.26

9.17

9.04

8.90

—

—

—

—

—

9

—

8

—

8



( OH )

(IOH = 25 mA) — — — 8.70 — —

(IOH = 0 mA)

(IOH = 5.0 mA)

(IOH = 10 mA)

(IOH = 15 mA)

(IOH = 20 mA)

(IOH = 25 mA)

15 14.1

—

14

—

13.6

—

—

—

—

—

—

—

14.1

—

14

—

13.6

—

14.59

14.27

14.18

14.07

13.95

13.70

—

—

—

—

—

—

14

—

13

—

13

—


(VOL = 0.4 V) Sink

(VOL = 0.5 V)

(VOL = 1.5 V)

IOL

5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2



Quiescent Current

(Per Package) Vin = 0 or VDD,

Iout = 0 µA

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


IT 5.0

10

15




MC14511B



VDD

Vdc Min Typ

Output Rise Time


tTLH = (0.25 ns/pF) CL + 17.5 ns


tTLH

5.0

10

15

—

—

—

40

30

25

Output Fall Time


tTHL = (0.75 ns/pF) CL + 37.5 ns

tTHL = (0.55 ns/pF) CL + 37.5 ns

tTHL

5.0

10

15

—

—

—

125

75

65

Data Propagation Delay Time

tPLH = (0.40 ns/pF) CL + 620 ns

tPLH = (0.25 ns/pF) CL + 237.5 ns

tPLH = (0.20 ns/pF) CL + 165 ns

tPLH

5.0

10

15

—

—

—

640

250

175


tPHL = (0.60 ns/pF) CL + 260 ns

tPHL = (0.35 ns/pF) CL + 182.5 ns

tPHL 5.0

10

15

—

—

—

720

290

200

Blank Propagation Delay Time

tPLH = (0.30 ns/pF) CL + 585 nstPLH = (0.25 ns/pF) CL + 187.5 ns

tPLH = (0.15 ns/pF) CL + 142.5 ns

tPLH

5.0I0

15

— —

—

600200

150

tPHL = (0.85 ns/pF) CL + 442.5 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns

tPHL = (0.35 ns/pF) CL + 142.5 ns

tPHL 5.0

10

15

—

—

—

485

200

160

Lamp Test Propagation Delay Time

tPLH = (0.45 ns/pF) CL + 290.5 ns

tPLH = (0.25 ns/pF) CL + 112.5 ns

tPLH

5.0

10

15

—

—

313

125

90



tPLH = (0.20 ns/pF) CL + 80 ns15 — 90


tPHL = (0.45 ns/pF) CL + 102.5 ns

tPHL = (0.35 ns/pF) CL + 72.5 ns

tPHL 5.0

10

15

—

—

—

313

125

90

Setup Time tsu 5.0

10

15

100

40

30

—

—

—

Hold Time th 5.0

10

15

60

40

30

—

—

—Latch Enable Pulse Width tWL 5.0

10

15

520

220

130

260

110

65

8. The formulas given are for the typical characteristics only.

MC14511B

Figure 1. Dynamic Power Dissipation Signal Waveforms

Input LE low, and Inputs D, BI and LT high.

f in respect to a system clock.All outputs connected to respective CL loads.

20 ns 20 nsVDD

VSS

VOH

VOL

90%50%

10%

50%

A, B, AND C

ANY OUTPUT

50% DUTY CYCLE

12f

20 ns 20 nsVDD90%

INPUT C

(a) Inputs D and LE low, and Inputs A, B, BI and LT high.

VSS

VOH

VOL

50%10%

OUTPUT g

tPLH tPHL

90%

10%50%

tTLH tTHL



(b) Input D low, Inputs A, B, BI and LT high.

20 ns

10%

90%

50%

VDD

VSS

VDD

VSS

VOH

VOL

thtsu

50%INPUT C

OUTPUT g

LE

20 ns 20 nsV

MC14511B

CONNECTIONS TO VARIOUS DISPLAY READOUTS

COMMON

CATHODE LED

≈ 1.7 V

VDD

VSS

VDD

COMMON

ANODE LED

VSS

LIGHT EMITTING DIODE (LED) READOUT

INCANDESCENT READOUT FLUORESCENT READ

VDD VDD

**

VDD

DIRECT

(LOW BRI



GAS DISCHARGE READOUT LIQUID CRYSTAL (LCD) R

VSSVSS

(CAUTION: Maximum working voltag

VDD

APPROPRIATE

VOLTAGE VDD

MC14511B

LOGIC DIAGRAM

LE 5

D 6

C 2

B 1

A 7

VDD = PIN 16

VSS = PIN 8

BI 4

LT 3



The MC14512B is an 8–channel data selector constructed withMOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. This data selector finds primaryapplication in signal multiplexing functions. It may also be used for

data routing, digital signal switching, signal gating, and numbersequence generation.

• Diode Protection on All Inputs• Single Supply Operation• 3–State Output (Logic “1”, Logic “0”, High Impedance)• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power






(DC or Transient)

–0.5 to VDD + 0.5 V

http://onsem

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751



Iin, Iout Input or Output Current(DC or Transient) per Pin ± 10 mA



500 mW



TL Lead Temperature


260 °C










A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14512BCP PDIP–

MC14512BD SOIC–

MC14512BDR2 SOIC–

SOEIAJ–F SUFFI

CASE 96

MC14512BF SOEIAJ

MC14512B

TRUTH TABLE

C B A Inhibit Disable Z

0 0 0 0 0 X0

0 0 1 0 0 X1

0 1 0 0 0 X2

0 1 1 0 0 X3

1 0 0 0 0 X4

1 0 1 0 0 X5

1 1 0 0 0 X6

1 1 1 0 0 X7

X X X 1 0 0

X X X X 1 High

Impedance

X = Don’t Care

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

B

C

Z

DIS

VDD

X7

INH

A

X3

X2

X1

X0

VSS

X6

X5

X4



MC14512B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.9

9.9

14

Input Voltage “0” Level(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —



Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15






IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14512B

SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25 C, See Figure 1)

All Type

Characteristic Symbol VDD Typ (8.)





tTLH,

tTHL 5.0

10

15

100

50

40

Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z

tPLH

5.0

10

15

330

125

85

Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z

tPHL

5.0

10

15

330

125

85

3–State Output Delay Times (Figure 3)

“1” or “0” to High Z, and

High Z to “1” or “0”

tPHZ, tPLZ,

tPZH, tPZL

5.0

10

15

60

35

30


VDD

ID

CL

Z

DISABLE

INHIBITABC

X0X1X2

X3

PULSE

GENERATOR50%Vin

50%




X3X4X5X6X7

VSS

50%DUTY

CYCLE



MC14512B

LOGIC DIAGRAM

1312

11

1

2

3

4

5

6

7

9X7

X6

X5

X4

X3

X2

X1

X0

B

C

A

15

10

14

DISABLE

INHIBITVDD

Z

VSS

1 1

INOUT

IN

2

OUT

2TRANSMISSION

GATE

SELECTED

DEVICE

MC14512B

MC14512B

MC14512B

IOD

ITL

ITL

3–STATE MODE OF OPERATION



3 STATE MODE OF OPERATION

Output terminals of several MC14512B 8–Bit DataSelectors can be connected to a single date bus as shown.One MC14512B is selected by the 3–state control, and theremaining devices are disabled into a high–impedance “off”state. The number of 8–bit data selectors, N, that may beconnected to a bus line is determined from the output drivecurrent, IOD, 3–state or disable output leakage current, ITL,

and the load current, IL, required to drive the bus line

(including fanout to other device calculated by:

ITLN = +

IOD – IL

N must be calculated for both high andbus line.

CMOS MSI(Low–Power Complementary MOS)

The MC14513B BCD–to–seven segment latch/decoder/driver isconstructed with complementary MOS (CMOS) enhancement modedevices and NPN bipolar output drivers in a single monolithic structure.The circuit provides the functions of a 4–bit storage latch, an 8421BCD–to–seven segment decoder, and has output drive capability. Lamptest (LT), blanking (BI), and latch enable (LE) inputs are used to test thedisplay, to turn–off or pulse modulate the brightness of the display, andto store a BCD code, respectively. The Ripple Blanking Input (RBI) and

Ripple Blanking Output (RBO) can be used to suppress either leadingor trailing zeroes. It can be used with seven–segment light emittingdiodes (LED), incandescent, fluorescent, gas discharge, or liquid crystalreadouts either directly or indirectly.

Applications include instrument (e.g., counter, DVM, etc.) displaydriver, computer/calculator display driver, cockpit display driver, andvarious clock, watch, and timer uses.

• Low Logic Circuit Power Dissipation• High–current Sourcing Outputs (Up to 25 mA)

• Latch Storage of Binary Input

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A = Assem

WL or L = WaferYY Y Y

1

18

PDIP–18

P SUFFIX

CASE 707



• Latch Storage of Binary Input• Blanking Input• Lamp Test Provision• Readout Blanking on all Illegal Input Combinations• Lamp Intensity Modulation Capability• Time Share (Multiplexing) Capability• Adds Ripple Blanking In, Ripple Blanking Out to MC14511B

• Supply Voltage Range = 3.0 V to 18 V• Capable of Driving Two Low–Power TTL Loads, One Low–power

Schottky TTL Load to Two HTL Loads Over the Rated TemperatureRange.

MAXIMUM RATINGS (Voltages Referenced to VSS) (1.)



Vin Input Voltage Range, All Inputs –0.5 to VDD + 0.5 V

I DC C t D i I t Pi 10 A

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14513BCP PDIP–

This device contains prote

the inputs against damage du

or electric fields. However, it

precautions be taken to avoid

age higher than maximum rat

impedance circuit. A destruc

may occur if Vin and Vout are

range VSS (Vin or Vout)

Due to the sourcing capab

age can occur to the device if

outputs are shorted to VSS an

MC14513B

PIN ASSIGNMENT

LE

LT

C

B

VSS

RBI

A

D

BI a

g

f

VDD

RBO

ed

c

b14

15

16

17

18

10

1112

13

5

4

3

2

1

9

87

6

0 1 2 3 4 5 6 7 8 9

DISPLAY

a

b

c

d

e

f g

Inputs Outputs

RBI LE BI LT D C B A RBO a b c d e f g Display

X X X 0 X X X X + 1 1 1 1 1 1 1 8

X X 0 1 X X X X + 0 0 0 0 0 0 0 Blank

1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 Blank0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0

X 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 1X 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 2

TRUTH TABLE



X 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 2X 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1 3X 0 1 1 0 1 0 0 0 0 1 1 0 0 1 1 4X 0 1 1 0 1 0 1 0 1 0 1 1 0 1 1 5

X 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 6X 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 7X 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 8X 0 1 1 1 0 0 1 0 1 1 1 1 0 1 1 9X 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 Blank

X 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0 Blank

X 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 BlankX 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 BlankX 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 BlankX 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank

X 1 1 1 X X X X † * *

X = Don’t Care

†RBO = RBI (D C B A), indicated by other rows of table

*Depends upon the BCD code previously applied when LE = 0

MC14513B


VDD – 55 C 25 C


Output Voltage — Segment Outputs

“0” Level

Vin = VDD or 0

VOL

5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.1

9.1

14.1

—

—

—

4.1

9.1

14.1

5.0

10

15

—

—

—

4

9

1

Output Voltage — RBO Output

“0” Level

Vin = VDD or 0

VOL

5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4

9

14

Input Voltage . “0” Level

(VO = 3.8 or 0.5 Vdc)

(VO = 8.8 or 1.0 Vdc)(VO = 13.8 or 1.5 Vdc)

VIL

5.0

1015

—

— —

1.5

3.04.0

—

— —

2.25

4.506.75

1.5

3.04.0

—

— —

(VO = 0.5 or 3.8 Vdc) “1” Level

(VO = 1.0 or 8.8 Vdc)

(VO = 1.5 or 13.8 Vdc)

VIH 5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

Output Drive Voltage — Segments

(IOH = 0 mA) Source

(IOH = 5.0 mA)

(IOH = 10 mA)

(IOH

= 15 mA)

(IOH = 20 mA)

VOH

5.0 4.1

—

3.9

—

3.4

—

—

—

—

—

4.1

—

3.9

—

3.4

4.57

4.24

4.12

3.94

3.70

—

—

—

—

—

4

—

3

—

3



(IOH = 25 mA) — — — 3.54 — —

(IOH = 0 mA)

(IOH = 5.0 mA)

(IOH = 10 mA)

(IOH = 15 mA)

(IOH = 20 mA)

(IOH = 25 mA)

10 9.1

—

9.0

—

8.6

—

—

—

—

—

—

—

9.1

—

9.0

—

8.6

—

9.58

9.26

9.17

9.04

8.90

8.75

—

—

—

—

—

—

9

—

8

—

8

—

(IOH = 0 mA)

(IOH = 5.0 mA)(IOH = 10 mA)

(IOH = 15 mA)

(IOH = 20 mA)

(IOH = 25 mA)

15 14.1

—14

—

13.6

—

—

— —

—

—

—

14.1

—14

—

13.6

—

14.59

14.2714.18

14.07

13.95

13.80

—

— —

—

—

—

1

—1

—

1

—

MC14513B

ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to VSS)

VDD – 55 C 25 C

Characteristic Symbol Vdc Min Max Min Typ (4.) Max

Output Drive Current — RBO Output

(VOH = 2.5 V) Source

(VOH = 9.5 V)

(VOH = 13.5 V)

IOH

5.0

10

15

– 0.40

– 0.21

– 0.81

—

—

—

– 0.32

– 0.17

– 0.66

– 0.64

– 0.34

– 1.30

—

—

—

–

–

–

(VOL = 0.4 V) Sink

(VOL = 0.5 V)

(VOL = 1.5 V)

IOL 5.0

10

15

0.18

0.47

1.80

—

—

—

0.15

0.38

1.50

0.29

0.75

2.90

—

—

—

Output Drive Current — Segments

(VOL = 0.4 V) Sink

(VOL = 0.5 V)

(VOL = 1.5 V)

IOL

5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

Input Current Iin 15 — ± 0.1 — ±0.00001 ± 0.1


Quiescent Current

(Per Package) Vin = 0 or VDD,

Iout = 0 µA

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20Total Supply Current (5.) (6.)


Per Package)


buffers switching)

IT 5.0

10

15




4. Noise immunity specified for worst–case input combination.Noise Margin for both “1” and “0” level =

1.0 Vdc min @ VDD = 5.0 Vdc2.0 Vdc min @ VDD = 10 Vdc

2.5 Vdc min @ VDD = 15 Vdc5. The formulas given are for the typical characteristics only at 25 C.



6. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + 3.5 x 10 –3 (CL – 50) VDDf

where: IT is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.

20 ns 20 ns

90%50%1

2f

Input LE and RBI low, and Inputs D, BI and LT high.

f in respect to a system clock.

All outputs connected to respective CL loads.

VDD

VSS

VOH

VOL

A, B, AND C

ANY OUTPUT

10%

50% DUTY CYCLE

50%

MC14513B


VDDAll Types

Characteristic Symbol Vdc Min Typ

Output Rise Time — Segment Outputs tTLH

5.0

10

15

—

—

—

40

30

25

Output Rise Time — RBO Output tTLH

5.0

10

15

—

—

—

480

240

190

Output Fall Time — Segment Outputs (7.)


tTHL = (0.75 ns/pF) CL + 37.5 ns

tTHL = (0.55 ns/pF) CL + 37.5 ns

tTHL

5.0

10

15

—

—

—

125

75

65

Output Fall Time — RBO Outputs

tTHL = (3.25 ns/pF) CL + 107.5 ns

tTHL = (1.35 ns/pF) CL + 67.5 ns

tTHL = (0.95 ns/pF) CL + 62.5 ns

tTHL

5.0

10

15

—

—

—

270

135

110

Propagation Delay Time — A, B, C, D Inputs .tPLH = (0.40 ns/pF) CL + 620 ns

tPLH = (0.25 ns/pF) CL + 237.5 ns

tPLH = (0.20 ns/pF) CL + 165 ns

tPLH5.0

10

15

—

—

—

640

250

175


tPHL = (0.60 ns/pF) CL + 260 ns

tPHL = (0.35 ns/pF) CL + 182.5 ns

tPHL 5.0

10

15

—

—

—

720

290

200

Propagation Delay Time — RBI and BI Inputs (7.)

tPLH = (1.05 ns/pF) CL + 547.5 ns

tPLH

= (0.45 ns/pF) CL

+ 177.5 ns

tPLH = (0.30 ns/pF) CL + 135 ns

tPLH5.0

10

15

—

—

—

600

200

150



tPHL = (0.85 ns/pF) CL + 442.5 ns

tPHL = (0.45 ns/pF) CL + 177.5 ns

tPHL = (0.35 ns/pF) CL + 142.5 ns

tPHL 5.0

10

15

—

—

—

485

200

160

Propagation Delay Time — LT Input (7.)

tPLH = (0.45 ns/pF) CL + 290.5 ns

tPLH = (0.25 ns/pF) CL + 112.5 ns


tPLH5.0

10

15

—

—

—

313

125

90

tPHL = (1.3 ns/pF) CL + 248 nstPHL = (0.45 ns/pF) CL + 102.5 ns

tPHL = (0.35 ns/pF) CL + 72.5 ns

tPHL

5.0

10

15

—

—

—

313

125

90

Setup Time tsu 5.0

10

15

100

40

30

—

—

—

Hold Time th 5.0

10

15

60

40

30

—

—

—

Latch Enable Pulse Width tWL(LE)

5.0

10

520

220

260

110



MC14513B



INCANDESCENT READOUT FLUORESCENT READ

VDD

COMMON

CATHODE LED

VSS

≈ 1.7 V

VDD

COMMON

ANODE LED

VSS

VDD VDDVDD

DIRECT

(LOW BRIGHT

* *



GAS DISCHARGE READOUT LIQUID CRYSTAL (LC) RE

VSS VSS

VDD

APPROPRIATE

VOLTAGE VDD

MC14513B

LOGIC DIAGRAM

BI 4

A 7

B 1

C 2

D 6

LE 5

RBI 8 10 RBO

LT 30



MC14513B

TYPICAL APPLICATIONS FOR RIPPLE BLANKING

LEADING EDGE ZERO SUPPRESSION

CONNECT TO

VDD (1)

DISPLAYS

RBI RBO

a – – – – g –

MC14513B

INPUT

CODE

0 0 0 0

(0)

D C B A 1 1 0 0 0RBI RBI RBI RBI

D C B A D C B A D C B A D C B A

MC14513B MC14513B MC14513B MC14513B

0 0 0 0

(0)

0 1 0 1

(5)

0 0 0 0

(0)

0 0 0 1

(1)

a g a g a g a g

RBO RBO RBO RBO

– – – – – – – – – – – – – – – – – – – –

TRAILING EDGE ZERO SUPPRESSION

DISPLAYS



RBI

a g

MC14513B

0 1 0 1

(5)

D C B A 0 0 0 1 1RBO

D C B A D C B A D C B A D C B A D C

MC14513B MC14513B MC14513B MC14513B MC14

0 0 0 0

(0)

0 0 0 1

(1)

0 0 1 1

(3)

0 0 0 0

(0)

0 0

(

a g a g a g a g a

RBI RBI RBI RBIRBO RBORBO RBO RBO0

– – – – – – – – – – – – – – – – – – – – – – – – – – –

The MC14514B and MC14515B are two output options of a 4 to 16line decoder with latched inputs. The MC14514B (output active highoption) presents a logical “1” at the selected output, whereas the

MC14515B (output active low option) presents a logical “0” at theselected output. The latches are R–S type flip–flops which hold thelast input data presented prior to the strobe transition from “1” to “0”.These high and low options of a 4–bit latch/4 to 16 line decoder areconstructed with N–channel and P–channel enhancement modedevices in a single monolithic structure. The latches are R–S typeflip–flops and data is admitted upon a signal incident at the strobeinput, decoded, and presented at the output.

These complementary circuits find primary use in decoding

applications where low power dissipation and/or high noise immunityis desired.




http://onsem

1

24

PDIP–24

P SUFFIXCASE 709

M

24

SOIC–24





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C



XX = Specif

A = Assem

WL or L = Wafer


Device Packag

ORDERING INF

MC14514BCP PDIP–2

MC14514BDW SOIC–

C C

1

DW SUFFIX

CASE 751E

MC14514B, MC14515B

S5

S7

D2

D1

ST

S3

S4

S6 S10

D3

D4

INH

VDD

S15

S14

S9

5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

13

11

12

21

22

23

24

S13

S12

S8

S11

S0

VSS

S2

S1

PIN ASSIGNMENT

Data Inputs Selected Output

MC14514 = Logic “1”

Inhibit D C B A MC14515 = Logic “0”

0 0 0 0 0 S0

0 0 0 0 1 S1

0 0 0 1 0 S2

0 0 0 1 1 S3

0 0 1 0 0 S4

0 0 1 0 1 S5

0 0 1 1 0 S6

0 0 1 1 1 S7

0 1 0 0 0 S8

0 1 0 0 1 S9

0 1 0 1 0 S10

DECODE TRUTH TABLE (Strobe = 1)*



0 1 0 1 0 S10

0 1 0 1 1 S11

0 1 1 0 0 S12

0 1 1 0 1 S13

0 1 1 1 0 S14

0 1 1 1 1 S15

1 X X X X All Outputs = 0, MC14514

All Outputs = 1, MC14515

X = Don’t Care

*Strobe = 0, Data is latched

BLOCK DIAGRAM

VDD = PIN 24

VSS = PIN 12

2

3

DATA 1

DATA 2

A

B 4

5

6

7

8

10

9

11A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C DS6

S5

S4

S3

S2

S1

S0

MC14514B, MC14515B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL 5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.010

15

– 1.2

– 0.25 – 0.62

– 1.8

—

— —

—

– 1.0

– 0.2 – 0.5

– 1.5

– 1.7

– 0.36 – 0.9

– 3.5

—

— —

—

– 0

– 0 – 0

–


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

—

—

5.0

10

—

—

0.005

0.010

5.0

10

—

—



15 — 20 — 0.015 20 —



Per Package)


buffers switching)

ITL 5.0

10

15






IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14514B, MC14515B


All Typ

Characteristic Symbol VDD Min Typ (7

Output Rise Time




tTLH

5.0

10

15

—

—

—

180

90

65

Output Fall Time


tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 9.5 ns

tTHL

5.0

10

15

—

—

—

100

50

40

Propagation Delay Time; Data, Strobe to S




tPLH,

tPHL 5.0

10

15

—

—

—

550

225

150

Inhibit Propagation Delay Times




tPLH,

tPHL 5.0

10

15

—

—

—

400

150

100

Setup TimeData to Strobe tsu5.0

10

15

250

100

75

125

50

38

Hold Time

Strobe to Data

th 5.0

10

15

– 20

0

10

– 100

– 40

– 30

Strobe Pulse Width tWH

5.0

10

15

350

100

75

175

50

38

6. The formulas given are for the typical characteristics only at 25 C.7 Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe



7. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential pe

EXTERNAL

POWER SUPPLY

STROBE

INHIBIT

D1

D2

D3

D4

VDD

VDS

ID

For MC145151. For P–cha

2. For N–cha

2. and D1–D4

2. code for “o

For MC14514B

1. For P–channel: Inhibit = VSS

1. and D1–D4 constitute

1. binary code for “output

1. under test.”

2. For N–channel: Inhibit = VDD

S14

S13S12S11S10

S9S8S7S6S5S4S3S2S1

S0

MC14514B, MC14515B

Figure 2. Dynamic Power Dissipation Test Circuit and Waveform

PULSEGENERATOR

CL

CL

VDD

VDD

VSS

S0

S15

12

24

ID0.01 µF

CERAMIC500

µF

Vin

20 ns

90%

10%

STROBE

D1

D2

D3

D4

INHIBIT

PROGRAMMABLEPULSE

GENERATOR

VDD

STROBE

INHIBIT

D1

D2

CL

S0

S1

CL

INPUT

OUTPUT

tTLH

tPLH

20 n

OUTPUT S0

OUTPUT S1

90%50%

90%50%

10%




D3

D4S15

VSS CL

tTLHOUTPUT S15

50%10%

MC14514B, MC14515B

L O G I C

D I A G R A M

A B C D

1 1 S

0

9 S

1

1 0 S

2

8 S

3

7 S

4

6 S

5

5 S

6

4 S

7

1 8 S

8

1 7 S

9

2 0 S

1 0

1 9 S

1 1

1 4 S

1 2

1 3 S

1 3

1 6 S

1 4

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D

A B C D



Q Q

R S

Q Q

R S

Q Q

R S

Q Q

R S

A B C D

MC14514B, MC14515B

COMPLEX DATA ROUTING

Two MC14512 eight–channel data selectors are used herewith the MC14514B four–bit latch/decoder to effect acomplex data routing system. A total of 16 inputs from dataregisters are selected and transferred via a 3–state data busto a data distributor for rearrangement and entry into 16output registers. In this way sequential data can be re–routedor intermixed according to patterns determined by dataselect and distribution inputs.

Data is placed into the routing scheme via the eight inputson both MC14512 data selectors. One register is assigned toeach input. The signals on A0, A1, and A2 choose one of eight inputs for transfer out to the 3–state data bus. A fourthsignal, labelled Dis, disables one of the MC14512 selectors,assuring transfer of data from only one register.

In addition to a choice of input registers, 1 thru 16, the rateof transfer of the sequential information can also be varied.That is, if the MC14512 were addressed at a rate that is eight

times faster then the shift frequency the most significant bit (MSB) from selected for transfer to the data busmost significant bits from all of transferred to the data bus before thebit is presented for transfer by the inp

Information from the 3–state bus iMC14514B four–bit latch/decoder

address, D1 thru D4, the information be transferred to the addressed outpoutput registers, A thru P. This distribuoutput registers can be made in manyexample, all of the most significanregisters can be routed into output regmost significant bits into register horizontal, vertical, or other methodsimplemented.

DATA ROUTING SYSTEM

INPUTREGISTERS

DATATRANSFER

DATADISTRIBUTION

OUREG

3–STATEDATA BUS

REGISTER 1 DIS QD0

D1

D2



REGI

REGI

REGISTER 8

REGISTER 9

DATA

SELECT

STROBE

INHIBIT

Q

D1 D2 D3 D4

A0 A1 A2

A0 A1 A2

M C 1 4 5 1 4 B

M C 1 4 5 1 2

1 4 5 1 2

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3S15

S14

S13

S12

S11

S10

S9

S8

S7

S6

S5

S4

S3

S2

S1

S0

The MC14516B synchronous up/down binary counter isconstructed with MOS P–channel and N–channel enhancement modedevices in a monolithic structure.

This counter can be preset by applying the desired value, in binary,to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset

Enable (PE) high. The direction of counting is controlled by applyinga high (for up counting) or a low (for down counting) to theUP/DOWN input. The state of the counter changes on the positivetransition of the clock input.

Cascading can be accomplished by connecting the Carry Out to theCarry In of the next stage while clocking each counter in parallel. Theoutputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a highto the reset (R) pin.

This CMOS counter finds primary use in up/down and difference

counting. Other applications include: (1) Frequency synthesizerapplications where low power dissipation and/or high noise immunityis desired, (2) Analog–to–digital and digital–to–analog conversions,and (3) Magnitude and sign generation.

• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Internally Synchronous for High Speed• Logic Edge–Clocked Design — Count Occurs on Positive Going

Edge of Clock• Single Pin Reset• A h P t E bl O ti

http://onsem

A = Assem

WL or L = Wafer

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96



• Asynchronous Preset Enable Operation• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky Load Over the Rated Temperature Range





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14516BCP PDIP–

MC14516BD SOIC–

MC14516BDR2 SOIC–

1. For ordering information the SOIC packages, plea

MC14516BF SOEIAJ–


MC14516B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

P1

P2

Q2

C

VDD

R

U/D

Q1

P0

P3

Q3

PE

VSS

CARRY OUT

Q0

CARRY IN

BLOCK DIAGRAM


6

11

14

2

7

Q0

Q1

Q2

Q3

CARRY

OUT

PE

CARRY IN

RESETUP/DOWN

CLOCK

P0

P1

P2

P3

1

5

910

15

4

12

13

3



TRUTH TABLE

Carry In Up/Down

Preset

Enable Reset Clock Action

1 X 0 0 X No Count

0 1 0 0 Count Up

0 0 0 0 Count Down

X X 1 0 X Preset

X X X 1 X Reset

X = Don’t Care

NOTE: When counting up, the Carry Out signal is normally high and is low onlywhen Q0 through Q3 are high and Carry In is low. When counting down,Carry Out is low only when Q0 through Q3 and Carry In are low.

MC14516B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.010

15

— —

—

1.53.0

4.0

— —

—

2.254.50

6.75

1.53.0

4.0

— —

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.010

15

– 3.0

– 0.64 – 1.6

– 4.2

—

— —

—

– 2.4

– 0.51 – 1.3

– 3.4

– 4.2

– 0.88 – 2.25

– 8.8

—

— —

—

–

– 0 – 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —


IDD 5.010

15

— —

—

5.010

20

— —

—

0.0050.010

0.015

5.010

20

— —

—





Per Package)


buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14516B


All TypesCharacteristic Symbol VDD Min Typ (8.)

Output Rise and Fall TimetTLH, tTHL = (1.5 ns/pF) CL + 25 nstTLH, tTHL = (0.75 ns/pF) CL + 12.5 nstTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,tTHL 5.0

1015

— — —

1005040

Propagation Delay TimeClock to Q

tPLH, tPHL = (1.7 ns/pF) CL + 230 nstPLH, tPHL = (0.66 ns/pF) CL + 97 nstPLH, tPHL = (0.5 ns/pF) CL + 75 ns

tPLH,tPHL

5.01015

— — —

315130100

Clock to Carry OuttPLH, tPHL = (1.7 ns/pF) CL + 230 nstPLH, tPHL = (0.66 ns/pF) CL + 97 nstPLH, tPHL = (0.5 ns/pF) CL + 75 ns

tPLH,tPHL 5.0

1015

— — —

315130100

Carry In to Carry OuttPLH, tPHL = (1.7 ns/pF) CL + 230 nstPLH, tPHL = (0.66 ns/pF) CL + 97 nstPLH, tPHL = (0.5 ns/pF) CL + 75 ns

tPLH,tPHL 5.0

1015

— — —

1808060

Preset or Reset to QtPLH, tPHL = (1.7 ns/pF) CL + 230 ns


tPLH,tPHL 5.0

1015

—

— —

315

130100

Preset or Reset to Carry OuttPLH, tPHL = (1.7 ns/pF) CL + 465 nstPLH, tPHL = (0.66 ns/pF) CL + 192 nstPLH, tPHL = (0.5 ns/pF) CL + 125 ns

tPLH,tPHL 5.0

1015

— — —

550225150

Reset Pulse Width tw 5.01015

380200160

19010080


1015

350

170140

200

10075


——

3.06 0



1015

— —

6.08.0

7. The formulas given are for the typical characteristics only at 25 C.8. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential pe

MC14516B

SWITCHING CHARACTERISTICS (9.) (CL = 50 pF, TA = 25 C) (continued)

All TypesCharacteristic Symbol VDD Min Typ (10.)

Preset or Reset Removal TimeThe Preset or Reset signal must be low prior to apositive–going transition of the clock.

trem 5.01015

650230180

32511590

Clock Rise and Fall Time tTLH,tTHL

5.01015

— — —

— — —

Setup TimeCarry In to Clock

tsu 5.010

15

260120

100

13060

50Hold Time

Clock to Carry Inth 5.0

1015

02020

– 60 – 20

0

Setup TimeUp/Down to Clock

tsu 5.01015

500200150

25010075

Hold TimeClock to Up/Down

th 5.01015

– 70 – 10

0

– 160 – 60 – 40

Setup TimePn to PE

tsu 5.01015

– 40 – 30 – 25

– 120 – 70 – 50

Hold TimePE to Pn

th 5.01015

480420420

240210210

Preset Enable Pulse Width tWH 5.01015

20010080

1005040

9. The formulas given are for the typical characteristics only at 25 C.10.Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential pe



MC14516B


PULSEGENERATOR CL

CL

CL

CL

VDD

VARIABLEWIDTH

CLOCK

ID 0.01 µF

CERAMIC

20 ns

50%9

500 pF

Q0

Q1

Q2

Q3

CARRY

OUT

PE

CARRY IN

R

UP/DOWN

CLOCK

P0

P1

P2

P3

CL

LOGIC DIAGRAM

PE

C

QP

PE

C

QP

PE

C

QP

PE

C

Q214

P213

Q111

P04

Q06

P112

CLOCK

PRESET

ENABLE

RESET 9

1

15



T Q T Q T Q TCARRY OUT

CARRY IN

UP/DOWN

7

5

10

MC14516B

TOGGLE FLIP–FLOP

PE

C

T

Q

Q

P

PARALLEL IN

FLIP–FLOP FUNCTIONAL T

PresetEnable Clock T

1 X X

0 0

0 1

0 X

X = Don’t Care

RESET

PRESET ENABLE

CARRY IN OR

UP/DOWN

CLOCK

Q0 OR CARRY OUT

trem

tsu trem

th

tTLH

tPLH

tPHL

tPLHtTHL

50%

50%

90%

10%

50%

90%10%

CARRY OUT ONLY

tw(H)tw(H)

tw

1fcl



Figure 2. Switching Time Waveforms

PIN DESCRIPTIONS

INPUTS

P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Dataon these inputs is loaded into the counter when PE is takenhigh.

Carry In, (Pin 5) — This active–low input is used whenCascading stages. Carry In is usually connected to Carry Outof the previous stage. While high, Clock is inhibited.

Clock, (Pin 15) — Binary data is incremented ordecremented, depending on the direction of count, on thepositive transition of this input.

CONTROLS

PE, Preset Enable, (Pin 1) — Asynon the Preset Inputs. This pin is activclock when high.

R, Reset, (Pin 9) — Asynchronouputs to a low state. This pin is activeclock when high.

Up/Down, (Pin 10) — Controls thigh for up count, low for down coun

MC14516B

Figure 3. Presettable Cascaded 8–Bit Up/Down Counter

NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The M

Digit (M.S.D.) is disabled while C in is high. When the count of the L.S.D. reaches 0 (count down mode) or re

up mode), Cout goes low for one complete clock cycle, thus allowing the next counter to decrement/increm

(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cy

L.S.D.MC14516B

Cout

Q0 Q1 Q2 Q3

P0 P1 P2 P3

PE

R

U/D

CLOCK

CinM.S.D.

MC14516B

Cout

Q0 Q1 Q2 Q3

P0 P1 P2 P3

PE

R

U/D

CLOCK

Cin

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

P0 P1 P2 P3 P4 P5 P6 P7

THUMBWHEEL SWITCHES(OPEN FOR “0”)

+VDD+VDD

+VDD

OPEN = COUNT

CLOCK

RESET

RESISTORS = 10 k

0 = COUNT

1 = PRESET

1 = UP

0 = DOWN

PRESET

ENABLE



MC14516B

TIMING DIAGRAM FOR THE PRESETTABLE CASCADED 8–BIT UP/DOWN CO



MC14516B

Figure 4. Programmable Cascaded Frequency Divider

NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset

the maximum divide ratio of 255 may be obtained by applying a 1111 1111 to the preset inputs P0 to P7. For t

both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and

M.S.D.MC14516B

L.S.D.MC14516B

THUMBWHEEL SWITCHES(OPEN FOR “0”)

+VDD+VDD

Cout

+VDD

OPEN = COUNT

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q0 Q1 Q2 Q3

P0 P1 P2 P3

P0 P1 P2 P3

PE

RU/D

CLOCK

CinCout

Q0 Q1 Q2 Q3

P0 P1 P2 P3

PE

RU/D

CLOCK

Cin

P4 P5 P6 P7

CLOCK (fin)

RESET

RESISTORS = 10 k

fout =

finn



The MC14517B dual 64–bit static shift register consists of twoidentical, independent, 64–bit registers. Each register has separate clockand write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data

at the data input is entered by clocking, regardless of the state of the writeenable input. An output is disabled (open circuited) when the write enableinput is high. During this time, data appearing at the data input as well asthe 16–bit, 32–bit, and 48–bit taps may be entered into the device byapplication of a clock pulse. This feature permits the register to be loadedwith 64 bits in 16 clock periods, and also permits bus logic to be used.This device is useful in time delay circuits, temporary memory storagecircuits, and other serial shift register applications.


• Fully Static Operation• Output Transitions Occur on the Rising Edge of the Clock Pulse• Exceedingly Slow Input Transition Rates May Be Applied to the

Clock Input• 3–State Output at 64th–Bit Allows Use in Bus Logic Applications• Shift Registers of any Length may be Fully Loaded with 16 Clock

Pulses• Supply Voltage Range = 3.0 Vdc to 18 Vdc



http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751






(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current(DC or Transient) per Pin ±10 mA



500 mW

TA Operat ing Temperature Range –55 to +125 °C


TL Lead Temperature


260 °C

Device Packag

ORDERING INF

MC14517BCP PDIP–

MC14517BDW SOIC–


MC14517B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

CB

WEB

Q48B

Q16B

VDD

DB

Q32B

Q64B

CA

WEA

Q48A

Q16A

VSS

Q32A

Q64A

DA

FUNCTIONAL TRUTH TABLE (X = Don’t Care)

ClockWrite

Enable Data 16–Bit Tap 32–Bit Tap 48–Bit Tap

0 0 X Content of 16–BitDisplayed

Content of 32–BitDisplayed


Co

0 1 X High Impedance High Impedance High Impedance Hi

1 0 X Content of 16–BitDisplayed



Co

1 1 X High Impedance High Impedance High Impedance Hi

0 Data enteredinto 1st Bit




Co

1 Data enteredinto 1st Bit

Data at tapentered into 17–Bit



Hi

0 X Content of 16–BitDisplayed



Co

1 X High Impedance High Impedance High Impedance Hi



MC14517B


VDD – 55 C 25 CCharacteristic Symbol Vdc Min Max Min Typ (3.) Max M


Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.010

15

— —

—

1.53.0

4.0

— —

—

2.254.50

6.75

1.53.0

4.0

— —

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH

= 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —


IDD 5.010

15

— —

—

5.010

20

— —

—

0.0050.010

0.015

5.010

20

— —

—


(D i l Q i

IT 5.0

10


I (8 8 A/kH ) f I




Per Package)


buffers switching)

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14517B


Characteristic Symbol VDD

Min Typ (7.)





tTLH, tTHL

5.0

10

15

—

—

—

100

50

40





tPLH, tPHL

5.0

10

15

—

—

—

475

210

140


10

15

330

125

100

170

75

60


10

15

—

—

—

3.0

6.7

8.3


10

15

See Note (8.

Data to Clock Setup Time tsu 5.0

1015

0

1015

– 40

– 150

Data to Clock Hold Time th 5.0

10

15

150

75

35

75

25

10

Write Enable to Clock Setup Time tsu 5.0

10

15

400

200

110

170

65

50

Write Enable to Clock Release Time trel 5.0

1015

380

180100

160

5540

6. The formulas given are for the typical characteristics only at 25 C.7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe8 When shift register sections are cascaded the maximum rise and fall time of the clock input should be equal toor



8. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to ortime of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.

VDD

Q16 Q32 Q48 Q64

VDD

VDD

VSS

VSS

D

C

WE

D

C

WE

D

CREPETITIVE WAVEFORM

C

D

fo

(f = 1/2 fo)

MC14517B

Figure 2. Typical Output Source CurrentCharacteristics Test Circuit

Figure 3. Typical OutpuCharacteristics Te

EXTERNALPOWERSUPPLY

IOH

Vout = VOH

VDD = VGS

VSS

D

C

WE

D

C

WE

Q16 Q32 Q48 Q64

Q16 Q32 Q48 Q64

(Output being tested should be in the high–logic state)

VDD = VGS

VSS

D

C

WE

D

C

WE

Q16 Q32 Q48 Q64

Q16 Q32 Q48 Q64

(Output being tested should be in the lo

1 22 16 17 18 19

th1

th1

tWH

tWL

VOH

90%

10%

20 ns

trel

tPHL

90%

th0

t

tsu0

tsu0

50%

V

tsu1

tsu1

DATA IN 7 (9)

WRITE 3 (13)

CLOCK 4 (12)

PIN NO’S

tPLH



Figure 4. AC Test Waveforms

16–BIT OUTPUT 1 (15)

17–BIT INPUT


33–BIT INPUT


49–BIT INPUT


th1

th1

tTH

tTH

tTH

tTHL

OH

VOH

VOH

tPHL

tPHL

tPHL

tPLH

90%10%

tTLH

tTLH

tTLH

tTLH

th0

th0

th0

tsu020 ns

20 ns

20 ns

VDD

VDD

VDD

tsu0tsu1

tsu1

90%

10%50%

tPLH

tPLH

EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)

The MC14518B dual BCD counter and the MC14520B dual binarycounter are constructed with MOS P–channel and N–channelenhancement mode devices in a single monolithic structure. Eachconsists of two identical, independent, internally synchronous 4–stagecounters. The counter stages are type D flip–flops, with

interchangeable Clock and Enable lines for incrementing on either thepositive–going or negative–going transition as required whencascading multiple stages. Each counter can be cleared by applying ahigh level on the Reset line. In addition, the MC14518B will count outof all undefined states within two clock periods. These complementaryMOS up counters find primary use in multi–stage synchronous orripple counting applications requiring low power dissipation and/orhigh noise immunity.


• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Internally Synchronous for High Internal and External Speeds• Logic Edge–Clocked Design — Incremented on Positive Transition

of Clock or Negative Transition on Enable• Capable of Driving Two Low–power TTL Loads or One Low–power





http://onsem

A = Assem

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751

SOEIAJ–1

F SUFFIXCASE 96



DD pp y g g


(DC or Transient)

–0.5 to VDD + 0.5 V



±10 mA


500 mW



TL Lead Temperature


260 °C


3 Temperature Derating:

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14518BCP PDIP–

MC14518BDW SOIC–


MC14518BF SOEIAJ–

MC14518B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q1B

Q2B

Q3B

RB

VDD

CB

EB

Q0B

Q1A

Q0A

EA

CA

VSS

RA

Q3A

Q2A

BLOCK DIAGRAM


3

4

5

6

14

13

12

11

C

C

R

RQ3

Q2

Q1

Q0

Q3

Q2Q1

Q0CLOCK

1

2

CLOCK

ENABLE

ENABLE

7

9

10

15



TRUTH TABLE

Clock Enable Reset Action

1 0 Increment Counter

0 0 Increment Counter

X 0 No Change

X 0 No Change

0 0 No Change

1 0 No Change

X X 1 Q0 thru Q3 = 0

MC14518B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.010

15

— —

—

1.53.0

4.0

— —

—

2.254.50

6.75

1.53.0

4.0

— —

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —


IDD 5.010

15

— —

—

5.010

20

— —

—

0.0050.010

0.015

5.010

20

— —

—



IT 5.0

10





Per Package)


buffers switching)

15 IT = (1.7 µA/kHz) f + IDD

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe5. The formulas given are for the typical characteristics only at 25 C.

6. To calculate total supply current at loads other than 50 pF:IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14518B


All Types






tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40


Clock to Q/Enable to Q




tPLH,

tPHL

5.0

10

15

—

—

—

280

115

80

Reset to Q


tPHL = (0.66 ns/pF) CL + 117 ns


tPHL

5.0

10

15

—

—

—

330

130

90

Clock Pulse Width tw(H)

tw(L)

5.0

10

15

200

100

70

100

50

35


1015

—

— —

2.5

6.08.0

Clock or Enable Rise and Fall Time tTHL, tTLH 5.0

10

15

—

—

—

—

—

—

Enable Pulse Width tWH(E) 5.0

10

15

440

200

140

220

100

70

Reset Pulse Width tWH(R) 5.0

1015

280

12090

125

5540


10

15

– 5

15

20

– 45

– 15

– 5




PULSEGENERATOR

CLCLCL

CL

VDD

500 µF0.01 µFCERAMICID

Q3Q2Q1

Q0C

ER

MC14518B


PULSEGENERATOR

CLCLCL

CL

VDD

VSS

Q3

Q2

Q1

Q0C

ER

20 ns

Qtr

CLOCKINPUT

tWtWH

tPLH tPH

181716151413121110987654321

0987654321

210151413121110987654321 43

0987654321

CLOCK

ENABLE

RESET

Q0

Q1

Q2

Q3

Q0

Q1

MC14518B




Q1

Q2

Q3

MC14520B

MC14518B

Figure 4. Decade Counter (MC14518B) Logic Diagram

(1/2 of Device Shown)

D

CR

Q

Q

D

CR

Q

Q

D

CR

Q

Q

D

C

Q0 Q1 Q2

RESET

ENABLE

CLOCK

D Q D Q D Q D

Q0 Q1 Q2



Figure 5. Binary Counter (MC14520B) Logic Diagram

CR

Q CR

Q CR

Q C

RESET

ENABLE

CLOCK

The MC14521B consists of a chain of 24 flip–flops with an inputcircuit that allows three modes of operation. The input will function asa crystal oscillator, an RC oscillator, or as an input buffer for anexternal oscillator. Each flip–flop divides the frequency of theprevious flip–flop by two, consequently this part will count up to 224 =

16,777,216. The count advances on the negative going edge of theclock. The outputs of the last seven–stages are available for addedflexibility.

• All Stages are Resettable• Reset Disables the RC Oscillator for Low Standby Power Drain• RC and Crystal Oscillator Outputs Are Capable of Driving External

Loads• Test Mode to Reduce Test Time

• VDD′ and VSS′ Pins Brought Out on Crystal Oscillator Inverter toAllow the Connection of External Resistors for Low–PowerOperation


Schottky TTL Load over the Rated Temperature Range.




Vin, Vout Input or Output Voltage Range –0.5 to VDD + 0.5 V

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96



(DC or Transient)



± 10 mA



500 mW



TL Lead Temperature


260 °C


3. Temperature Derating:Plastic “P and D/DW” Packages 7 0 mW/ C From 65 C To 125 C

Device Packag

ORDERING INF

MC14521BCP PDIP–

MC14521BD SOIC–

MC14521BDR2 SOIC–


MC14521BFR2 SOEIAJ–

MC14521BF SOEIAJ–

MC14521B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q20

Q21

Q22

VDD

IN 1

Q18

Q19

OUT 2

VSS′

RESET

Q24

VSS

IN 2

VDD′

Q23

BLOCK DIAGRAM

OutputQ18

Q19

Q20

Q21

Q22

Q23

Q24

STAGES18 THRU 24

STAGES1 THRU 17

Q18 Q19 Q20 Q21 Q22 Q23 Q24

10 11 12 13 14 15 1

2

6

IN 2

9

IN 1

7

RESET


53

4

OUT 1VDD′

VSS′OUT2



MC14521B


VDD

– 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.010

15

— —

—

1.53.0

4.0

— —

—

2.254.50

6.75

1.53.0

4.0

— —

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc) Pins 4 & 7

(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)

IOH

5.0

5.0

1015

– 1.2

– 0.25

– 0.62 – 1.8

—

—

— —

– 1.0

– 0.2

– 0.5 – 1.5

– 1.7

– 0.36

– 0.9 – 3.5

—

—

— —

– 0

– 0

– 0 –


(VOH = 4.6 Vdc) Pins 1, 10,

(VOH = 9.5 Vdc) 11, 12, 13, 14

(VOH = 13.5 Vdc) and 15

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

—

—

5.0

10

—

—

0.005

0 010

5.0

10

—

—



(Per Package) 10

15

—

10

20

—

0.010

0.015

10

20

—



Per Package)


IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14521B



VDD

Vdc Min Typ (8.)

Output Rise and Fall Time (Counter Outputs)




tTLH, tTHL

5.0

10

15

—

—

—

100

50

40


Clock to Q18




tPHL, tPLH

5.0

10

15

—

—

—

4.5

1.7

1.3Clock to Q24




5.0

10

15

—

—

—

6.0

2.2

1.7


Reset to Qn

tPHL = (1.7 ns/pF) CL + 1215 ns

tPHL = (0.66 ns/pF) CL + 467 ns


tPHL

5.0

10

15

—

—

—

1300

500

375

Clock Pulse Width tWH(cl) 5.0

10

15

385

150

120

140

55

40


10

15

—

—

—

3.5

9.0

12


10

15

—

—

—

—

—

—

Reset Pulse Width tWH(R) 5.0

10

15

1400

600

450

700

300

225


10

15

30

0

40

– 200

– 160

110



15 – 40 – 110


PULSEGENERATOR

VDD

VDD VDD

Q18

Q19

Q20CL

CL

ID

IN 2

500 µF 0.01 µF

CERAMIC

20 ns

Vin90%

10%

MC14521B


PULSEGENERATOR

Q18

Q19

Q20

Q21

Q22

Q23

Q24

IN 2

R

VDD

VDD

′

VSS VSS′CL

CL

CL

CL

CL

CL

CL

VDD

20 ns 2

10%50%

10%50%

90%

IN 2

Qn

tPLH

tTLH

tWL

Characteristic

500 kHz

Circuit

Crystal CharacteristicsResonant Frequency

Equivalent Resistance, RS

500

1.0

External Resistor/Capacitor Values

Ro

CT

CS

47

82

20

Frequency Stability

Frequency Change as a Function

of VDD (TA = 25 C)

VDD Change from 5.0 V to 10 VVDD Change from 10 V to 15 V

Frequency Change as a Function

of Temperature (VDD = 10 V)

TA Change from – 55 C to + 25 C

MC14521 only

+ 6.0

+ 2.0

– 4.0

+ 100

VDD

VDD VDD′

OUT 1OUT 2

Q18Q19Q20

Q21Q22Q23Q24

IN 1

IN 2

R

R*

CS CT

Ro

18 M



MC14521 only

Complete Oscillator*

TA Change from +25 C to+125 C

MC14521 only

Complete Oscillator*

– 2.0

– 160

*Complete oscillator includes crystal, capacitors, and

Figure 4. Typical Data for Crystal OscFigure 3. Crystal Oscillator Circuit

VSS VSS′

Q24R

R*

CS CT

*Optional for low power operation,

10 kΩ ≤ R ≤ 70 kΩ.

MC14521B

Figure 5. RC Oscillator Stability Figure 6. RC Oscillator Fr

Function of RTC a

–55 –25 0 25 50 75 100 125

8.0

4.0

0

–4.0

–8.0

–12

–16

F R E Q U E N C Y D E V I A T I O N ( % )

TA, AMBIENT TEMPERATURE (°C), DEVICE ONLY

TEST CIRCUITFIGURE 7

VDD = 15 V

10 V

5.0 V

RTC = 56 kΩ,

C = 1000 pF

RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C

RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C

f , O S C I L L A T O R F R E Q U E N C Y ( k

H z )

100

50

20

10

5.0

1.0

2.0

0.1

0.2

0.5

1.0 k 10 k

0.0001 0.001

RTC, RESISTANCE (OH

C, CAPACITANCE (µ

VDD = 10

f AS A FUNCTIONOF C

(RTC = 56 kΩ)(RS = 120 k)

OUT 1OUT 2

Q18Q19Q20

Q21

Q22Q23Q24

IN 1

IN 2

R

VDD VDD′

VSS VSS′

VDDRS RTC

C

IN 1

IN 2

R

V

V

PULSEGENERATOR



Figure 7. RC Oscillator Circuit Figure 8. Functional T

MC14521B

FUNCTIONAL TEST SEQUENCE

Inputs Outputs

Reset In 2 Out 2 VSS′ VDD′ Q18 thruQ24

CounsectioCoun

1 0 0 VDD Gnd 0 Out 2togeth

A test function (see Figure 8) has been

included for the reduction of test time re uired to

0 1 1 First “on In

exercise all 24 counter stages. This test function

divides the counter into three 8–stage sections,

and 255 counts are loaded in each of the

8–stage sections in parallel. All flip–flops arenow at a logic “1”. The counter is now returned

01

—

— —

01

—

— —

255 “0are clOut 2

to the normal 24–stages in series configuration.

One more pulse is entered into Input 2 (In 2)1 1 1

The 2transi

which will cause the counter to ripple from an all

“1” state to an all “0” state.00

00

11

1 0n

VDD1

Coun24–st

1 0 1Out 2outpu

0 1 0Coun“1” st



MC14521B

LOGIC DIAGRAM

VDD5

RESET2

9

IN 1

6IN 2

7OUT 1

3VSS

4OUT 2

STAGES3 THRU 7

STAGES

11 THRU 15

1 2 8

9 10 16

17 18 19 20 21 22 23 24



10Q18

11Q19

12Q20

13Q21

14Q22

15Q23

1Q24

The MC14526B binary counter is constructed with MOS P–channeland N–channel enhancement mode devices in a monolithic structure.

This device is presettable, cascadable, synchronous down counterwith a decoded “0” state output for divide–by–N applications. In

single stage applications the “0” output is applied to the Preset Enableinput. The Cascade Feedback input allows cascade divide–by–Noperation with no additional gates required. The Inhibit input allowsdisabling of the pulse counting function. Inhibit may also be used as anegative edge clock.

This complementary MOS counter can be used in frequencysynthesizers, phase–locked loops, and other frequency divisionapplications requiring low power dissipation and/or high noiseimmunity.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Logic Edge–Clocked Design — Incremented on Positive Transition

of Clock or Negative Transition of Inhibit• Asynchronous Preset Enable• Capable of Driving Two Low–power TTL Loads or One Low–power





Vin, Vout Input or Output Voltage Range –0.5 to VDD + 0.5 V

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751

SOEIAJ–1

F SUFFIX

CASE 96



in out p p g g

(DC or Transient)DD



±10 mA



500 mW



TL Lead Temperature


260 °C


YY or Y Year

WW or W = Work

Device Packag

ORDERING INF

MC14526BCP PDIP–

MC14526BDW SOIC–


MC14526BF SOEIAJ–

MC14526B

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

“0”

CF

P2

Q2

VDD

Q1

RESET

P1

INHIBIT

PE

P3

Q3

VSS

CLOCK

P0

PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output

Clock Reset Inhibit

Preset

Enable

Cascade

Feedback “0”

Resulting

Function

X H X L L L Asynchronous reset*

X H X H L H Asynchronous reset

X H X X H H Asynchronous reset

X L X H X L Asynchronous preset

L H L X L Decrement inhibited

L L L X L Decrement inhibited

L L L L L No change** (inactive edge)

H L L L L No change** (inactive edge)

L L L L L

Decrement**

ecremen

X = Don’t Care

NOTES:** Output “0” is low when reset goes high only it PE and CF are low.

** Output “0” is high when reset is low, only if CF is high and count is 0000.



MC14526B







tTLH,

tTHL

(Figures 4, 5)

5.0

10

15

—

—

—

100

50

40

Propagation Delay Time (Inhibit Used as Negative

Edge Clock)

Clock or Inhibit to Q




tPLH,

tPHL

(Figures 4, 5, 6)

5.0

10

15

—

—

—

550

225

160

Clock or Inhibit to “0”




5.0

10

15

—

—

—

240

130

100


Pn to Q

tPLH,

tPHL

(Figures 4, 7)

5.0

10

15

—

—

—

260

120

100


Reset to Q

tPHL

(Figure 8)

5.0

10

15

—

—

—

250

110

80


Preset Enable to “0”

tPHL,

tPLH

(Figures 4, 9)

5.0

10

15

—

—

—

220

100

80

Clock or Inhibit Pulse Width tw

(Figures 5, 6)

5.0

10

15

250

100

80

125

50

40

Clock Pulse Frequency (with PE = low) fmax

(Figures 4, 5, 6)

5.0

10

15

—

—

—

2.0

5.0

6.6

Clock or Inhibit Rise and Fall Time tr,

tf(Figures 5, 6)

5.0

10

15

—

—

—

—

—

—

Setup Time

Pn to Preset Enable

tsu 5.0

10

90

50

40

15



(Figure 10) 15 40 10

Hold Time

Preset Enable to Pn

th

(Figure 10)

5.0

10

15

30

30

30

– 15

– 5

0

Preset Enable Pulse Width tw

(Figure 10)

5.0

10

15

250

100

80

125

50

40

Reset Pulse Width tw

(Figure 8)

5.0

10

15

350

250

200

175

125

100


10

10

20

– 110

30

MC14526B



Figure 2. Typical O

Characteristics Te

CF

PE

P0P1

P2

P3RESET

INHIBIT

CLOCK

Q0

Q1

Q2

Q3

“0”

VSS

VDD = –VGS

VOH

IOH

EXTERNALPOWERSUPPLY

CF

PE

P0P1

P2

P3RESET

INHIBIT

CLOCK

Q0

Q1

Q2

Q3

“0”

VSS

VDD = VGS

CF

PE

P0P1

P2

P3RESET

INHIBIT

CLOCK

Q0

Q1

Q2

Q3

“0”

VSS

VDD

CL

CL

CL

CL

CL

PULSEGENERATOR 20 ns 20 ns

CLOCK 90%

10%50%

VARIABLEVSS

VDD

DEVICEUNDERTEST



Figure 3. Power Dissipation Figure 4. Te

VARIABLEWIDTH 50% DUTY CYCLE *Includes all probe a

MC14526B

SWITCHING WAVEFORMS

Figure 5. Figure 6.

VDD

VSS

VDD

VSS

tr tf

tr tf

tf tr

CLOCK

ANY P

ANY Q

ANY Q

CLOCK

RESET

tPLH tPHL

tPLH tPHL

tw tw

tw

ANY QOR “0”

ANY QOR “0”

tTLH tTHL

1/fmax 1/fmax

90%50%

10%

90%50%

10%

90%50%10%

90%50%

10%

50%

90%50%

10%

tTLH

INHIBIT

tPLH tP

tPHL

50%

50%

trem



tr tf

VDDPRESETENABLE

ANY P

GND

90%50%

10%t t

50%

VALID

Figure 7. Figure 8.

MC14526B

PIN DESCRIPTIONS

Preset Enable (Pin 3) — If Reset is low, a high level onthe Preset Enable input asynchronously loads the counterwith the programmed values on P0, P1, P2, and P3.

Inhibit (Pin 4) — A high level on the Inhibit input pre–vents the Clock from decrementing the counter. With Clock(pin 6) held high, Inhibit may be used as a negative edgeclock input.

Clock (Pin 6) — The counter decrements by one for eachrising edge of Clock. See the Function Table for level

requirements on the other inputs.Reset (Pin 10) — A high level on Reset asynchronouslyforces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback ishigh, causes the “0” output to go high.

“0” (Pin 12) — The “0” (Zero) output issues a pulse oneclock period wide when the counter reaches terminal count(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high andPreset Enable is low. When presetting the counter to a value

other than all zeroes, the “0” output iedge of Preset Enable (when Cascade the Function Table.

Cascade Feedback (Pin 13) — If input is high, a high level is generatedthe count is all zeroes. If Cascade Feoutput depends on the Preset EnablFunction Table.

P0, P1, P2, P3 (Pins 5, 11, 14, 2) —

data inputs. P0 is the LSB.Q0, Q1, Q2, Q3 (Pins 7, 9, 15,

synchronous counter outputs. Q0 is thVSS (Pin 8) — The most negative p

This pin is usually ground.VDD (Pin 16) — The most po

potential. VDD may range from 3 to 18

STATE DIAGRAM

MC14526B

43210

15

14

13 7

6

5



12 11 10 9 8

MC14526B

MC14526B LOGIC DIAGRAM (Binary Down Counter)

CF

PE

INHIBIT

CLOCK

RESET

13

3

4

610

P0 Q0 P1 Q1 P2 Q2 P3

5 7 11 9 14 15

D

C

T

R Q

PE Q

D

C

T

R Q

PE Q

D

C

T

R

PEQ

VDDVDD



MC14526B


Divide–By–N, Single Stage

Figure 11 shows a single stage divide–by–N application.To initialize counting a number, N is set on the parallel

inputs (P0, P1, P2, and P3) and reset is taken highasynchronously. A zero is forced into the master and slaveof each bit and, at the same time, the “0” output goes high.Because Preset Enable is tied to the “0” output, preset isenabled. Reset must be released while the Clock is high sothe slaves of each bit may receive N before the Clock goeslow. When the Clock goes low and Reset is low, the “0”output goes low (if P0 through P3 are unequal to zero).

The counter downcounts with each rising edge of theClock. When the counter reaches the zero state, an outputpulse occurs on “0” which presets N. The propagation delaysfrom the Clock’s rising and falling edges to the “0” output’srising and falling edges are about equal, making the “0”output pulse approximately equal to that of the Clock pulse.

The Inhibit pin may be used to stop pulse counting. Whenthis pin is taken high, decrementing is inhibited.

Cascaded, Presettable Divide–By–

Figure 12 shows a three stage cascaReset high loads N. Only the first stsignificant counter) must be taken hifor all stages, but all pins could be tie

When the first stage’s Reset pin goeis latched in a high state. Reset must bis high and time allowed for Preset Enstages before Clock goes low.

When Preset Enable is high and Cbe allowed for the zero digits to Feedback to the first non–zero stage. most significant bit (M.S.B.) to the Lis equal to one (i.e. N = 1).

After N is loaded, each stage couneach rising edge of Clock. When any the leading stages (more significant output goes high and feeds back toWhen all stages are zero, the Preset loads N while the Clock is high and t

P0P1P2P3

CFRESETINHIBIT

CLOCK

PE

Q0Q1Q2Q3

“0”

N

VDD

VSSfin

BUFFERfin

N



Figure 11. ÷ N Counter

N0 N1 N2 N3 N4 N5 N6 N7

P0 P1 P2 P3 Q0 Q1 Q2 Q3fin CLOCK

INHIBITVSS

VDD

RESET “0” PE

CF

VSS

P0 P1 P2 P3 Q0 Q1 Q2 Q3

CLOCK

INHIBITRESET “0” PE

CF

CLOCK

INHIBITRESET

P0 P1 P2 P

N8 N9N10 N

VSS

LSB M

The MC14528B is a dual, retriggerable, resettable monostablemultivibrator. It may be triggered from either edge of an input pulse,and produces an output pulse over a wide range of widths, the durationof which is determined by the external timing components, CX and

RX.• Separate Reset Available• Diode Protection on All Inputs• Triggerable from Leading or Trailing Edge Pulse• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range• Pin–for–Pin Replacement with the MC14538B





(DC or Transient)

–0.5 to VDD + 0.5 V


(DC or Transient) per Pin± 10 mA



500 mW



http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

ORDERING INF

PDIP–16

P SUFFI

CASE 64

SOIC–1D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96



stg

TL Lead Temperature


260 °C








U d i t t l b ti d t i t l i lt l l (

Device Packag

ORDERING INF

MC14528BCP PDIP–

MC14528BD SOIC–

MC14528BDR2 SOIC–

1. For ordering information the SOIC packages plea


MC14528BF SOEIAJ–

MC14528B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

A2

RESET 2

CX2/RX2

VSS

VDD

Q2

Q2

B2

A1

RESET 1

CX1/RX1

VSS

VSS

Q1

Q1

B1

BLOCK DIAGRAM

RESET 1

RESET 2

VDD

VDD

Q1

Q1

Q2

Q2

A1

B1

A2

B2

CX1

CX2 RX2

RX1

1 2

4

5

3

6

7

1415

12

11

13

10

9



RESET 2

VDD = PIN 16

VSS = PIN 1, PIN 8, PIN 15RX AND CX ARE EXTERNAL COMPONENTS

ONE–SHOT SELECTION GUIDE

100 ns 1 s 10 s 100 s 1 ms 10 ms 100 ms 1 s 10 s

MC14528B

MC14528B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)(VO = 13.5 or 1.5 Vdc)

VIL

5.0

1015

—

— —

1.5

3.04.0

—

— —

2.25

4.506.75

1.5

3.04.0

—

— —

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)

IOH

5.0

5.0

1015

– 1.2

– 0.64

– 1.6 – 4.2

—

—

— —

– 1.0

– 0.51

– 1.3 – 3.4

– 1.7

– 0.88

– 2.25 – 8.8

—

—

— —

– 0

– 0

– 0 – 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL

5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

1015

—

— —

5.0

1020

—

— —

0.005

0.0100.015

5.0

1020

—

— —

Total Supply Current at an

external load Capacitance (CL)

and at external timing

capacitance (CX), use the

formula — (5.)

IT — IT(CL, CX) = [(CL + 0.36CX)VDDf + 2x10 –8

RXCX(VDD –2)2f] x 10 –3

where: IT in µA (per circuit), CL and CX in pF, RX in m

VDD in Vdc, f in kHz is input frequency.

MC14528B



CX

pF

RX

kΩ

VDD

Vdc Min TypOutput Rise and Fall Time




tTLH,

tTHL

— —

5.0

10

15

—

—

—

100

50

40

Turn–Off, Turn–On Delay Time — A or B to Q or Q




tPLH,

tPHL

15 5.0

5.0

10

15

—

—

—

325

120

90

Turn–Off, Turn–On Delay Time — A or B to Q or Q



tPLH,

tPHL

1000 10

5.010

15

— —

—

705290

210

Input Pulse Width — A or B tWH 15 5.0 5.0

10

15

150

75

55

70

30

30

tWL 1000 10 5.0

10

15

—

—

—

70

30

30

Output Pulse Width — Q or Q(For CX < 0.01 µF use graph for

appropriate VDD level.)

tW 15 5.0 5.010

15

— —

—

550350

300

Output Pulse Width — Q or Q

(For CX > 0.01 µF use formula:

tW = 0.2 RX CX Ln [VDD – VSS]) (6.)

tW 10,000 10 5.0

10

15

15

10

15

30

50

55

Pulse Width Match between Circuits in the same

package

t1 – t2 10,000 10 5.0

10

15

—

—

—

6.0

8.0

8.0

Reset Propagation Delay — Reset to Q or Q tPLH,

tPHL

15 5.0 5.0

1015

—

— —

325

9060

1000 10 5.0

10

15

—

—

—

100

300

250

Retrigger Time trr 15 5.0 5.0

10

15

0

0

0

—

—



15 0 —

1000 10 5.0

1015

0

00

—

— —

External Timing Resistance RX — — — 5.0 —

External Timing Capacitance CX — — — No Lim

6. RX is in Ohms, CX is in farads, VDD and VSS in volts, PWout in seconds.7. If CX > 15 µF, Use Discharge Protection Diode DX, per Fig. 9.8. The formulas given are for the typical characteristics only at 25 C.9. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe

MC14528B

FUNCTION TABLE

Inputs Outputs

Reset A B Q Q

H H

H L

H L Not Triggered

H H Not Triggered

H L, H, H Not Triggered

H L L, H, Not Triggered

L X X L H

X X Not Triggered

Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Cu

VDD VDD

OPEN

VSS VSS

RESET

A

B

Q

Q

16

8

16

8

RESET

A

B

Q

Q

IOH

VOH

VDD

ID500 pF

20 ns

0.1 F

CERAMIC

RX′

CX′

RX

CX



DUTY CYCLE = 50%

CL

CL

CL

CL

VSS

Vin

Vin

90%

10%

A

B

RESET

A′

B′

RESET′

Q

Q

Q′

Q′

MC14528B

INPUT CONNEC

Characteristics Rese

tPLH, tPHL, tTLH, tTHL

tW

VDD

tPLH, tPHL, tTLH, tTHL

tW

VDD

tPLH(R), tPHL(R), tW PG3

90%10%

90%10%

50%50% 50%

50%

50%

50%

tTLH

tTHLtTLH

tTHL

90%

10%

tTLH

tTHL

tTHL tTLH

50%90%

10%

50%

50%

tWL

tPLH

50%50% 50%90%10%

A

B

Q

Q

RESET

tWH

tTLH tTHL

tPHLtPHL

tPHL

tWL

tPHL

tW

Figure 4. AC Test Circuit

PULSEGENERATOR

PULSEGENERATOR

PULSEGENERATOR

VDD

RX′

CX′

RX

CX

VSS

A

B

RESET

A′

B′

RESET′

Q

Q

Q′

Q′

CL

CL

CL

CL

P

P

P

*CX = 15 pF

*CL = 15 pFRX = 5.0 k

*Includes capacitance of probes,wiring, and fixture parasitic.

NOTE: AC test waveforms for

PG1, PG2, and PG3 on

next page.



Figure 5. AC Test Waveforms

E W I D T H ( s )

1000

100

10

VDD = 15 V

10 V5.0 V

15 V

10 V

5.0 V

15 V10 V

5.0 V

RX = 100 k

MC14528B


Figure 7. Retriggerable

Monostables Circuitry

Figure 8. Non–R

Monostables

VDD

RxCx

VDD

Q

Q

RESET

FALLING EDGE

TRIGGER

RISING EDGE

TRIGGER

VDD

RxC

x

VDD

Q

Q

RESET

A

B

A

B

VDD

FALLING EDGE

TRIGGER

RISING EDGE

TRIGGER A

B

A

B

VDD

VDD

DX

Rx

Cx

Q

A

B

1, 1



Figure 9. Use of a Diode to Limit

Power Down Current Surge

Figure 10. Connection o

VDD

VDD

Q

RESET

VDD

B

The MC14532B is constructed with complementary MOS (CMOS)enhancement mode devices. The primary function of a priorityencoder is to provide a binary address for the active input with thehighest priority. Eight data inputs (D0 thru D7) and an enable input(Ein) are provided. Five outputs are available, three are address outputs(Q0 thru Q2), one group select (GS) and one enable output (Eout).

• Diode Protection on All Inputs• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–Power

Schottky TTL Load over the Rated Temperature Range





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C


3. Temperature Derating:Pl ti “P d D/DW” P k 7 0 W/ C F 65 C T 125 C

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

ORDERING INF

PDIP–16

P SUFFI

CASE 64

SOIC–1D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96










Device Packag

MC14532BCP PDIP–

MC14532BD SOIC–

MC14532BDR2 SOIC–


MC14532BF SOEIAJ–

MC14532BFR1 SOEIAJ–

MC14532B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D2

D3

GS

Eout

VDD

Q0

D0

D1

D7

D6

D5

D4

VSS

Q1

Q2

Ein

TRUTH TABLE

Input Output

Ein D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 Eout

0 X X X X X X X X 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0 0 1

1 1 X X X X X X X 1 1 1 1 01 0 1 X X X X X X 1 1 1 0 0

1 0 0 1 X X X X X 1 1 0 1 0

1 0 0 0 1 X X X X 1 1 0 0 0

1 0 0 0 0 1 X X X 1 0 1 1 0

1 0 0 0 0 0 1 X X 1 0 1 0 0

1 0 0 0 0 0 0 1 X 1 0 0 1 0

1 0 0 0 0 0 0 0 1 1 0 0 0 0

X = Don’t Care



MC14532B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)(VO = 13.5 or 1.5 Vdc)

VIL

5.0

1015

—

— —

1.5

3.04.0

—

— —

2.25

4.506.75

1.5

3.04.0

—

— —

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH

= 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

1015

—

— —

5.0

1020

—

— —

0.005

0.0100.015

5.0

1020

—

— —



Per Package)


buffers switching)

IT 5.0

10

15




4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential pe5 Th f l i f h i l h i i l 25 C




IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14532B



Output Rise and Fall TimetTLH, tTHL = (1.5 ns/pF) CL + 25 ns



tTLH,tTHL 5.0

10

15

—

—

—

100

50

40

Propagation Delay Time — Ein to Eout




tPLH,

tPHL 5.0

10

15

—

—

—

205

110

80

Propagation Delay Time — Ein to GS


tPLH, tPHL = (0.66 ns/pF) CL 57 ns


tPLH,

tPHL 5.0

10

15

—

—

—

175

90

65

Propagation Delay Time — Ein to Qn




tPHL,

tPLH 5.0

10

15

—

—

—

280

140

100

Propagation Delay Time — Dn to Qn




tPLH,

tPHL 5.0

10

15

—

—

—

300

170

110Propagation Delay Time — Dn to GS




tPLH,

tPHL 5.0

10

15

—

—

—

280

140

100


SWITCHMATRIX

ID

Ein

D0

D1

D2

D3

D4

D5 GS

Q2

Q1

Q0

Eout

Vout

VDD



Output

Under

VGS = VDD

VDS = Vout

Sink Current

VGS = – VDD

VDS = Vout – VDD

Source Current

Test D0 thru D7 Ein D0 thru D6 D7 Ein

EXTERNALPOWERSUPPLY

D6

D7

Ein

D0

D1

D2

D3

D4

ID

Q1

Q0

Eout

500 µF

MC14532B

PROGRAMMABLEPULSE

GENERATOR

Ein

D0

D1

D2

D3

D4

D5

D6

D7 GS

Q2

Q1

Q0

Eout

VDD

VSS

CL

CL

CL

CL

CL

NOTE: Input rise and fall times are 20

50%

50%

50%

50%

50%

50%

50%

50%

tTLH

tPHLtPLH

tTHL

90%50%

10%

tPLH

D0

D1

D2

D3

D4

D5

D6

D7

Ein

Eout

GS

10

11

12

13

1

2

3

4

5

15

14

PINNO.



tPHL

tPLHtPLHtPLH

tPLH

tPLH

tPLH

tPLH

tTLH

tTLH

tTLH

tPHL tPHL tPHL

GS

Q0

Q1

14

9

7

MC14532B

LOGIC DIAGRAM

(Positive Logic)LOGIC EQUATIONS

Eout = Ein D0 D1 D2 D3 D4 D5

10

11

12

13

1

2

3

4

5

D0

D1

D2

D3

D4

D5

D6

D7

Q0 = Ein (D1 D2 D4 D6 + D3 D4

Q1 = Ein (D2 D4 D5 + D3 D4 D5 +

Q2 = Ein (D4 + D5 + D6 + D7)

GS = Ein (D0 + D1 + D2 + D3 + D4 + 05



5Ein



The MC14536B programmable timer is a 24–stage binary ripplecounter with 16 stages selectable by a binary code. Provisions for anon–chip RC oscillator or an external clock are provided. An on–chipmonostable circuit incorporating a pulse–type output has beenincluded. By selecting the appropriate counter stage in conjunctionwith the appropriate input clock frequency, a variety of timing can be

achieved.• 24 Flip–Flop Stages — Will Count From 20 to 224

• Last 16 Stages Selectable By Four–Bit Select Code• 8–Bypass Input Allows Bypassing of First Eight Stages• Set and Reset Inputs• Clock Inhibit and Oscillator Inhibit Inputs• On–Chip RC Oscillator Provisions• On–Chip Monostable Output Provisions

• Clock Conditioning Circuit Permits Operation With Very Long Riseand Fall Times

• Test Mode Allows Fast Test Sequence• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power






(DC or Transient)

–0.5 to VDD + 0.5 V


C

±10 mA

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751

SOEIAJ–1

F SUFFIX

CASE 96






500 mW



TL Lead Temperature


260 °C


Device Packag

ORDERING INF

MC14536BCP PDIP–

MC14536BDW SOIC–


MC14536BF SOEIAJ–

MC14536B

BLOCK DIAGRAM

STAGES 9 THRU 24

Q

18

Q

17

Q

16

Q

15

Q

14

Q

13

Q

12

Q

11

Q

10

Q

9

DECODER

MONOSTABLE

MULTIVIBRATORMONO–IN 15

D 12

C 11B 10A 9


STAGES

1 THRU 8

8 BYPASSSETRESETCLOCK INH.7 2 1 6

5

OUT2

4

OUT1

3IN1

OSC. INHIBIT 14

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D

DECODE

OSC INH

MONO IN

VDD

A

B

C

OUT 1

IN 1

RESET

SET

VSS

CLOCK INH

8–BYPASS

OUT 2



MC14536B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)(VO = 13.5 or 1.5 Vdc)

VIL

5.0

1015

—

— —

1.5

3.04.0

—

— —

2.25

4.506.75

1.5

3.04.0

—

— —

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc) Pins 4 & 5

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 1.2

– 0.25

– 0.62

– 1.8

—

—

—

—

– 1.0

– 0.25

– 0.5

– 1.5

– 1.7

– 0.36

– 0.9

– 3.5

—

—

—

—

– 0

– 0

– 0

–


(VOH = 4.6 Vdc) Pin 13

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.010

0.020

0.030

5.0

10

20

—

—

—



Per Package)

(C 50 pF on all outputs all

IT 5.0

10

15







buffers switching)


IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14536B



Output Rise and Fall Time (Pin 13)tTLH, tTHL = (1.5 ns/pF) CL + 25 ns



tTLH,tTHL 5.0

10

15

—

—

—

100

50

40


Clock to Q1, 8–Bypass (Pin 6) High




tPLH,

tPHL

5.0

10

15

—

—

—

1800

650

450

Clock to Q1, 8–Bypass (Pin 6) Low



tPLH,

tPHL 5.010

15

— —

—

3.81.5

1.1

Clock to Q16




tPLH,

tPHL 5.0

10

15

—

—

—

7.0

3.0

2.2

Reset to Qn

tPHL = (1.7 ns/pF) CL + 1415 ns

tPHL

= (0.66 ns/pF) CL

+ 567 ns


tPHL

5.0

10

15

—

—

—

1500

600

450


10

15

600

200

170

300

100

85

Clock Pulse Frequency

(50% Duty Cycle)

fcl 5.0

10

15

—

—

—

1.2

3.0

5.0

Clock Rise and Fall Time tTLH,

tTHL

5.0

10

15

No Limit


10

15

1000

400

300

500

200

150




MC14536B

PIN DESCRIPTIONS

INPUTS

SET (Pin 1) — A high on Set asynchronously forcesDecode Out to a high level. This is accomplished by settingan output conditioning latch to a high level while at the sametime resetting the 24 flip–flop stages. After Set goes low(inactive), the occurrence of the first negative clocktransition on IN1 causes Decode Out to go low. Thecounter’s flip–flop stages begin counting on the secondnegative clock transition of IN1. When Set is high, theon–chip RC oscillator is disabled. This allows for verylow–power standby operation.

RESET (Pin 2) — A high on Reset asynchronouslyforces Decode Out to a low level; all 24 flip–flop stages arealso reset to a low level. Like the Set input, Reset disablesthe on–chip RC oscillator for standby operation.

IN1 (Pin 3) — The device’s internal counters advance onthe negative–going edge of this input. IN1 may be used as anexternal clock input or used in conjunction with OUT1 andOUT

2to form an RC oscillator. When an external clock is

used, both OUT1 and OUT2 may be left unconnected orused to drive 1 LSTTL or several CMOS loads.

8–BYPASS (Pin 6) — A high on this input causes the first8 flip–flop stages to be bypassed. This device essentiallybecomes a 16–stage counter with all 16 stages selectable.Selection is accomplished by the A, B, C, and D inputs. (Seethe truth tables.)

CLOCK INHIBIT (Pin 7) — A high on this inputdisconnects the first counter stage from the clocking source.This holds the present count and inhibits further counting.However, the clocking source may continue to run.Therefore, when Clock Inhibit is brought low, no oscillatorstart–up time is required. When Clock Inhibit is low, thecounter will start counting on the occurrence of the firstnegative edge of the clocking source at IN1.

OSC INHIBIT (Pin 14) — A highthe RC oscillator which allows for veroperation. May also be used, in conjunclock, with essentially the same resulinput.

MONO–IN (Pin 15) — Used as on–chip monostable multivibrator. Ifconnected to VSS, the monostable cDecode Out is directly connected to The monostable circuit is enabled if abetween Mono–In and VDD. This resinternal capacitance will determine pulse widths. With the addition of anVSS, the pulse width range may be eoperation the resistor value should be 5 kΩ to 100 kΩ and the capacitor valua maximum of 1000 pf. (See figures

A, B, C, D (Pins 9, 10, 11, 12) — Tflip–flop stage to be connected to Dectables.)

OUTPUTS

OUT1, OUT2 (Pin 4, 5) — Outpuwith IN1 to form an RC oscillatobuffered and may be used for 20 freexternal clock.

DECODE OUT (Pin 13) — Outpuconfiguration. When the monostable c

output is a 50% duty cycle square wa

TEST MODE

The test mode configuration divstages into three 8–stage sections tosequence. The test mode is enabled whReset are at a high level. (See Figure



MC14536B

TRUTH TABLES

InputSta e Selected

8–Bypass D C B A

for Decode Out0 0 0 0 0 9

0 0 0 0 1 10

0 0 0 1 0 11

0 0 0 1 1 12

0 0 1 0 0 13

0 0 1 0 1 14

0 0 1 1 0 150 0 1 1 1 16

0 1 0 0 0 17

0 1 0 0 1 18

0 1 0 1 0 19

0 1 0 1 1 20

0 1 1 0 0 21

0 1 1 0 1 220 1 1 1 0 23

0 1 1 1 1 24

Input

8–Bypass D C B A1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 01 0 1 1 1

1 1 0 0 0

1 1 0 0 1

1 1 0 1 0

1 1 0 1 1

1 1 1 0 0

1 1 1 0 11 1 1 1 0

1 1 1 1 1

FUNCTION TABLE

In1 Set Reset

Clock

Inh

OSC

Inh Out 1 Out 2

Decode

Out

0 0 0 0 No

Change

0 0 0 0 Advance to

next state

X 1 0 0 0 0 1 1

X 0 1 0 0 0 1 0

X 0 0 1 0 — — No

Change

X 0 0 0 1 0 1 No

Ch



Change

0 0 0 0 X 0 1 No

Change

1 0 0 0 Advance to

next state

X = Don’t Care

MC14536B

LOGIC DIAGRAM

S T A G E S

1 8 T H R U

2 3

2 4

1 7

S T A G E S

1 0 T H R U

1 5

1 6

T

9

S T A G E S

2 T H R U 7

8

T

1

6

2

R E S E T

8 –

B Y P A S S

R

E n

C

S

Q

A

9

B

1 0

C

1 1

D

1 2

D E C O D

E R

D E C O D E R

O U T

1 3

1 5

M O N O –

I N

V D D =

P I N 1 6

V S S =

P I N 8



1 4

I N H I B I T

4 O U T 1

O U T 2

5

S E T

1

7

C L O C K

I N H I B I T

E C



MC14536B

Figure 6. Power Dissipation Test

Circuit and Waveform

Figure 7. Switching Time Test Circuit

VDD

0.01 µF

CERAMIC500 µF ID

CL

CL

CL

VSS

PULSE

GENERATOR

SET

RESET

8–BYPASS

IN1

C INH

MONO IN

OSC INH

C

B

A

D

OUT 1

OUT

2

DECODE

OUT

20 ns 20 ns

90%10%

50%

50%

DUTY CYCLE

PULSE

GENERATOR

SET

RESET

8–BYPASS

IN1

C INH

MONO INOSC INH

C

B

A

D

OUT 1

OUT

2

DECODE

OUT CL

VSS

VDD

20 ns

IN1

tWL

90%

10%

tPLHtTL

OUT


Test function (Figure 8) has been included for thereduction of test time required to exercise all 24 counterstages. This test function divides the counter into three8–stage sections and 255 counts are loaded in each of the8–stage sections in parallel. All flip–flops are now at a “1”.

The counter is now returned to the normal 24–stages inseries configuration. One more pulse is entered into In1which will cause the counter to ripple from an all “1” stateto an all “0” state.

Figure 8. Functional Te

PULSE

GENERATOR

SET

RESET

8–BYPAS

IN1

C INH

MONO IN

OSC INH

C

B

A

D

DE



MC14536B


Inputs Outputs Comments

In1 Set Reset 8–Bypass Decade OutQ1 thru Q24 All 24 stages are in Reset mode

1 0 1 1 0

1 1 1 1 0 Counter is in three 8 stage sections in parallel m

0 1 1 1 0 First “1” to “0” transition of clock.

1

0

—

—

—

1 1 1 255 “1” to “0” transitions are clocked in the coun

0 1 1 1 1 The 255 “1” to “0” transition.

0 0 0 0 1 Counter converted back to 24 stages in series m

Set and Reset must be connected together and

go from “1” to “0”.

1 0 0 0 1 In1 Switches to a “1”.

0 0 0 0 0 Counter Ripples from an all “1” state to an all “0



MC14536B

NOTE: When power is first applied to the device, Decode Out can be either at a high or low sta

On the rising edge of a Set pulse the output goes high if initially at a low state. The outp

remains high if initially at a high state. Because Clock Inh is held high, the clock source

the input pin has no effect on the output. Once Clock Inh is taken low, the output goes lo

PULSE

GEN.

PULSE

GEN.CLOCK

8–BYPASS

A

B

C

D

RESET

OSC INH

MONO–IN

SET

CLOCK INH

IN1 VSSDECODE OUT

OUT 2

OUT 1

8

16

+V

6

9

10

11

12

2

14

15

1

7

3 13

5

4

DECODE OUT

CLOCK INH

SET

IN1

POWER UP

VDD



on the first negative clock transition. The output returns high depending on the 8–BypasA, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = t

number of stages selected from the truth table) is obtainable at Decode Out. A 20 –divid

output of IN1 can be obtained at OUT1 and OUT2.

Figure 9. Time Interval Configuration Using an External Clock, Set,

and Clock Inhibit Functions

(Divide–by–2 Configured)

MC14536B

Figure 10. Time Interval Configuration Using an External Clock, Reset,

d O M bl A hi P l O

NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. B

input low enables the chip’s internal counters. After Reset goes low, the 2n /2 negative transition of the c

Decode Out to go high. Since the Mono–In input is being used, the output becomes monostable. The p

output is dependent on the external timing components. The second and all subsequent pulses occur

period) intervals where n = the number of stages selected from the truth table.

PULSE

GEN.

CLOCK

8–BYPASS

A

B

C

D

RESET

SET

CLOCK INH

MONO–IN

CLOCK INH

IN1 VSSDECODE OUT

OUT 2

OUT 1

8

16

+V

6

9

10

11

12

2

1

7

15

14

3 13

5

4

DECODE OUT

RESET

IN1

POWER UP

VDD

RX

CX

*tw ≈ .00247

tw in µsec

RX in kΩCX in pF

*tw



and Output Monostable to Achieve a Pulse Output(Divide–by–4 Configured)

MC14536B

NOTE: This circuit is designed to use the on–chip oscillation function. The oscillator frequency is

mined by the external R and C components. When power is first applied to the device, Decod

i iti li t hi h t t B thi t t i ti d di tl t th O I h i t th ill

PULSE

GEN.

8–BYPASS

A

B

C

D

RESET

SET

CLOCK INHMONO–IN

CLOCK INH

IN1 VSSDECODE OUT

OUT 2

OUT 1

8

16

+V

6

9

10

11

12

2

14

15

1

7

3 13

5

4

VDD

RS

RTC

C

OUT 2

OUT 1

RESET

POWER UP

Rs

F

R

C

DECODE OUT

tw

≥ Rtc

= Hz

= Oh

= FA

fosc



Figure 11. Time Interval Configuration Using On–Chip RC Oscillator and

Reset Input to Initiate Time Interval

initializes to a high state. Because this output is tied directly to the Osc–Inh input, the oscill

disabled. This puts the device in a low–current standby condition. The rising edge of the Rese

will cause the output to go low. This in turn causes Osc–Inh to go low. However, while Reset i

the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remai

for 2n /2 of the oscillator’s period. After the part times out, the output again goes high.

The MC14538B is a dual, retriggerable, resettable monostablemultivibrator. It may be triggered from either edge of an input pulse,and produces an accurate output pulse over a wide range of widths, the

duration and accuracy of which are determined by the external timingcomponents, CX and RX.

Output Pulse Width = (Cx) (Rx) where:Rx is in kCx is in F

• Unlimited Rise and Fall Time Allowed on the A Trigger Input• Pulse Width Range = 10 µs to 10 s• Latched Trigger Inputs

• Separate Latched Reset Inputs• 3.0 Vdc to 18 Vdc Operational Limits• Triggerable from Positive (A Input) or Negative–Going Edge

(B–Input)• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range• Pin–for–pin Compatible with MC14528B and CD4528B (CD4098)• Use the MC54/74HC4538A for Pulse Widths Less Than 10 µs with

Supplies Up to 6 V.





(DC or Transient)

–0.5 to VDD + 0.5 V



±10 mA

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

ORDERING INF

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751

SOEIAJ–1

F SUFFIX

CASE 96

SOIC–16

D SUFFI

CASE 751

TSSOP–DT SUFF

CASE 94






500 mW



TL Lead Temperature


260 °C

Device PackagORDERING INF

MC14538BCP PDIP–

MC14538BD SOIC–

MC14538BDR2 SOIC–

MC14538BDT TSSOP–

MC14538B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

AB

RESET B

CX /RXB

VSS

VDD

QB

QB

BB

AA

RESET A

CX /RXA

VSS

VSS

QA

QA

BA

BLOCK DIAGRAM

VDD

VDD

6

7

10

9

12

11

5

4 A

B

CX RX

1 2

Q1

Q1RESET

3

CX RX

15 14

Q2

Q2RESET

13

A

B

RX AND CX ARE EXTERNAL COMPONENTS.

VDD = PIN 16

VSS = PIN 8, PIN 1, PIN 15



ONE–SHOT SELECTION GUIDE

100 ns

MC14528B

MC14536B

1 µs 10 µs 100 µs 1 ms 10 ms 100 ms 1 s 10 s

23 HR

MC14538B


VDD – 55 C 25 C

Characteristic SymbolVdc

Min Max Min Typ(4.)

Max MiOutput Voltage “0” Level

Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.9

9.9

14.9


(VO = 4.5 or 0.5 Vdc)

(VO

= 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3.5

7.0

11



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

– 1

– 0.

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.3

0.9

2.4

Input Current, Pin 2 or 14 Iin 15 — ± 0.05 — ± 0.00001 ±0.05 —

Input Current, Other Inputs Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 —

Input Capacitance, Pin 2 or 14 Cin — — — — 25 — —

Input Capacitance, Other Inputs

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

Q = Low, Q = High

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—

Quiescent Current, Active State

(Both) (Per Package)

Q = High, Q = Low

IDD 5.0

10

15

—

—

—

2.0

2.0

2.0

—

—

—

0.04

0.08

0.13

0.20

0.45

0.70

—

—

—

Total Supply Current at an external

load capacitance (CL) and at

external timing network (RX, CX)(5.)

IT 5.0

10

IT = (3.5 x 10 –2) RXCXf + 4CXf + 1 x 10 –5 CLf

IT = (8.0 x 10 –2) RXCXf + 9CXf + 2 x 10 –5 CLf

IT = (1.25 x 10 –1

) RXCXf + 12CXf + 3 x 10 –5

CLh I i A ( t bl it hi



external timing network (R , C ) I (1.25 x 10 ) R C f + 12C f + 3 x 10 Cwhere: IT in µA (one monostable switching on

where: CX in µF, CL in pF, RX in k ohms, and

where: f in Hz is the input frequency.


MC14538B


VDDAll Types

Characteristic SymbolVdc

Min Typ(7.)

Output Rise Time




tTLH

5.0

10

15

—

—

—

100

50

40

Output Fall Time




tTHL

5.0

10

15

—

—

—

100

50

40


A or B to Q or Q




tPLH,

tPHL

5.0

10

15

—

—

—

300

150

100

Reset to Q or Q




5.0

10

15

—

—

—

250

125

95

Input Rise and Fall Times

Reset

tr, tf 5

1015

—

— —

—

— —

B Input 5

10

15

—

—

—

300

1.2

0.4

A Input 5

10

15

No Limit

Input Pulse Width

A, B, or Reset

tWH,

tWL

5.0

1015

170

9080

85

4540

Retrigger Time trr 5.0

10

15

0

0

0

—

—

—

Output Pulse Width — Q or Q

Refer to Figures 8 and 9

CX = 0.002 µF, RX = 100 kΩ

T

5.0

10

15

198

200

202

210

212

214

CX = 0 1 µF RX = 100 kΩ 5 0 9 3 9 86



CX = 0.1 µF, RX = 100 kΩ 5.0

10

15

9.3

9.4

9.5

9.86

10

10.14

CX = 10 µF, RX = 100 kΩ 5.0

10

15

0.91

0.92

0.93

0.965

0.98

0.99

Pulse Width Match between circuits in

the same package

100

[(T1 – T2)/T1]

5.0

10

—

—

± 1.0

± 1 0

MC14538B

OPERATING CONDITIONS

External Timing Resistance RX — 5.0 —

External Timing Capacitance CX — 0 —

8. The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, alayout and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MΩ..

9. If CX > 15 µF, use discharge protection diode per Fig. 11.

Figure 1. Logic Diagram

(1/2 of DevIce Shown)

NOTE: Pins 1,

be exter

–

+

–

+

VDD VDD

P1RX

CX

2

1

(14)

(15)

4 (12)

5 (11)

3 (13)

A

B

RESET

VSS

N1

Vref1C1 C2

ENABLE

Vref2ENABLE

CONTROL

S

RESET LATCH

QR

QRRS

R

S

Q

Q

OUTPUTLATCH

500 pF

VDD

0.1 µF

CERAMIC

RX RX′

CX′VSS

CXVSS

Vin

CX /RXA

B

RESET

Q

Q CL

CL20 ns

90%

ID



A′

B′

RESET′

Q′

Q′

VSS

CL

CL

CL

10%Vin

MC14538B

INPUT CONNEC

Characteristics Rese

tPLH, tPHL, tTLH, tTHL,

T, tWH, tWL

VDD

tPLH, tPHL, tTLH, tTHL,

T, tWH, tWL

VDD

tPLH(R), tPHL(R),

tWH, tWL

PG3

Figure 4. Switching Test Waveforms

RESET

A

B

tPLH

Q

Q

50%

tWH

90%

10%

tTLH tTHL

tWL

tTHL tPHL

tTHL

90%

10%50%

T

50% 50% 50%90%

10%

tPLHtTHL tTLH

tPHL

tWL

50%90%

10%

tPHL tPHL

tTLH tTHLtPLH

50% 50% 90%

10%50%

50%

50%

50%

tTLH

E ( % )

T 25°C

Figure 3. Switching Test Circuit

*Includes capacitance of probes,

wiring, and fixture parasitic.

NOTE: Switching test waveformsfor PG1, PG2, PG3 are shown

In Figure 4.

VDD

RX RX′

VSS

CX

CX /RXA

B

RESET

A′

B′

RESET′

Q

Q

Q′

Q′CL

CX′

CL

CL

CL

VSS

PULSE

GENERATOR

PULSE

GENERATOR

PULSEGENERATOR

VSS

*CL = 50 pF



0.6

0.8

1.0

U E N C Y O F O C C U R R E N C E

2

1

0

1 P U L S E W I D T H C H A N G E

T O V A L U E A T V D D =

1 0 V (TA = 25°C

RX = 100 kΩCX = 0.1 µF

0% POINT PULSE WIDTH

VDD = 5.0 V, T = 9.8 ms

VDD = 10 V, T = 10 ms

VDD = 15 V, T = 10.2 ms

RX = 100 k

CX = 0.1 µF

MC14538B

Figure 7. Typical Total Supply Current

versus Output Duty Cycle

T O T A L S U P P L Y C U R R E N

T ( A )

µ

1000

100

10

1.0

0.10.001 0.1 1.0 10 100

OUTPUT DUTY CYCLE (%)

RX = 100 kΩ, CL = 50 pF

ONE MONOSTABLE SWITCHING ONLY

VDD = 15 V

10 V

5.0 V

FUNCTION TABL

Inputs

Reset A B

H H

H L

H L

H H

H L, H, H

H L L, H,

L X X

X X

Figure 8. Typical Error of Pulse Width

Equation versus Temperature

Figure 9. Typical Error o

Equation versus Te

– 2

– 1

0

1

2

– 60 – 40 – 20 0 20 40 60 80 100 120 140


T Y P I C A L N O R M A L I Z E D E R R O R

W I T

H R E S P E C T T O 2 5

D

D =

1 0 V ( % )

° C V A L U E A T V

RX = 100 kΩ

CX = 0.1 µF VDD = 15 V

VDD = 10 V

VDD = 5 V

– 2.0

– 1.0

0

1.0

2.0

3.0

– 3.0

– 60 – 40 – 20 0 20 40 6

TA, AMBIENT TEMPERA

RX = 100 kΩ

CX = .002 µF

VDD = 15 V

VDD = 10 V

VDD = 5.0 V

T Y P I C A L N O R M A L I Z E D E R R O R

W I T

H R E S P E C T T O 2 5

D

D =

1 0 V ( % )

° C V A L U E A T V



MC14538B

THEORY OF OPERATION

2

Figure 10. Timing Operation

Positive edge re–trigger (pulse lengthening)Positive edge trigger

1

2

3 4

1

3

4

5

RESET

A

B

CX /RX

Q

Vref 1 Vref 1 Vref 1 Vref 1Vref 2

Vref 2 Vref 2 Vref

T T T

Negative edge trigger

Positive edge trigger

Positive edge re–trigger (pulse lengthening)

TRIGGER OPERATION

The block diagram of the MC14538B is shown inFigure 1, with circuit operation following.

As shown in Figure 1 and 10, before an input trigger

occurs, the monostable is in the quiescent state with the Qoutput low, and the timing capacitor CX completely chargedto VDD. When the trigger input A goes from V SS to VDD(while inputs B and Reset are held to VDD) a valid trigger isrecognized, which turns on comparator C1 and N–channeltransistor N1 . At the same time the output latch is set. Withtransistor N1 on, the capacitor CX rapidly discharges towardVSS until Vref1 is reached. At this point the output of comparator C1 changes state and transistor N1 turns off.

Comparator C1 then turns off while at the same timeC2 Wi h i N1 ff h i

RETRIGGER OPERATION

The MC14538B is retriggered if a followed by another valid trigger breturned to the quiescent (zero) state. A

timing node voltage at pin 2 or 14 hVref 1, but has not yet reached Vref 2, in output pulse width T. When a vali

, the voltage at CX /RX will again progressing along the RC charging cuQ output will remain high until timeretrigger.

RESET OPERATION

The MC14538B may be reset durinoutput pulse In the reset mode of ope



comparator C2 turns on. With transistor N1 off, the capacitorCX begins to charge through the timing resistor, RX, towardVDD. When the voltage across CX equals Vref 2, comparatorC2 changes state, causing the output latch to reset (Q goeslow) while at the same time disabling comparator C2 . Thisends at the timing cycle with the monostable in the quiescentstate waiting for the next trigger

output pulse. In the reset mode of opeon Reset sets the reset latch and causfast charged to VDD by turning on tranvoltage on the capacitor reaches Vrefclear, and will then be ready to accepReset input is held low, any trigger ininhibited and the Q and Q outputs of th

MC14538B

the MC14538B is powered down, the capacitor voltage maydischarge from VDD through the standard protection diodesat pin 2 or 14. Current through the protection diodes should

be limited to 10 mA and therefore the discharge time of theVDD supply must not be faster than (VDD). (C)/(10 mA).For example, if VDD = 10 V and CX = 10µF, the VDD supplyshould discharge no faster than (10 V) x (10 µF)/ (10 mA)= 10 ms. This is normally not a problem since powersupplies are heavily filtered and cannot discharge at this rate.

When a more rapid decrease of VDD to zero volts occurs,the MC14538B can sustain damage. To avoid this possibilityuse an external clamping diode, DX, connected as shown in

Fig. 11. Figure 11. Use of a DiodPower Down Current

VSS

Dx

RxCx

Q

Q

RESET

Figure 12. Retriggerable

Monostables Circuitry

Figure 13. No

Monostab

CX RX

VDD

Q

Q

RESET = VDD

B = VDD

A

B

RISING–EDGE

TRIGGER

CX RX

VDD

Q

Q

RESET = VDD

B

A = VSS

FALLING–EDGE

TRIGGER

A

B

R

R

A

BFALLING–EDGE

TRIGGER

RISING–EDGE

TRIGGER


NC

NC

NC

A

B

Q

QCD

The MC14541B programmable timer consists of a 16–stage binarycounter, an integrated oscillator for use with an external capacitor andtwo resistors, an automatic power–on reset circuit, and output controllogic.

Timing is initialized by turning on power, whereupon the power–onreset is enabled and initializes the counter, within the specified VDDrange. With the power already on, an external reset pulse can beapplied. Upon release of the initial reset command, the oscillator willoscillate with a frequency determined by the external RC network. The16–stage counter divides the oscillator frequency (f osc) with the nth

stage frequency being f osc /2n.• Available Outputs 28, 210, 213 or 216

• Increments on Positive Edge Clock Transitions• Built–in Low Power RC Oscillator (± 2% accuracy over temperature

range and ± 20% supply and ± 3% over processing at < 10 kHz)

• Oscillator May Be Bypassed if External Clock Is Available (Applyexternal clock to Pin 3)

• External Master Reset Totally Independent of Automatic ResetOperation

• Operates as 2n Frequency Divider or Single Transition Timer• Q/Q Select Provides Output Logic Level Flexibility• Reset (auto or master) Disables Oscillator During Resetting to

Provide No Active Power Dissipation

• Clock Conditioning Circuit Permits Operation with Very Slow ClockRise and Fall Times

• Automatic Reset Initializes All Counters On Power Up• Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset

Supply Voltage Range = Disabled (Pin 5 = VDD)Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto ResetSupply Voltage Range = Enabled (Pin 5 = VSS)



http://onsem

A = Assem

WL or L = Wafer


Device Packag

ORDERING INF

MC14541BCP PDIP–

MC14541BD SOIC–

MC14541BDR2 SOIC–

MC14541BDT TSSOP–

PDIP–14

P SUFFI

CASE 64

SOIC–14

D SUFFI

CASE 751

TSSOP–1DT SUFF

CASE 948

SOEIAJ–

F SUFFI

CASE 96





(DC or Transient)

–0.5 to VDD + 0.5 V

Iin Input Current (DC or Transient) ± 10 (per Pin) mA

Iout Output Current (DC or Transient) ± 45 (per Pin) mA 1. For ordering information the SOIC packages plea

MC14541BDTR2 TSSOP–

MC14541BF SOEIAJ–


MC14541B

PIN ASSIGNMENT

NC = NO CONNECTION

11

12

13

14

8

9

105

4

3

2

1

7

6

MODE

NC

A

B

VDD

Q

Q/Q SEL

NC

RS

Ctc

Rtc

VSS

MR

AR


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7



(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

10

15

– 7.96

– 4.19

– 16.3

—

—

—

– 6.42

– 3.38

– 13.2

– 12.83

– 6.75

– 26.33

—

—

—

– 4

– 2

– 9


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

1.93

4.96

19.3

—

—

—

1.56

4.0

15.6

3.12

8.0

31.2

—

—

—

1.

2

10



Cin — — — — 5.0 7.5 —



Quiescent Current

(Pin 5 is High)

Auto Reset Disabled

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—

Auto Reset Quiescent Current

(Pin 5 is low)

IDDR 10

15

—

—

250

500

—

—

30

82

250

500

—

—

Supply Current (5 ) (6 ) I 5 0 I (0 4 µA/kHz) f + I

MC14541B







tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40

Propagation Delay, Clock to Q (28 Output)




tPLH

tPHL 5.0

10

15

—

—

—

3.5

1.25

0.9

Propagation Delay, Clock to Q (216 Output)


tPHL, tPLH = (0.66 ns/pF) CL + 3467 nstPHL, tPLH = (0.5 ns/pF) CL + 2475 ns

tPHL

tPLH 5.0

1015

—

— —

6.0

3.52.5


10

15

900

300

225

300

100

85

Clock Pulse Frequency (50% Duty Cycle) fcl 5.0

10

15

—

—

—

1.5

4.0

6.0

MR Pulse Width tWH(R) 5.0

10

15

900

300

225

300

100

85

Master Reset Removal Time trem 5.0

10

15

420

200

200

210

100

100


PULSE

GENERATOR

VDD

CL

Q

RS

AR

Q/Q SELECT

MODE

A

B

MR

VSS

PULSE

GENERATOR

VDD

RS

AR

Q/Q SELEC

MODE

A

B

MR

V



VSS

20 ns 20 ns

(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)

V

20 ns

90%50%

20 ns

10%RStPLH

50%

MC14541B

EXPANDED BLOCK DIAGRAM

A 12B 13

Rtc 1

Ctc 2

RS 3

5AUTO RESET

OSC

RESET

C 288–STAGE

COUNTER

RESET

POWER–ON

RESET

6

MASTER RESET

210 213 216

C 8–STAGE

COUNTER

RESET

1 OF 4

MUX

10

MODE

9

Q/Q

SELECTVDD = PIN 14

VSS = PIN 7

FREQUENCY SELECTION TABLE

A B

Number of

Counter Stages

n

Count

2n

0 0 13 8192

0 1 10 1024

1 0 8 256

1 1 16 65536

TRUTH TABLE

St

Pin 0

Auto Reset, 5 Auto Reset

Operating

Master Reset, 6 Timer Operational

Q/Q, 9 Output Initially Low

After Reset

Mode, 10 Single Cycle Mode



3TO CLOCK

CIRCUIT

INTERNAL

MC14541B

TYPICAL RC OSCILLATOR CHARACTERISTICS

Figure 4. RC Oscillator Stability

Figure 5. RC Oscillator Fr

Function of Rtc a

8.0

4.0

0

– 4.0

– 8.0

– 12

– 161251007550250 – 25 – 55


F R E Q U E N C Y D E V I A T I O N ( % )

VDD = 15 V

10 V

5.0 V

RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°CRS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C

RTC = 56 kΩ,

C = 1000 pF

100

0.1

0.2

0.5

1.0

2.0

5.0

10

20

50

1.0 k 10 k

f , O S C I L L A T O R F R E Q U E N C Y ( k H z )

RTC, RESISTANCE (OH

0.0001 0.001

C, CAPACITANCE (µ

f AS A FUNCTION

OF C

(RTC = 56 kΩ)

(RS = 120 kΩ)


With Auto Reset pin set to a “0” the counter circuit isinitialized by turning on power. Or with power already on,the counter circuit is reset when the Master Reset pin is setto a “1”. Both types of reset will result in synchronouslyresetting all counter stages independent of counter state.Auto Reset pin when set to a “1” provides a low poweroperation.

The RC oscillator as shown in Figure 3 will oscillate witha frequency determined by the external RC network i.e.,

if (1 kHz f 100 kHz)2.3 RtcCtc

1f =

and RS ≈ 2 Rtc where RS ≥ 10 kΩ

The time select inputs (A and B) provide a two–bit addressto output any one of four counter stages (28, 210, 213 and216). The 2n counts as shown in the Frequency Selection

Table represents the Q output of the Nth

stage of the counter.When A is “1”, 216 is selected for both states of B. However,

when B is “0”, normal counting is incounter stage receives its clock direc(i.e., effectively outputting 28).

The Q/Q select output control pin poutput level. When the counter is inQ/Q select pin is set to a “0” thecorrespondingly when Q/Q select pi

output is a “1”.When the mode control pin is set count is continually transmitted to mode pin “0” and after a reset conditioExpanded Block Diagram) resets, cand after 2n–1 counts the RS flip–flopoutput to change state. Hence, after aoutput will not change. Thus, a Masteapplied or a change in the mode pin le

the single cycle operation.



DIGITAL TIMER APPLICATION

Rtc

Ctc

VDD

B

1

2 13

14

When Master Reset (MR) receiveinternal counters and latch are reset. Tand remains high until the selected (v

The MC14543B BCD–to–seven segment latch/decoder/driver isdesigned for use with liquid crystal readouts, and is constructed withcomplementary MOS (CMOS) enhancement mode devices. The

circuit provides the functions of a 4–bit storage latch and an 8421BCD–to–seven segment decoder and driver. The device has thecapability to invert the logic levels of the output combination. Thephase (Ph), blanking (BI), and latch disable (LD) inputs are used toreverse the truth table phase, blank the display, and store a BCD code,respectively. For liquid crystal (LC) readouts, a square wave is appliedto the Ph input of the circuit and the electrically common backplane of the display. The outputs of the circuit are connected directly to thesegments of the LC readout. For other types of readouts, such as

light–emitting diode (LED), incandescent, gas discharge, andfluorescent readouts, connection diagrams are given on this data sheet.Applications include instrument (e.g., counter, DVM etc.) display

driver, computer/calculator display driver, cockpit display driver, andvarious clock, watch, and timer uses.

• Latch Storage of Code• Blanking Input• Readout Blanking on All Illegal Input Combinations•

Direct LED (Common Anode or Cathode) Driving Capability• Supply Voltage Range = 3.0 V to 18 V• Capable of Driving 2 Low–power TTL Loads, 1 Low–power Schottky

TTL Load or 2 HTL Loads Over the Rated Temperature Range• Pin–for–Pin Replacement for CD4056A (with Pin 7 Tied to VSS).• Chip Complexity: 207 FETs or 52 Equivalent Gates




V Input Voltage Range All Inputs 0 5 to V + 0 5 V

http://onsem

A = Assem


WW or W = Work

Device Packag

ORDERING INF

MC14543BCP PDIP–

MC14543BD SOIC–

MC14543BDR2 SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96




Iin DC Input Current per Pin ± 10 mA



500 mW


1. For ordering information the SOIC packages, pleaON Semiconductor repres


MC14543BF SOEIAJ–

MC14543B

TRUTH TABLE

Inputs Outputs

LD BI Ph* D C B A a b c d e f g Display

X 1 0 X X X X 0 0 0 0 0 0 0 Blank

1 0 0 0 0 0 0 1 1 1 1 1 1 0 0

1 0 0 0 0 0 1 0 1 1 0 0 0 0 11 0 0 0 0 1 0 1 1 0 1 1 0 1 21 0 0 0 0 1 1 1 1 1 1 0 0 1 3

1 0 0 0 1 0 0 0 1 1 0 0 1 1 41 0 0 0 1 0 1 1 0 1 1 0 1 1 51 0 0 0 1 1 0 1 0 1 1 1 1 1 61 0 0 0 1 1 1 1 1 1 0 0 0 0 7

1 0 0 1 0 0 0 1 1 1 1 1 1 1 81 0 0 1 0 0 1 1 1 1 1 0 1 1 91 0 0 1 0 1 0 0 0 0 0 0 0 0 Blank1 0 0 1 0 1 1 0 0 0 0 0 0 0 Blank

1 0 0 1 1 0 0 0 0 0 0 0 0 0 Blank1 0 0 1 1 0 1 0 0 0 0 0 0 0 Blank1 0 0 1 1 1 0 0 0 0 0 0 0 0 Blank1 0 0 1 1 1 1 0 0 0 0 0 0 0 Blank

0 0 0 X X X X ** **

† † † † Inverse of Output DisplayCombinations as aboveAbove

X = Don’t care

† = Above Combinations

* = For liquid crystal readouts, apply a square wave to Ph

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

d

e

g

f

VDD

a

b

c

D

B

C

LD

VSS

BI

PH

A



For common cathode LED readouts, select Ph = 0

For common anode LED readouts, select Ph = 1

** = Depends upon the BCD code previously applied when LD = 1

MC14543B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 0.5 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

10

15

– 3.0

– 0.64

—

– 1.6

– 4.2

—

—

—

—

—

– 2.4

– 0.51

—

– 1.3

– 3.4

– 4.2

– 0.88

– 10.1

– 2.25

– 8.8

—

—

—

—

—

–

– 0

—

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 9.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

10

15

0.64

1.6

—

4.2

—

—

—

—

0.51

1.3

—

3.4

0.88

2.25

10.1

8.8

—

—

—

—

0.

0

—

2



Quiescent Current

(Per Package) Vin = 0 or VDD,Iout = 0 µA

IDD 5.0

1015

—

— —

5.0

1020

—

— —

0.005

0.0100.015

5.0

1020

—

— —



Per Package)


buffers switching)

IT 5.0

10

15




5. Noise immunity specified for worst–case input combination.

Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V

= 2.0 V min @ VDD = 10 V

= 2.5 V min @ VDD = 15 V




IT(CL) = IT(50 pF) + 3.5 x 10 –3 (CL – 50) VDDf

where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.


MC14543B


Characteristic Symbol VDD Min Typ

Output Rise Time



tTLH

5.010

15

— —

—

10050

40

Output Fall Time


tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 12.5 ns

tTHL

5.0

10

15

—

—

—

100

50

40



tPLH

= (0.66 ns/pF) CL

+ 217 ns


tPLH

5.0

10

15

—

—

—

605

250

185



tPHL = (0.66 ns/pF) CL + 172 ns


tPHL

5.0

10

15

—

—

—

505

205

155

Setup Time tsu 5.0

10

15

350

450

500

Hold Time th 5.0

10

15

40

30

20

Latch Disable Pulse Width (Strobing Data) tWH 5.0

10

15

250

100

80

125

50

40


LOGIC DIAGRAM

VDD = PIN 16

VSS = PIN 8

B 3

A 5

BI 7



B 3

C 2

MC14543B


Characteristics


Characteristic

– 24

– 18

– 12

– 6.0

0

I O H ,

S O U R C E C U R R E N T ( m

A d c )

(VOH – VDD), SOURCE DEVICE VOLTAGE (Vdc)

– 16 – 12 – 8.0 – 4.0 0

VDD = 5.0 VdcPOHmax = 70 mWdc

VDD = 10 Vdc

VDD = 15 Vdc

VSS = 0 Vdc0

6.0

12

18

24

I O L ,

S I N K C U R R E N T ( m A d c )

(VOL – VSS), SINK DEVICE V

0 4.0 8.0

VDD = 10

VDD = 5.0 Vdc PO

Inputs BI and Ph low, and Inputs D and LD high.


(a) Inputs D, Ph, and BI low, and Inp

(b) Inputs D, Ph, and BI low, and Inp

(c) Data DCBA strobed into latches

20 ns 20 nsVDD

VSS

VOH

10% 50%90%1

2f

50% DUTY CYCLE

A, B, AND C

ANY OUTPUT

All outputs connected to respective CL loads.

20 ns 20 ns90%

10%

tPHL tPL

90% 50%

tTHL

C

g

LD

C

g

LD

20 ns

90% 50%10%

50% 50

tsu

50%



Figure 3. Dynamic Power Dissipation

Signal Waveforms

Figure 4. Dynamic Signa

VOL tWH

MC14543B


LIQUID CRYSTAL (LC) READOUT


INCANDESC

NOTE: Bipolar transistors may be added for gain (for VDD 10 V or Iout ≥ 10 mA).

GAS DISCHA

CONNECTIONS TO SEGMENTS

SQUARE WAVE

(VSS TO VDD)

COMMON

BACKPLANE

ONE OF SEVEN SEGMENTSMC14543B

OUTPUT

Ph

MC14543B

OUTPUTPh

VSS

MC14543B

OUTPUTPh

VSS

COMMON

CATHODE LED

COMMON

ANODE LED

VDD

MC14543B

OUTPUTPh

VDD

MC14543B

OUTPUTPh

VSS

a

b

cd

e

f g



VDD = PIN 16

VSS = PIN 8

DISPLAY

The MC14549B and MC14559B successive approximationregisters are 8–bit registers providing all the digital control and storagenecessary for successive approximation analog–to–digital conversionsystems. These parts differ in only one control input. The Master Reset(MR) on the MC14549B is required in the cascaded mode when more

than 8 bits are desired. The Feed Forward (FF) of the MC14559B isused for register shortening where End–of–Conversion (EOC) isrequired after less than eight cycles.

Applications for the MC14549B and MC14559B includeanalog–to–digital conversion, with serial and parallel outputs.

• Totally Synchronous Operation• All Outputs Buffered• Single Supply Operation

• Serial Output• Retriggerable• Compatible with a Variety of Digital and Analog Systems such as the

MC1408 8–Bit D/A Converter• All Control Inputs Positive–Edge Triggered• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving 2 Low–Power TTL Loads, 1 Low–Power Schottky

TTL Load or 2 HTL Loads Over the Rated Temperature Range

• Chip Complexity: 488 FETs or 122 Equivalent Gates





Iin DC Input Current, per Pin ±10 mA


per Package (Note 2 )

500 mW

http://onsem

XX = Specif

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14549BCP PDIP–

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751








MC14559BCP PDIP–


MC14549B, MC14559B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q0

Q1

Q2

Q3

VDD

SC

*

EOC

Q7

Q6

Q5

Q4

VSS

C

D

Sout

*For MC14549B Pin 10 is MR input.

For MC14559B Pin 10 is FF input.

SC SC(t–1) MR MR(t–1) Clock Action

X X X X NoneX X 1 X Reset

1 0 0 0 StartConversion

1 X 0 1 StartConversion

1 1 0 0 ContinueConversion

0 X 0 X ContinuePrevious

Operation

TRUTH TABLESMC14549B

X = Don’t Care t–1 = State at Previous Clock

SC SC(t–1) EOC Clock Action

X X X None1 0 0 Start

Conversio

X 1 0 ContinueConversio

0 0 0 ContinueConversio

0 X 1 RetainConversioResult

1 X 1 StartConversio

MC14559B



MC14549B, MC14559B


VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14

Input Voltage (3.) “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 1.2

– 0.25

– 0.62

– 1.8

—

—

—

—

– 1.0

– 0.2

– 0.5

– 1.5

– 1.7

– 0.36

– 0.9

– 3.5

—

—

—

—

– 0

– 0

– 0

–


(VOL = 0.5 Vdc) Q Outputs

(VOL = 1.5 Vdc)

IOL 5.0

10

15

1.28

3.2

8.4

—

—

—

1.02

2.6

6.8

1.76

4.5

17.6

—

—

—

0.

1

4


(VOL = 0.5 Vdc) Pin 5, 11 only

(VOL = 1.5 Vdc)

5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2

Input Current Iin 15 — ± 0.1 — ± 0.00001 ±0.1 —



(Clock = 0 V,

Other Inputs = VDD

or 0 V, Iout = 0 µA)

IDD 5.010

15

— —

—

5.010

20

— —

—

0.0050.010

0.015

5.010

20

— —

—



Per Package)


buffers switching)

IT 5.0

10

15




3. Noise immunity specified for worst–case input combination.

Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V

= 2.0 V min @ VDD = 10 V



@ DD

= 2.5 V min @ VDD = 15 V


IT(CL) = IT(50 pF) + 3.5 x 10 –3 (CL = 50) VDDf

where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.

MC14549B, MC14559B


Characteristic Symbol VDD Min Typ

Output Rise Time



tTLH

5.010

15

— —

—

18090

65

Output Fall Time


tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 9.5 ns

tTHL

5.0

10

15

—

—

—

100

50

40


Clock to Q




Clock to Sout




Clock to EOC




tPLH,

tPHL

5.0

10

15

5.0

10

15

5.0

10

15

—

—

—

—

—

—

—

—

500

210

155

750

310

220

300

130

100

SC, D, FF or MR Setup Time tsu 5.010

15

250100

80

12550

40


10

15

700

270

200

350

135

100

Pulse Width — D, SC, FF or MR tWH 5.0

10

15

500

200

160

250

100

80

Clock Rise and Fall Time tTLH,tTHL

5.010

15

— —

— —


10

15

—

—

—

1.5

3.0

4.0




MC14549B, MC14559B

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

1

fcltWH(cl)

50%

50%

tsu

tsu ts

tPLH

50%

50% 90% 1tTLH

Sout

Q7

D

SC

C

NOTE: Pin 10 = VSS

C

CL

CL

CL

CL

CL

CL

CL

CL

CL

VDD

VSS

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

EOC

Sout

C

SC

FF(MR)

D

PROGRAMMABLE

PULSE

GENERATOR

TIMING DIAGRAM

CLOCK

SCD

Q7

Q6

Q5

Q4



Q3

Q2

Q1

MC14549B, MC14559B


Both the MC14549B and MC14559B can be operated ineither the “free run” or “strobed operation” mode forconversion schemes with any number of bits. Reliablecascading and/or recirculating operation can be achieved if the End of Convert (EOC) output is used as the controllingfunction, since with EOC = 0 (and with SC = 1 forMC14549B but either 1 or 0 for MC14559B) no stable stateexists under continual clocked operation. The MC14559Bwill automatically recirculate after EOC = 1 duringexternally strobed operation, provided SC = 1.

All data and control inputs for these devices are triggeredinto the circuit on the positive edge of the clock pulse.

Operation of the various terminals is as follows:C = Clock — A positive–going transition of the Clock is

required for data on any input to be strobed into the circuit.SC = Start Convert — A conversion sequence is initiated

on the positive–going transition of the SC input onsucceeding clock cycles.

D = Data in — Data on this input (usually from acomparator in A/D applications) is also entered into thecircuit on a positive–going transition of the clock. This inputis Schmitt triggered and synchronized to allow fast responseand guaranteed quality of serial and parallel data.

MR = Master Reset (MC14549B Only) — Resets alloutput to 0 on positive–going transitions of the clock. If removed while SC = 0, the circuit will remain reset until SC= 1. This allows easy cascading of circuits.

FF = Feed Forward (MC14559B Only) — Providesregister shortening by removing unwanted bits from asystem.

For operation with less than 8 bits, tie the output following

the least significant bit of the circuit to EOC. E.g., for a 6–bit

conversion, tie Q1 to FF; the part wilthe timing diagram less two bit timeswill still operate and must be disrega

For 8–bit operation, FF is tied to VFor applications with more than 8 bu

the basic connections shown in FigureMC14559B is used to shorten the setto the least significant bit used in thEOC to provide the cascading signal,transition of serial information from MC14549B. The Serial Out (Sout) inMC14559B remains inactive one cyclwhile Sout of the MC14549B remaisecond clock cycle of its operation.

Qn = Data Outputs — After a conQ’s on succeeding cycles go high andreset dependent upon the state ofconditionally reset they remain in thecircuit is either reset or reinitiated.

EOC = End of Convert — This onegative–going transition of the clockthe MC14559B) or the conditional resettling of the digital circuitry prior to indication. Therefore either level orindicate complete conversion.

Sout = Serial Out — Transmitsfashion. Serial data occurs during the corresponding parallel data bit is conOut is inhibited on the initial periodcircuit is reset, and on the second cyclThis provides efficient operation whe

Q7 Q6 Q5 Q4 Q0 EOCFF

SC

C D Sout

MC14559B

••

*

FROM A/D

COMPARATOR

Q7 Q6 Q5MR

SC

C D Sout

MC14549B

Q4 Q3 Q2 Q1 Q0 EOC

EXTERNAL

CLOCK1/4 MC14001

SE

(C

U

13



Q7 Q6 Q5 Q4 Q0 EOC

NCMSB

TO D/A AND PARALLEL DATA

••

**

Q7 Q6 Q5

LSB

Q4 Q3 Q2 Q1 Q0 EOC

MC14549B, MC14559B


Externally Controlled 6–Bit ADC (Figure 2)

Several features are shown in this application:

• Shortening of the register to six bits by feeding theseventh output bit into the FF input.

• Continuous conversion, if a continuous signal is appliedto SC.

• Externally controlled updating (the start pulse must beshorter than the conversion cycle).

• The EOC output indicating that the parallel data are validand that the serial output is complete.

Continuously Cycling 8–Bit ADC (Figure 3)

This ADC is running continuously because the EOCsignal is fed back to the SC input, immediately initiating anew cycle on the next clock pulse.

Continuously Cycling 12–Bit ADC

Because each successive approxim

has a capability of handling only anmust be cascaded to make an ADC wit

When it is necessary to cascade twSAR must have a stable resettable stawaiting a subsequent start signal. Hmust not have a stable resettable sbecause during switch–on or due to ofirst stage has entered a reset state,remain in a stable non–functional con

This 12–bit ADC is continuously rwell as the parallel outputs are updclock pulse. The EOC pulse indicates12–bit conversion cycle, the end of tand the validity of the parallel data ou

Figure 2. Externally Controlled 6–Bit ADC

TO DAC

SCC

Sout

Q7 Q6 Q5

MC14559B


SC

C

Sout

Q7 Q6 Q5

MC14559B




TO DAC

Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EOCFF

MC14549B, MC14559B

Q7 Q6 Q5MRSC

C

SoutMC14549B

Q4 Q3 Q2 Q1 Q0 EOC

TO DAC

Q7 Q6 Q5

SC

C Sout

MC14559B

Q4 Q3 Q2 Q1 Q0 EOC

TO DAC

FF

EOC

Figure 4. Continuously Cycling 12–Bit ADC

Externally Controlled 12–Bit ADC (Figure 5)

In this circuit the external pulse starts the first SAR andsimultaneously resets the cascaded second SAR. When Q4of the first SAR goes high, the second SAR startsconversion, and the first one stops conversion. EOCindicates that the parallel data are valid and that the serialoutput is complete. Updating the output data is started withevery external control pulse.

Additional Motorola Parts for Succ

Approximation ADC

Monolithic digital–to–analog

MC1408/1508 converter has eight–available with 6, 7, and 8–amplifier–comparator block —

contains a high speed operational ampcomparator with adjustable window.

With these two linear parts it is SA–ADCs with an accuracy of up to register one MC14549B or one MC1CMOS block will be necessary tofrequency.

Additional information on succeADC is found in Motorola Applicatio

Q7 Q6 Q5MR

SCC

SoutMC14549B

Q4 Q3 Q2 Q1 Q0 EOC

S t

TO DAC

Q7 Q6 Q5

SCC Sout

MC14559B

Q4 Q3 Q2 Q1 Q0 EOC

TO DAC

FF

EOC



Figure 5. Externally Controlled 12–Bit ADC

SoutEOC

The MC14551B is a digitally–controlled analog switch. This deviceimplements a 4PDT solid state switch with low ON impedance andvery low OFF Leakage current. Control of analog signals up to thecomplete supply voltage range can be achieved.

• Triple Diode Protection on All Control Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V

Note: VEE must be VSS

• Linearized Transfer Characteristics• Low Noise — 12 nV√Cycle, f ≥ 1.0 kHz typical• For Low RON, Use The HC4051, HC4052, or HC4053 High–Speed

CMOS Devices• Switch Function is Break Before Make

MAXIMUM RATINGS (2.)


VDD DC Supply Voltage Range

(Referenced to VEE, VSS ≥ VEE)

– 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage (DC orTransient) (Referenced to VSS for

Control Input & VEE for Switch I/O)

– 0.5 to VDD + 0.5 V

Iin Input Current (DC or Transient),

per Control Pin

± 10 mA

Isw Switch Through Current ± 25 mA

PD Power Dissipation, per Package (3.) 500 mW

TA Ambient Temperature Range – 55 to + 125 C

Tstg Storage Temperature Range – 65 to + 150 C

TL Lead Temperature


260 C

2 M i R ti th l b d hi h d t th d i

Device Packag

ORDERING INF

MC14551BCP PDIP–1

MC14551BD SOIC–1

http://onsem

MC14551BDR2 SOIC–1

PDIP–1

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 75

A = Asse

WL or L = Wafe

YY or Y = Year

WW or W = Work

SOEIAJ–

F SUFFI

CASE 96





MC14551BF SOEIAJ–


MC14551B

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Z1

Z

W

W0

VDD

CONTROL

Y1

Z0

X

X1

X0

W1

VSS

VEE

Y0

Y

PIN ASSIGNMENT

VDD = Pin 16

VSS = Pin 8VEE = Pin 7

NOTE: Control Input referenced to VSS, Analog Inputs and

Outputs reference to VEE. VEE must be VSS.

Control ON

0 W0 X0 Y0 Z0

1 W1 X1 Y1 Z1

12

11

106

3

2

1

15

9

13

5

4

14

SWITCHES

IN/OUT

COMMONS

OUT/IN

CONTROL

W0

W1

X0

X1

Y0Y1

Z0

Z1

W

X

Y

Z



MC14551B


– 55 C 25 C




Range

VDD — VDD – 3.0 ≥ VSS ≥

VEE

3.0 18 3.0 — 18


Package

IDD 5.0

10

15

Control Inputs: Vin =

VSS or VDD,

Switch I/O: VEE VI/O

VDD, and ∆Vswitch

500 mV (5.)

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20


(Dynamic Plus

Quiescent, Per Package)

ID(AV) 5.0

10

15

TA = 25 C only (The

channel component,


not included.)

(0.07 µA/kHz) f + Typical (0.20 µA/kHz) f +

(0.36 µA/kHz) f +

CONTROL INPUT (Voltages Referenced to VSS)


10

15

Ron = per spec,

Ioff = per spec

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0


10

15

Ron = per spec,

Ioff = per spec

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—



SWITCHES IN/OUT AND COMMONS OUT/IN — W, X, Y, Z (Voltages Referenced to VEE)

Recommended Peak–to–

Peak Voltage Into or Out

of the Switch



Dynamic Voltage Acrossthe Switch (5.) (Figure 3)




10

15


Vin = VIL or VIH

(Control), and Vin =

0 to VDD (Switch)

—

—

800

400

220

—

—

—

250

120

80

1050

500

280


Any Two Channels

in the Same Package

∆Ron 5.0

10

15

—

—

—

70

50

45

—

—

—

25

10

10

70

50

45


Current (Figure 8)



Channel or Any One

— ± 100 — ± 0.05 ± 100



Channel

Capacitance, Switch I/O CI/O — Switch Off — — — 10 —

Capacitance, Common O/I CO/I — — — — 17 —

MC14551B

ELECTRICAL CHARACTERISTICS (CL = 50 pF, TA = 25 C, VEE VSS)


VDD – VEE

Vdc Min Typ (6.)

Propagation Delay TimesSwitch Input to Switch Output (RL = 10 kΩ)




tPLH, tPHL

5.0

10

15

—

—

—

35

15

12

Control Input to Output (RL = 10 kΩ)

VEE = VSS (Figure 4)

tPLH, tPHL

5.0

10

15

—

—

—

350

140

100

Second Harmonic Distortion

RL = 10 kΩ, f = 1 kHz, Vin = 5 Vp–p

— 10 — 0.07

Bandwidth (Figure 5)

RL = 1 kΩ, Vin = 1/2 (VDD – VEE) p–p,

20 Log (Vout /Vin) = – 3 dB, CL = 50 pF

BW 10 — 17

Off Channel Feedthrough Attenuation, Figure 5


fin = 55 MHz

— 10 — – 50

Channel Separation (Figure 6)


fin = 3 MHz

— 10 — – 50

Crosstalk, Control Input to Common O/I, Figure 7

R1 = 1 kΩ, RL = 10 kΩ,

Control tr = tf = 20 ns

— 10 — 75




MC14551B

Figure 1. Switch Circuit Schematic

IN/OUT OUT/I

VDD VDD VDD

VEE

VDD

VEE

LEVEL

CONVERTED

CONTROLIN/OUT OUT/IN

CONTROL

CONTROL 9

W0 15

W1 1

X0 2

X1 3

Y0 6

Y1 10

Z0 11

Z1 12

8 7

16 VDD

VEE

14 W

4 X

5 Y

13 Z

CONTROLLEVEL

CONVERTER

VSS



Figure 2. MC14551B Functional Diagram

MC14551B

TEST CIRCUITS

Figure 3. ∆V Across Switch Figure 4. Propagation De

Control to Outp

CONTROL

SECTION

OF IC

SOURCE

VLOAD

ON SWITCH

PULSE

GENERATOR CONTROL

VDD



Figure 6. Channel Se

(Adjacent Channels Used

CONTROL Vout

CL = 50 pFRL

Vin

CONTROL

OFF

ON

VinVDD – VEE

2

Figure 7. Crosstalk, Control Inputto Common O/I

Figure 8. Off Channel

CONTROL Vout

CL = 50 pFRL

R1

CONTROL

SECTION

OF IC

OFF CHA

OTHE

CHAN

Control input used to turn ON or OFF


VDD – VEE

2

V



VDD

KEITHLEY 160

DIGITAL

MULTIMETER

MC14551B


Figure 10. VDD @ 7.5 V, VEE @ – 7.5 V Figure 11. VDD @ 5.0 V,

350

300

250

200

150

100

50

0 – 8.0 – 10 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10


R O N ,


TA = 125°C

– 55°C

350

300

250

200

150

100

50

0 – 8.0 – 10 – 6.0 – 4.0 – 2.0 0 2


R O N ,


25°C

700

600

500

400

300

200

100

0 – 8.0 – 10 – 6.0 – 4.0 – 2.0 0 2.0 4.0 6.0 8.0 10


R O N ,


TA = 125°C

– 55°C

25°C

350

300

250

200

150

100

50

0 – 8.0 – 10 – 6.0 – 4.0 – 2.0 0 2


R O N ,


TA = 25°C

VD

Figure 12. VDD @ 2.5 V, VEE @ – 2.5 V Figure 13. Comparison at 25



MC14551B


Figure A illustrates use of the on–chip level converterdetailed in Figure 2. The 0–to–5 volt Digital Control signal

is used to directly control a 9 Vp–p analog signal.The digital control logic levels are determined by VDD

and VSS. The VDD voltage is the logic high voltage; the VSSvoltage is logic low. For the example, VDD = + 5 V = logichigh at the control inputs; VSS = GND = 0 V = logic low.

The maximum analog signal level is determined by VDDand VEE. The VDD voltage determines the maximumrecommended peak above VSS. The VEE voltagedetermines the maximum swing below VSS. For the

example, VDD – VSS = 5 volt maximum swing above VSS;VSS – VEE = 5 volt maximum swing below VSS. Theexample shows a ± 4.5 volt signal which allows a 1/2 volt

margin at each peak. If voltage transiebelow VEE are anticipated on the ana

diodes (Dx) are recommended as shodiodes should be small signal typemaximum anticipated current surges

The absolute maximum potentiaVDD and VEE is 18.0 volts. Most parup to 15 volts which is the recodifference between VDD and VEE.

Balanced supplies are not requiredbe greater than or equal to VEE. F

+ 10 volts, VSS = + 5 volts, and VEE =See the table below.


EXTERNAL

CMOS

DIGITAL

CIRCUITRY

9 Vp–p

ANALOG SIGNAL


CONTROL SIGNAL

VDD VSS VEE

SWITCH

I/O COMMON

O/I

CONTROL

MC14551B

– 5 V+5 V

9 Vp–p

ANALOG SIGNAL

VDD VDD

VEE VEE

Dx

Dx

Dx

Dx

SWITCH

I/O

COMMON

O/I

Figure B. External Schottky or Germanium Clipping Diodes

+5 V



POSSIBLE SUPPLY CONNECTIONS

V V VControl Inputs

Logic High/Logic Low Maximum Analog Signal

The MC14553B 3–digit BCD counter consists of 3 negative edgetriggered BCD counters that are cascaded synchronously. A quad latchat the output of each counter permits storage of any given count. Theinformation is then time division multiplexed, providing one BCDnumber or digit at a time. Digit select outputs provide display control.All outputs are TTL compatible.

An on–chip oscillator provides the low–frequency scanning clock

which drives the multiplexer output selector.This device is used in instrumentation counters, clock displays,digital panel meters, and as a building block for general logicapplications.

• TTL Compatible Outputs• On–Chip Oscillator• Cascadable• Clock Disable Input

• Pulse Shaping Permits Very Slow Rise Times on Input Clock• Output Latches• Master Reset





(DC or Transient)

–0.5 to VDD + 0.5 V

Iin Input Current


±10 mA

Iout Output Current


+20 mA



500 mW



TL Lead Temperature

( S d S ld i )

260 °C

http://onsem

A = Assem

WL or L = Wafer


Device Packag

ORDERING INF

MC14553BCP PDIP–

MC14553BDW SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751





MC14553B

BLOCK DIAGRAM

12

10

11

13

9

7

6

5

14

2

1

15

VDD = PIN 16

VSS = PIN 8

4 3

CLOCK

LE

DIS

MR

Q0

Q1

Q2

Q3

O.F.

DS1

DS2

DS3

CIA CIB

TRUTH TABLE

Inputs

Master

Reset Clock Disable LE Outputs

0 0 0 No Change

0 0 0 Advance

0 X 1 X No Change

0 1 0 Advance

0 1 0 No Change

0 0 X X No Change

0 X X Latched

0 X X 1 Latched

1 X X 0 Q0 = Q1 = Q2 = Q3 = 0

X = Don’t Care



MC14553B


VDD – 55 C 25 C



VOL 5.010

15

— —

—

0.050.05

0.05

— —

—

00

0

0.050.05

0.05

— —

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO

= 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1


(VOH = 4.6 Vdc) Source —

(VOH = 9.5 Vdc) Pin 3

(VOH = 13.5 Vdc)

IOH

5.0

10

15

– 0.25

– 0.62

– 1.8

—

—

—

– 0.2

– 0.5

– 1.5

– 0.36

– 0.9

– 3.5

—

—

—

0.

0.

1

(VOH = 4.6 Vdc) Source —

(VOH = 9.5 Vdc) Other

(VOH = 13.5 Vdc) Outputs

5.0

10

15

– 0.64

– 1.6

– 4.2

—

—

—

– 0.51

– 1.3

– 3.4

– 0.88

– 2.25

– 8.8

—

—

—

– 0

– 0

– 2

(VOL = 0.4 Vdc) Sink —

(VOL = 0.5 Vdc) Pin 3

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.5

1.1

1.8

—

—

—

0.4

0.9

1.5

0.88

2.25

8.8

—

—

—

0.

0.

1.

(VOL = 0.4 Vdc) Sink — Other

(VOL = 0.5 Vdc) Outputs

(VOL = 1.5 Vdc)

5.0

10

15

3.0

6.0

18

—

—

—

2.5

5.0

15

4.0

8.0

20

—

—

—

1

3

1


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

MR = VDD

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.010

0.020

0.030

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk



T( L) T( p ) ( L )


MC14553B


Characteristic Figure Symbol VDD Min Typ (7.)


tTLH, tTHL = (1.5 ns/pF) CL + 25 nstTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns


2a tTLH,

tTHL 5.010

15

— —

—

10050

40

Clock to BCD Out 2a tPLH,

tPHL

5.0

10

15

—

—

—

900

500

200

Clock to Overflow 2a tPHL 5.0

10

15

—

—

—

600

400

200

Reset to BCD Out 2b tPHL

5.0

10

15

—

—

—

900

500

300

Clock to Latch Enable Setup Time

Master Reset to Latch Enable Setup Time

2b tsu 5.0

10

15

600

400

200

300

200

100

Removal Time

Latch Enable to Clock

2b trem 5.0

10

15

– 80

– 10

0

– 200

– 70

– 50

Clock Pulse Width 2a tWH(cl) 5.0

10

15

550

200

150

275

100

75

Reset Pulse Width 2b tWH(R) 5.0

10

15

1200

600

450

600

300

225

Reset Removal Time — trem 5.0

10

15

– 80

0

20

– 180

– 50

– 30

Input Clock Frequency 2a fcl 5.0

1015

—

— —

1.5

5.07.0

Input Clock Rise Time 2b tTLH 5.0

10

15

No

Limit

Disable, MR, Latch Enable

Rise and Fall Times

— tTLH,

tTHL

5.0

10

15

—

—

—

—

—

—

Scan Oscillator Frequency

(C1 measured in µF)

1 fosc 5.0

1015

—

— —

1.5/C1

4.2/C17.0/C1




MC14553B

Figure 1. 3–Digit Counter Timing Diagram (Reference Figure 3)

9 9 2

9 9 1

9 9 0

9 0 1

9 0 0

8 9 9

1 0 1

1 0 0

9 9

9 8

9 7

9 6

9 5

9 4

9 3

9 2

9 1

9 0

8 9

8 8

8 7

8 6

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

9 8 7 6 5 4 3 2 1

UNITS CLOCK

UNITS Q0

UNITS Q1

UNITS Q2

UNITS Q3

TENS CLOCK

TENS Q0

TENS Q3

HUNDREDS

CLOCK

HUNDREDS Q0

HUNDREDS Q3

DISABLE

OVERFLOW

MASTERRESET

SCAN

OSCILLATOR

DIGIT SELECT 1

DIGIT SELECT 2

DIGIT SELECT 3

UP AT 80 UP

UP AT 800(DISABLES CLOCK WHEN HIGH)

UNITS

TENS

HUNDREDS

PULSEGENERATOR

(a)16 VDD

Q3

Q2

Q1

Q0

O.F.

DS1

DS2

DS3

8 VSS

C

LE

DIS

MR

CL

CL

CL

CL

CL

GENERATOR

1

(b)VDD

Q3C

20 ns20 ns

90%10%

tPLHtPHL

tTHLtTLH

10% 90% 50%

9 9 9

tTLH

50%

OVERFLOW

BCD OUT

CLOCK

90%

10%

tremtsu

CLOCK



1 Q2

Q1

Q0LE C

CL

CL

GENERATOR50%LATCH

ENABLE

MC14553B


The MC14553B three–digit counter, shown in Figure 3,consists of three negative edge–triggered BCD counters

which are cascaded in a synchronous fashion. A quad latchat the output of each of the three BCD counters permitsstorage of any given count. The three sets of BCD outputs(active high), after going through the latches, are timedivision multiplexed, providing one BCD number or digit ata time. Digit select outputs (active low) are provided fordisplay control. All outputs are TTL compatible.

An on–chip oscillator provides the low frequencyscanning clock which drives the multiplexer output selector.

The frequency of the oscillator can be controlled externallyby a capacitor between pins 3 and 4, or it can be overriddenand driven with an external clock at pin 4. Multiple devicescan be cascaded using the overflow output, which providesone pulse for every 1000 counts.

The Master Reset input, when takethree BCD counters and the multipl

While Master Reset is high the digitone; but all three digit select outputs adisplay life, and the scan oscillator is iinput, when high, prevents the input clcounters, while still retaining the last ccircuit at the clock input permits theoperating on input pulses with veInformation present in the counters goes high, will be stored in the latche

while the latch input is high, indepeInformation can be recovered fromcounters have been reset if Latch during the entire reset cycle.

PULSE

SHAPER

CLOCK12

11DISABLE

(ACTIVEHIGH)

C

R

Q0

Q1

Q2

Q3÷ 10

UNITS

C

R

Q0

Q1

Q2

Q3÷ 10

TENS

C

R

Q0

Q1

Q2

Q3÷ 10

10LATCH ENABLE

QUAD

LATCH

QUAD

LATCH

QUAD

LATCH

R

R

SCAN

OSCILLATOR

SCANNER

PU

GENEC1

4

3

C1A

C1B

MULTIPLEXER

9

7

6

5

Q0

Q1

Q2

Q3



Q3÷ 10

HUNDREDS

MC14553B

Figure 4 Six Digit Display

V D D

S T R O B E

R E S E T

C L O C K

I N P U T

1 0

1 3

5

6

7

9

1 5

1

2

1 4 3 4

1 2 1 1

C L K

D I S Q

3

Q 2

Q 1

Q 0

D S 3 D S 2

D S 1

C 1 A

C 1 B

O . F .

µ 0 . 0

0 1

F

5 3 2 4 6 1 7 A B C D P

h L D

B I

a b c d e f g 9 1

0 1 1

1 2

1 3

1 5

1 4

M C 1 4 5 4 3 B

L S D

V D D

D I S P

L A Y S A R E L O W

C U R R E N T L E D

M S D

V D D

5 3 2 4 6 1 7 A B C D P

h L D

B I

a b c d e f g

9 1 0

1 1

1 2

1 3

1 5

1 4

M C 1 4 5 4 3 B

1 0

1 3

5

6

7

9

1 5

1

2

1 4 3 4

1 2 1

1

C L K

D I S Q

3

Q 2

Q 1

Q 0

D S 3 D S 2 D S 1

C 1 A

C 1 B

O . F .

M C 1 4 5 5 3 B

M C 1 4 5 5 3 B

L E

M R

L E

M R



Figure 4. Six–Digit Display

The MC14555B and MC14556B are constructed withcomplementary MOS (CMOS) enhancement mode devices. EachDecoder/Demultiplexer has two select inputs (A and B), an active lowEnable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,Q3). The MC14555B has the selected output go to the “high” state,and the MC14556B has the selected output go to the “low” state.Expanded decoding such as binary–to–hexadecimal (1–of–16), etc.,can be achieved by using other MC14555B or MC14556B devices.

Applications include code conversion, address decoding, memoryselection control, and demultiplexing (using the Enable input as a datainput) in digital data transmission systems.

• Diode Protection on All Inputs• Active High or Active Low Outputs• Expandable

• Supply Voltage Range = 3.0 Vdc to 18 Vdc• All Outputs Buffered• Capable of Driving Two Low–Power TTL Loads or One Low–Power






(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C

2 Maximum Ratings are those values beyond which damage to the device

http://onsem

X = Specif

A = Assem


WW or W = Work

Device Packag

ORDERING INF

MC14555BCP PDIP–

MC14555BD SOIC–

MC14555BDR2 SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96


MC14555BF SOEIAJ–




3. Temperature Derating:MC14556BCP PDIP–

MC14555B, MC14556B

PIN ASSIGNMENTS

13

14

1516

9

10

11

125

4

3

21

8

7

6

Q0B

BB

AB

EB

VDD

Q3B

Q2B

Q1B

Q0A

BA

AA

EA

VSS

Q3A

Q2A

Q1A

13

14

1516

9

10

11

125

4

3

21

8

7

6

Q0B

BB

AB

EB

VDD

Q3B

Q2B

Q1B

Q0A

BA

AA

EA

VSS

Q3A

Q2A

Q1A

MC14555B MC14556B

TRUTH TABLE

Inputs Outputs

Enable Select MC14555B MC14556B

E B A Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

0 0 0 0 0 0 1 1 1 1 00 0 1 0 0 1 0 1 1 0 1

0 1 0 0 1 0 0 1 0 1 1

0 1 1 1 0 0 0 0 1 1 1

1 X X 0 0 0 0 1 1 1 1

X = Don’t Care

BLOCK DIAGRAM

2 4

MC14555B MC14556B

3

1

14

13

15

5

6

7

1211

10

9

2 4

3

1

14

13

15

5

6

7

1211

10

9

VDD = PIN 16

VSS = PIN 8

A

B

E

Q0

Q1

Q2

Q3

A

B

E

Q0

Q1

Q2

Q3

A

B

E

Q0Q1

Q2

Q3

A

B

E

Q0Q1

Q2

Q3



MC14555B, MC14556B


VDD – 55 C 25 C



VOL 5.010

15

— —

—

0.050.05

0.05

— —

—

00

0

0.050.05

0.05

— —

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2

(VOL = 0.4 Vdc) Sink(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.010

15

0.641.6

4.2

— —

—

0.511.3

3.4

0.882.25

8.8

— —

—

0.0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk




MC14555B, MC14556B




tTLH

, tTHL

= (1.5 ns/pF) CL

+ 25 ns



tTLH,

tTHL

5.0

10

15

—

—

—

100

50

40

Propagation Delay Time — A, B to Output




tPLH,

tPHL 5.0

10

15

—

—

—

220

95

70

Propagation Delay Time — E to Output




tPLH,

tPHL 5.0

10

15

—

—

—

200

85


Figure 1. Dynamic Power Dissipation Signal Waveforms Figure 2. Dynamic S

All 8 outputs connect to respective CL loads.


INPUT E LOW

20 ns 20 ns

90%50%

10%2f1

VDD

VSS

VDD

VSS

VOH

VOL

A INPUTS(50% DUTY CYCLE)

B INPUTS

(50% DUTY CYCLE)

OUTPUT Q1

20 ns

90%

50%10%

90%50%10%

90%50%10%

tPHL

tTHLtPLH

tTLH

INPUT A HIGH

INPUT B

OUTPUT Q3

MC14556B

OUTPUT Q3

MC14555B

LOGIC DIAGRAM

(1/2 of Dual)

*

*

*

Q0

Q1

B

A



* Q2

The MC14557B is a static clocked serial shift register whose lengthmay be programmed to be any number of bits between 1 and 64. Thenumber of bits selected is equal to the sum of the subscripts of theenabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plusone. Serial data may be selected from the A or B data inputs with theA/B select input. This feature is useful for recirculation purposes. A

Clock Enable (CE) input is provided to allow gating of the clock ornegative edge clocking capability.

The device can be effectively used for variable digital delay lines orsimply to implement odd length shift registers.

• 1–64 Bit Programmable Length• Q and Q Serial Buffered Outputs• Asynchronous Master Reset• All Inputs Buffered

• No Limit On Clock Rise and Fall Times• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or one Low–power






(DC or Transient)

–0.5 to VDD + 0.5 V



±10 mA



500 mW



TL Lead Temperature


260 °C


http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14557BCP PDIP–

MC14557BDW SOIC–

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751

MC14557BDWR2 SOIC

SOEIAJ–1

F SUFFIX

CASE 96



may occur.3 Temperature Derating:


MC14557B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

L32

L16

L8

L4

VDD

A/B SEL

Q

Q

CLOCK

RESET

L1

L2

VSS

A

B

CE

BLOCK DIAGRAM

TRUTH TABLE

Inputs Output

Rst A/B Clock CE Q

0 0 0 B

0 1 0 A

0 0 1 B

0 1 1 A

1 X X X 0

Q is the output of the first selected shift

register stage.

X = Don’t Care

121314

115

2976543

11

10

RESETCLOCKCEBAA/B SELECTL1L2L4L8L16

L32

Q

Q

VDD = PIN 16

VSS = PIN 8

LENGTH SELECT TRUTH TABLEL32 L16 L8 L4 L2 L1 Register Length

0 0 0 0 0 0 1 Bit

0 0 0 0 0 1 2 Bitss

0 0 0 1 0 0

5 Bits



0 0 0 1 0 1 6 Bits

MC14557B


VDD – 55 C 25 C



VOL 5.010

15

— —

—

0.050.05

0.05

— —

—

00

0

0.050.05

0.05

— —

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 1.5 Vdc)

IOL 5.010

15

0.641.6

4.2

— —

—

0.511.3

3.4

0.882.25

8.8

— —

—

0.0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.010

0.020

0.030

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk




MC14557B



Rise and Fall Time, Q or Q Output



tTLH,

tTHL 5

1015

—

— —

100

5040

Propagation Delay, Clock or CE to Q or Q




tPLH,

tPHL 5

10

15

—

—

—

300

130

90

Propagation Delay, Reset to Q or Q




tPLH,

tPHL 5

10

15

—

—

—

300

130

95

Pulse Width, Clock tWH(cl) 510

15

200100

75

9545

35

Pulse Width, Reset tWH(rst) 5

10

15

300

140

100

150

70

50

Clock Frequency (50% Duty Cycle) fcl 5

10

15

—

—

—

3.0

7.5

13.0

Setup Time, A or B to Clock or CE

Worst case condition: L1 = L2 = L4 = L8 =L16 = L32 = VSS (Register Length = 1)

tsu

510

15

700290

145

350130

85

Best case condition: L32 = VDD, L1 through L16 =

Don’t Care (Any register length from 33 to 64)

5

10

15

400

165

60

45

5

0

Hold Time, Clock or CE to A or B

Best case condition: L1 = L2 = L4 = L8 = L16 =

L32 = VSS (Register Length = 1)

th5

10

15

200

100

10

– 150

– 60

– 50

Worst case condition: L32 = VDD, L1 through L16 =Don’t Care (Any register length from 33 to 64)

510

15

400185

85

5025

22

Rise and Fall Time, Clock tr,

tf

5

10

15

No Limit

Rise and Fall Time, Reset or CE tr,

tf

5

10

15

—

—

—

—

—

—

Removal Time, Reset to Clock or CE trem 5

1015

160

8070

80

4035




MC14557B

TIMING DIAGRAM

1–bit length:

CE = 0

A/B = 1

L1 = L2 = L4 = L8 = L16 = L32 = 0

PWR

50%

tWH(cl)

th

50%

tsu

trem

50%

tTLH tTHL

tPHLtPHLtPLH

90%50%

10%

A INPUT

CLOCK

RESET

Q

1/fcl



MC14557B

LOGIC DIAGRAM

C

R

3 2 B I T

1 2 L 3 2

C

R

2 B I T

1 L 2

2 L 1 C

R

1 B I T

C

R

1 6 B I T

1 3

L 1 6

1 4

L 8 C

R

1 B I T

C

R

8 B I T

1 0

1 1

Q Q 1 5

L 4 C

R

4 B I T

V D

D =

P I N 1 6

V S S =

P I N 8



The MC14562B is a 128–bit static shift register constructed withMOS P–channel and N–channel enhancement mode devices in asingle monolithic structure. Data is clocked in and out of the shiftregister on the positive edge of the clock input. Data outputs areavailable every 16 bits, from 16 through bit 128. This complementaryMOS shift register is primarily used where low power dissipation

and/or high noise immunity is desired.• Diode Protection on All Inputs• Fully Static Operation• Cascadable to Provide Longer Shift Register Lengths• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power






(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C


may occur.2. Temperature Derating:






http://onsem

A = Assem


WW or W = Work

Device Packag

ORDERING INF

MC14562BCP PDIP–

PDIP–14

P SUFFI

CASE 64



g p p p p , in out

t th V (V V ) V

MC14562B

PIN ASSIGNMENT

11

1213

14

8

9

105

4

32

1

7

6

Q16

NC

DATAQ32

VDD

Q80

Q48

NC

Q128Q96

Q64

VSS

Q112

CLOCK

NC = NO CONNECTION

BLOCK DIAGRAM

10

13

9

1

82

6

3Q128

Q112

Q96Q80

Q64

Q48

Q32

Q16

12

5

DATA

CLOCK

VDD = PIN 14

VSS = PIN 7

Pins 4 and 11

not used.

LOGIC DIAGRAM

1 2 3 16 17 32 33 48 49

CLOCK 5

DATA IN 12

65 80 81 96

DC

Q

97

DC

Q

112

DC

Q

113

DC

Q

128

DC

Q DC

Q DC

Q DC

Q

DC

Q DC

Q DC

Q DC

QDC

Q DC

Q DC

Q DC

Q DC

Q



MC14562B


VDD – 55 C 25 C



VOL 5.010

15

— —

—

0.050.05

0.05

— —

—

00

0

0.050.05

0.05

— —

—

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 05 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 1.5 Vdc)

IOL 5.010

15

0.641.6

4.2

— —

—

0.511.3

3.4

0.882.25

8.8

— —

—

0.0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.010

0.020

0.030

5.0

10

20

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15





IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT

is in µA (per package), CL

in pF, V = (VDD

– VSS

) in volts, f in kHz is input frequency, and k = 0.004.



MC14562B






tTLH,

tTHL 5.0

1015

—

— —

100

5040


Clock to Q




tPLH,

tPHL

5.0

10

15

—

—

—

600

250

170

Clock Pulse Width

(50% Duty Cycle)

tWH 5.0

10

15

600

220

150

300

110

75


10

15

—

—

—

1.9

5.6

8.0

Data to Clock Setup Time tsu(1) 5.0

10

15

– 20

– 10

0

– 170

– 64

– 60

tsu(0) 5.0

10

15

– 20

– 10

0

– 91

– 58

– 48

Data to Clock Hold Time th(1) 5.0

10

15

350

165

155

263

109

100

th(0) 5.0

10

15

350

200

140

267

140

93

Clock Input Rise and Fall Times tr, tf 5.0

10

15

—

—

—

—

—

—




MC14562B

Figure 1. Power Dissipation Test Circuit and Waveforms

VDD

DATA

CLOCK

Q128

Q112

Q96

Q80

Q64Q48

Q32

Q16

VSS7

ID 500 µF

CL CL CL CL CL CL CL CL

foCLOCK

DATA

(f = 1/2 fo)

V

V

V

V



MC14562B

TIMING DIAGRAM

PULSE 1PIN

NO.’S

CLOCK 5

DATA IN 12

Q16 10

Q32 13

Q28 3

PULSE 16 PULSE 32 PULSE 1

AC TEST WAVEFORMS

CLOCK

DATA IN

Q16

CLOCK

DATA IN

Q16

PULSE 1 PULSE 2 PULSE 16 PULSE 1

50% 50% 50%90%

10%50%

tWH

tWL

trtf

50% 50%

tsu(0)

th(0)

50% 1

tPHL tTHL

PULSE 1 PULSE 2 PULSE 16 PULSE 1

50% 50% 50%

tWH

tWL

50%

50% 50%

tsu(1)th(1)

50%

tTHLtPLH



The MC14569B is a programmable divide–by–N dual 4–bit binaryor BCD down counter constructed with MOS P–channel andN–channel enhancement mode devices (complementary MOS) in amonolithic structure.

This device has been designed for use with the MC14568B phasecomparator/counter in frequency synthesizers, phase–locked loops,and other frequency division applications requiring low powerdissipation and/or high noise immunity.

• Speed–up Circuitry for Zero Detection• Each 4–Bit Counter Can Divide Independently in BCD or Binary

Mode• Can be Cascaded With MC14526B for

Frequency Synthesizer Applications

• All Outputs are Buffered• Schmitt Triggered Clock Conditioning





(DC or Transient)

–0.5 to VDD + 0.5 V



±10 mA



500 mW


Tstg

Storage Temperature Range –65 to +150 °C

TL Lead Temperature


260 °C



http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14569BCP PDIP–

MC14569BDT TSSOP–

PDIP–16

P SUFFI

CASE 64

SOIC–16

DW SUFF

CASE 751

MC14569BDW SOIC–

TSSOP–1DT SUFFI

CASE 948



MC14569B

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

P5

P6

P7

Q

VDD

CLOCK

CTL2

P4

P1

P0

CTL1

ZERODETECT

VSS

CASCADEFEEDBACK

P3

P2

PIN ASSIGNMENT

BLOCK DIAGRAM

CTL = Low for Binary Count

CTL = High for BCD Count

CASCADEFEEDBACK

CLOCK9

7

V

CLOCK

LOAD

ZERO DETECT ENCODER

BINARY/BCD

COUNTER #1

BINARY/BCD

COUNTER #2

P0 P1 P2 P3 CTL1 CTL2 P4 P5 P6 P7

141312111026543



MC14569B


VDD – 55 C 25 C



Vin = VDD or 0

VOL

5.0

10

15

—

—

—

0.05

0.05

0.05

—

—

—

0

0

0

0.05

0.05

0.05

—

—

—


10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH 5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2



IOL 5.0

1015

0.64

1.64.2

—

— —

0.51

1.33.4

0.88

2.258.8

—

— —

0.

02


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—


(Dynamic plus Quiescent,Per Package)


buffers switching)

IT 5.0

1015





IT(CL) = IT(50 pF) + (CL – 50) Vfk




MC14569B

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25 C)

VDDAll Types


Output Rise Time tTLH

5.0

10

15

—

—

—

100

50

40


10

15

—

—

—

100

50

40


Zero Detect Output

tPLH

5.0

10

15

—

—

—

420

175

125

Q Output 5.010

15

— —

—

675285

200


Zero Detect Output

tPHL

5.0

10

15

—

—

—

380

150

100

Q Output 5.0

10

15

—

—

—

530

225

155


10

15

300

150

115

100

45

30


10

15

—

—

—

3.5

9.5

13.0


10

15

NO LIMIT




MC14569B

SWITCHING WAVEFORMS

tWH

Figure 1.

Figure 2.

20 ns

20 ns

CLOCK

Q

CLOCK

ZERO DETECT

90%50%

10%

50%90%

10%

tPLH tPHL

20 ns

20 ns

90%50%

10%

tWH

tPLH

tPHL

90%

10%

tTLH tTHL

tTLH tTHL

fin = fmax



MC14569B

PIN DESCRIPTIONS

INPUTS

P0, P1, P2, P3 (Pins 3, 4, 5, 6) — Preset Inputs.

Programmable inputs for the least significant counter. Maybe binary or BCD depending on the control input.P4, P5, P6, P7 (Pins 11, 12, 13, 14) — Preset Inputs.

Programmable inputs for the most significant counter. Maybe binary or BCD depending on the control input.

Clock (Pin 9) — Preset data is decremented by one oneach positive transition of this signal.

OUTPUTS

Zero Detect (Pin 1) — This output is normally low and

goes high for one clock cycle when the counter hasdecremented to zero.

Q (Pin 15) — Output of the last stage of the mostsignificant counter. This output will be inactive unless thepreset input P7 has been set high.

CONTROLS

Cascade Feedback (Pin 7) — Th

high. When low, loading of the preset is inhibited, i.e., P0 through P7 are “Table 1 for output characteristics.

CTL1 (Pin 2) — This pin controlsthe least significant counter. When seis BCD. When set low, counting mod

CTL2 (Pin 10) — This pin controlsthe most significant counter. When seis BCD. When set low, counting mod

SUPPLY PINS

VSS (Pin 18) — Negative Supplyusually connected to ground.

VDD (Pin 16) — Positive Supplyconnected to a positive supply voltvolts to 18.0 volts.


The MC14569B is a programmable divide–by–N dual4–bit down counter. This counter may be programmed (i.e.,preset) in BCD or binary code through inputs P0 to P7. Foreach counter, the counting sequence may be chosenindependently by applying a high (for BCD count) or a low(for binary count) to the control inputs CTL1 and CTL2.

The divide ratio N (N being the value programmed on thepreset inputs P0 to P7) is automatically loaded into thecounter as soon as the count 1 is detected. Therefore, a

division ratio of one is not possible. After N clock cycles,

one pulse appears on the Zero DetecDiagram.) The Q output is the output most significant counter (See TableControls.)

When cascading the MC14569B tCascade Feedback input, Q, and Zerobe respectively connected to “0”, Clfollowing counter. If the MC14569B Feedback must be connected to VDD

18

16

14

12

10

8.0

6.0

4.0

2.0 f , F R E Q U E N C Y ( M H z ) , T Y P I C A L

CL = 50 pF

VDD = 15 V

10 V

5.0 V



MC14569B

Table 1. Mode Controls (Cascade Feedback = Low)

Counter Control Values Divide Ratio

CTL1 CTL2 Zero Detect Q

0 0 256 256

0 1 160 160

1 0 160 160

1 1 100 100

NOTE: Data Preset Inputs (P0–P7) are “Don’t Cares” while Cascade Feedback is

Low.

Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)

Preset Inputs Divide Ratio

P7 P6 P5 P4 P3 P2 P1 P0 ZeroDetect Q Com

0 0 0 0 0 0 0 0 256 256 Max

0 0 0 0 0 0 0 1 X X Illeg

0 0 0 0 0 0 1 0 2 X Min

0 0 0 0 0 0 1 1 3 X

X

X

X

0 0 0 0 1 1 1 1 15 X

0 0 0 1 0 0 0 0 16 XX

X

X

0 0 1 0 0 0 0 0 32 X

X

X

X

0 1 0 0 0 0 0 0 64 X

X

XX

0 1 1 1 1 1 1 1 127 X

1 0 0 0 0 0 0 0 128 128 Q Out

1 0 0 0 1 0 0 0 136 136

1 1 1 1 1 1 1 1 255 255

27 26 25 24 23 22 21 20

128 64 32 16 8 4 2 1 Bit

Counter #2

Binary

Counter #1

Binary

Co

Seq

X = No Output (Always Low)



MC14569B

Table 3. Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High)

Preset Inputs Divide Ratio

P7 P6 P5 P4 P3 P2 P1 P0

Zero

Detect Q Com

0 0 0 0 0 0 0 0 160 160 Ma

0 0 0 0 0 0 0 1 X X Illeg

0 0 0 0 0 0 1 0 2 X Min

0 0 0 0 0 0 1 1 3 X

X

X

X

0 0 0 0 1 0 0 1 9 X

0 0 0 1 0 0 0 0 10 X

X

XX

0 0 0 1 1 0 0 1 19 X

0 0 1 0 0 0 0 0 20 X

X

X

X

0 0 1 1 0 0 0 0 30 X

X

X

X0 1 0 0 0 0 0 0 40 X

X

X

X

0 1 0 1 0 0 0 0 50 X

X

X

X

0 1 1 0 0 0 0 0 60 X

XX

X

0 1 1 1 0 0 0 0 70 X

X

X

X

1 0 0 0 0 0 0 0 80 80 Q Out

1 0 0 1 0 0 0 0 90 90

1 1 1 1 0 0 0 0 150 150



MC14569B

Table 4. Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High)

Preset Values Divide Ratio

P7 P6 P5 P4 P3 P2 P1 P0

Zero

Detect Q Com

0 0 0 0 0 0 0 0 160 160 Ma

0 0 0 0 0 0 0 1 X X Illeg

0 0 0 0 0 0 1 0 2 X Min

0 0 0 0 0 0 1 1 3 X

X

X

X

0 0 0 0 1 1 1 1 15 X

0 0 0 1 0 0 0 0 16 X

X

XX

0 0 0 1 1 1 1 1 31 X

0 0 1 0 0 0 0 0 32 X

X

X

X

0 0 1 1 0 0 0 0 48 X

0 1 0 0 0 0 0 0 64 X

0 1 0 1 0 0 0 0 80 X

0 1 1 1 0 0 0 0 112 X

1 0 0 0 0 0 0 0 128 128 Q Out

1 0 0 1 0 0 0 0 144 144

1 0 0 1 1 1 1 1 159 159

27 26 25 24 23 22 21 20

128 64 32 16 8 4 2 1 Bit

Counter #2

BCD

Counter #1

Binary

Co

Se




MC14569B

Table 5. Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High)

Preset Values Divide Ratio

P7 P6 P5 P4 P3 P2 P1 P0

Zero

Detect Q Com

0 0 0 0 0 0 0 0 100 100 Ma

0 0 0 0 0 0 0 1 X X illeg

0 0 0 0 0 0 1 0 2 X Min

0 0 0 0 0 0 1 1 3 X

X

X

X

0 0 0 0 1 0 0 1 9 X

0 0 0 1 0 0 0 0 10 X

X

XX

0 0 1 1 0 0 0 0 30 X

X

X

X

0 1 0 0 0 0 0 0 40 X

X

X

X

0 1 0 1 0 0 0 0 50 XX

X

X

0 1 1 1 0 0 0 0 70 X

X

X

X

1 0 0 0 0 0 0 0 80 80 Q Out

1 0 0 1 0 0 0 0 90 90

1 0 0 1 1 0 0 1 99 99

80 40 20 10 8 4 2 1 Bit

Counter #2

BCD

Counter #1

BCD

Co

Se


TIMING DIAGRAM MC14569B

CLOCK 13121110987654321



MC14569B

LOGIC DIAGRAM

Q

DPEC

DP

Q

DPEC

DP

Q

DPEC

DP

Q

D

PE

C

DP

Q

D

PE

C

DP

Q

D

PE

C

DP

Q

DPEC

DP

Q

DPEC

DP

VDD

VDD

D

Q PE

DP C

D

Q PE

DP C

IU

2

CASCADE

FEEDBACK

7

3

4

5

6

9

11

12

CTL1

P0

P1

P2

P3

CLOCK

P4

P5



MC14569B


Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B

finCF

C

MC14569B

ZERO DETECT

CFC

MC14522BOR

MC14526B

Q4

PE “0”

CFC

MC14522BOR

MC14526B

Q4

PE “0”

Q1/C2

PE

MC1456

LSD MS

DP0 – – – – – – DP3 DP0 – – – – – – DP3 DP0 – – – – –

Q

Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixe

(Channel Spacing 10 kHz)

Frequencies shown in parenthesis are given as an example

(40 kHz)

VSS

PE

DP0 – – – – DP3

PCin

C1

CT1

“0”

PCout

G

F

Q1/C2

VSS

VSS

VCO

MC14011

CFQ

ZERO DETECT

C

2 M

MC14569B



The MC14572UB hex functional gate is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. These complementary MOS logic gates findprimary use where low power dissipation and/or high noise immunityis desired. The chip contains four inverters, one NOR gate and oneNAND gate.

• Diode Protection on All Inputs•

Single Supply Operation• Supply Voltage Range = 3.0 Vdc to 18 Vdc• NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter• NAND Input Pin Adjacent to VDD Pin to Simplify Use As An

Inverter• NOR Output Pin Adjacent to Inverter Input Pin For OR Application• NAND Output Pin Adjacent to Inverter Input Pin For AND

Application

• Capable of Driving Two Low–power TTL Loads or One Low–PowerSchottky TTL Load over the Rated Temperature Range




Vin, Vout Input or Output Voltage Range(DC or Transient) –0.5 to VDD + 0.5 V



±10 mA



500 mW



TL Lead Temperature(8–Second Soldering) 260°C




http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14572UBCP PDIP–

MC14572UBD SOIC–



PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14572UBFEL SOEIAJ–

MC14572UBF SOEIAJ–



MC14572UB

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

INE

OUTF

IN 1F

IN 2F

VDD

OUTD

IND

OUTE

INB

OUTB

INA

OUTA

VSS

IN 2C

IN 1C

OUTC

LOGIC DIAGRAM

15

14

12

10

7

6

4

2

13

11

9

5

3

1

VDD = PIN 16

VSS = PIN 8

CIRCUIT SCHEMATIC

VDD

VDDVDD



MC14572UB



MC14572UB



Output Rise Time



tTLH

5.0

1015

—

— —

180

9065

Output Fall Time


tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 9.5 ns

tTHL

5.0

10

15

—

—

—

100

50

40





tPLH,

tPHL 5.0

10

15

—

—

—

90

50

40


Figure 1. Switching Time Test Circuits and Waveforms

PULSE

GENERATOR

PULSEGENERATOR

INPUT

2

INPUT

15

VDD

VDD

16

16

8

8 VSS

VSS

CL

CL

1

13

OUTPUT

OUTPUT

PULSE

GENERATOR

INPUT

7

VDD

16

8 VSS

6

20 ns

trtf

90%50%

10%

90%50%

10%

90%50%

10%

90%

10%50%

INPUT

OUTPUT

tPHL tPLH

14



The MC14584B Hex Schmitt Trigger is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. These devices find primary use where low powerdissipation and/or high noise immunity is desired. The MC14584Bmay be used in place of the MC14069UB hex inverter for enhancednoise immunity to “square up” slowly changing waveforms.


Schottky TTL Load over the Rated Temperature Range• Double Diode Protection on All Inputs• Can Be Used to Replace MC14069UB• For Greater Hysteresis, Use MC14106B which is Pin–for–Pin

Replacement for CD40106B and MM74Cl4





(DC or Transient)

–0.5 to VDD + 0.5 V



± 10 mA



500 mW



TL Lead Temperature


260 °C









ith V V ) U d t t t b l ft

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

PDIP–14

P SUFFIX

CASE 64

SOIC–14

D SUFFIX

CASE 751

TSSOP–1

DT SUFF

CASE 948

SOEIAJ–1

F SUFFIXCASE 96

Device Packag

ORDERING INF

MC14584BCP PDIP–

MC14584BD SOIC–

MC14584BDR2 SOIC

MC14584B



MC14584B

PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OUT 5

IN 5

OUT 6

IN 6

VDD

OUT 4

IN 4

OUT 2

IN 2

OUT 1

IN 1

VSS

OUT 3

IN 3

LOGIC DIAGRAM

13

11

9

5

3

1

12

10

8

6

4

2


EQIVALENT CIRCUIT SCHEMATIC


MC14584B



MC14584B


VDD – 55 C 25 C



Vin = VDD

VOL 5.0

1015

—

— —

0.05

0.050.05

—

— —

0

00

0.05

0.050.05

—

— —

Vin = 0 “1” Level VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH

= 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2


(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

—

—

0.51

1.3

3.4

0.88

2.25

8.8

—

—

—

0.

0

2


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

0.25

0.5

1.0

—

—

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

—

—



Per Package)


buffers switching)

IT 5.0

10

15




Hysteresis Voltage VH (7.) 5.0

10

15

0.27

0.36

0.77

1.0

1.3

1.7

0.25

0.3

0.6

0.6

0.7

1.1

1.0

1.2

1.5

0.

0.

0.

Threshold VoltagePositive–Going

VT+5.0

10

15

1.9

3.4

5.2

3.5

7.0

10.6

1.8

3.3

5.2

2.7

5.3

8.0

3.4

6.9

10.5

1

3

5

Negative–Going VT– 5.0

10

15

1.6

3.0

4.5

3.3

6.7

9.7

1.6

3.0

4.6

2.1

4.6

6.9

3.2

6.7

9.8

1

3

4


IT(CL) = IT(50 pF) + (CL – 50) Vfk


7. VH = VT+ – VT– (But maximum variation of VH is specified as less than VT + max – VT – min).

MC14584B



MC14584B



VDD

Vdc Min Typ (8.)


10

15

—

—

—

100

50

40


10

15

—

—

—

100

50

40


10

15

—

—

—

125

50

40


MC14584B




PULSE

GENERATOR

VDD

INPUTCLVSS7

OUTPUT

20 ns

90%50%10%

90%

50%10%

tPHL

OUTPUT

INPUT

tf

VDD

VT+

VT–

VSS

VDD

VSS

Vout

Vin

VH VH

Vout

Vin

VDD

0VDDVT+VT–0

VH


V o u t ,


Figure 2. Typical Schmitt Trigger Applications

(b) A Schmitt trigger offers maximu

in gate application

(a) Schmitt Triggers will square up inputs with slow

rise and fall times.


Vin Vout

14

The MC14585B 4–Bit Magnitude Comparator is constructed withcomplementary MOS (CMOS) enhancement mode devices. Thecircuit has eight comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0),three cascading inputs (A < B, A = B, and A > B), and three outputs (A< B, A = B, and A > B). This device compares two 4–bit words (A andB) and determines whether they are “less than”, “equal to”, or “greaterthan” by a high level on the appropriate output. For words greater than4–bits, units can be cascaded by connecting outputs (A > B), (A < B),and (A = B) to the corresponding inputs of the next significantcomparator. Inputs (A < B), (A = B), and (A > B) on the leastsignificant (first) comparator are connected to a low, a high, and a low,respectively.

Applications include logic in CPU’s, correction and/or detection of instrumentation conditions, comparator in testers, converters, andcontrols.

• Diode Protection on All Inputs• Expandable• Applicable to Binary or 8421–BCD Code• Supply Voltage Range = 3.0 Vdc to 18 Vdc• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load over the Rated Temperature Range• Can be Cascaded – See Fig. 3





(DC or Transient)

–0.5 to VDD + 0.5 V



±10 mA



500 mW



TL Lead Temperature


260 °C

2 M i R i h l b d hi h d h d i

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14585BCP PDIP–

MC14585BD SOIC–

MC14585BDR2 SOIC–


PDIP–16

P SUFFI

CASE 64

SOIC–1

D SUFFI

CASE 751

SOEIAJ–

F SUFFI

CASE 96

MC14585BF SOEIAJ–

MC14585B

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

(A B)out

(A B)out

B3

A3

VDD

B1

A0

B0

(A B)in

(A = B)out

A2

B2

VSS

A1

(A = B)in

(A B)in

BLOCK DIAGRAM

14

15

1

2

97

11

10

5

6

4

13

3

12

VDD = PIN 16

VSS = PIN 8

( A > B )in( A = B )in( A B )out

( A = B )out

( A B A B

A3 > B3 x x x x x x 0 0 1

A3 = B3 A2 > B2 x x x x x 0 0 1

A3 = B3 A2 = B2 A1 > B1 x x x x 0 0 1

A3 = B3 A2 = B2 A1 = B1 A0 > B0 x x x 0 0 1

A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 x 0 0 1

A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 x 0 1 0

A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 x 1 0 0

A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 1 x 1 1 0

A3 = B3 A2 = B2 A1 = B1 A0 < B0 x x x 1 0 0

MC14585B




VDD – 55 C 25 C



Vin = VDD or 0

VOL 5.0

1015

—

— —

0.05

0.050.05

—

— —

0

00

0.05

0.050.05

—

— —

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

—

—

4.95

9.95

14.95

5.0

10

15

—

—

—

4.

9.

14


(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

10

15

—

—

—

1.5

3.0

4.0

—

—

—

2.25

4.50

6.75

1.5

3.0

4.0

—

—

—


(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH5.0

10

15

3.5

7.0

11

—

—

—

3.5

7.0

11

2.75

5.50

8.25

—

—

—

3

7

1



(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

—

—

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

—

—

—

–

– 0

– 0

– 2



IOL 5.0

1015

0.64

1.64.2

—

— —

0.51

1.33.4

0.88

2.258.8

—

— —

0.

02


Input Capacitance

(Vin = 0)

Cin — — — — 5.0 7.5 —

Quiescent Current

(Per Package)

IDD 5.0

10

15

—

—

—

5.0

10

20

—

—

—

0.005

0.010

0.015

5.0

10

20

—

—

—

Total Supply Current(5.)

(6.)


Per Package)


buffers switching)

IT 5.010

15

IT = (0.6 µA/kHz) f + IDDIT = (1.2 µA/kHz) f + IDD



IT(CL) = IT(50 pF) + (CL – 50) Vfk


MC14585B

tTLH,

tTHL 5.0

10

15

—

—

—

100

50

40

Turn–On, Turn–Off Delay Time




tPLH,

tPHL 5.0

10

15

—

—

—

430

180

130


Figure 1. Dynamic Power Dissipation

Signal Waveforms

Figure 2. Dynamic Sign

20 ns

20 ns

2f

1

VDD

VSS

VDD

VSS

VOH

VOL

VOH

VOL

VOH

VOL

( A B )out

B3

A3

20 ns

90%

50%

10%

tPLH

tTLH

90%

50%

10%

B0

( A = B )out

( A B) and (A=B) high, an

A2, B1, A1, A0, and (A<B) low.

Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,

A1, B0, A0 and (A<B) low.


MC14585B

Figure 3. Cascading Comparators

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0V

WORDB =

A =WORD

MC14585B

MC14585B

MC14585BB3 A3 B2 A2 B1 A1 B0 A0

( A B

)

( A B )

OUTPUT

( A B )

OUTPUTS

WORD B = B11, B10, ..., B0.

WORD A = A11, A10, ..., A0.

15

14

2

1

7

9

10

11B0

A0

B1

A1

B2

A2

B3

A3

LOGIC DIAGRAM



The MC14598B is an 8–bit latch addressed with an external binaryaddress. The 8 latch–outputs are high drive, three–state and bus linecompatible. The drive capability allows direct applications with MPUsystems such as the Motorola 6800 family.

The latches of the MC14598B are accessed via the Address pins,A0, A1, and A2.

All 8 outputs from the latches are available in parallel when Enableis in the low state. Data is entered into a selected latch from the Datapin when the Strobe is high. Master reset is available on both parts.

• Serial Data Input• Three–State Bus Compatible Parallel Outputs• Three–State Control Pin (Enable) TTL Compatible Input• Open Drain Full Flag (Multiple Latch Wire–O Ring)• Master Reset•

Level Shifting Inputs on All Except Enable• Diode Protection — All Inputs• Supply Voltage Range — 3.0 Vdc to 18 Vdc• Capable of Driving TTL Over Rated Temperature Range

With Fanout as Follows:1 TTL Load4 LSTTL Loads




Vin Input Voltage Range,

Enable (DC or Transient)

–0.5 to VDD + 0.5 V

Vin Input Voltage Range, All Other

Inputs (DC or Transient)

–0.5 to VDD + 12 V

Vout

Output Voltage Range,

(DC or Transient)

–0.5 to VDD

+ 0.5 V



±10 mA



500 mW

http://onsem

A = Assem

WL or L = Wafer

YY or Y = Year

WW or W = Work

Device Packag

ORDERING INF

MC14598BCP PDIP–

1

18

PDIP–18P SUFFIX

CASE 707

This device contains prote

MC14598B



PIN ASSIGNMENT

NC

DATA

RESET

D0

VSS

A1

A0

STROBE

ENABLE D3

D2

D1

VDD

A2

D7

D6

D5

D414

15

16

17

18

10

11

12

13

5

4

3

2

1

9

8

7

6

BLOCK DIAGRAMS

MC14598B

Enable O

1 High I

0

Dn = State of nth l

OUTPUTRUTH TA

NC = NO CO

1

17

16

15

14

13

12

11

D0

D1

D2

D3

D4

D5

D6

D7

ENABLE

4

THREE

STATE

OUTPUT

BUFFERS

8

LATCHESADDRESS

DECODER

VDD = 18VSS = 9

2

3

6

RESET

DATA

STROBE

A0

A1

A2

7

8

10

MC14598B




VDD – 55 C 25 C



VOL 5.010

15

— —

—

0.050.05

0.05

— —

—

00

0

0.050.05

0.05

— —

—


VOH 5.01015

4.959.9514.95

— — —

4.959.9514.95

5.01015

— — —

4.9.14

Input Voltage (4.) — Enable “0” Level(VO = 4.5 or 0.5 Vdc)(VO = 9.0 or 1.0 Vdc)(VO = 13.5 or 1.5 Vdc)

VIL5.01015

— — —

0.81.62.4

— — —

1.12.23.4

0.81.62.4

— — —


(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH5.0

1015

2.0

6.010

—

— —

2.0

6.010

1.9

3.14.3

—

— —

2

61

Input Voltage “0” LevelOther Inputs(VO = 4.5 or 0.5 Vdc)(VO = 9.0 or 1.0 Vdc)(VO = 13.5 or 1.5 Vdc)

VIL

5.01015

— — —

1.53.04.0

— — —

2.254.506.75

1.53.04.0

— — —

(VO = 0.5 or 4.5 Vdc) “1” Level(VO = 1.0 or 9.0 Vdc)(VO = 1.5 or 13.5 Vdc)

VIH 5.01015

3.57.011

— — —

3.57.011

2.755.508.25

— — —

371

Output Drive Current Source(Full — Sink Only)(VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)

IOH

5.0101 5

– 1.0 — —

– — —

– 1.0 — —

– 2.0 – 6.0 – 12

— — —

– — —

(VOL = 0.4 Vdc) Sink(VOL = 0.5 Vdc)(VOL = 1.5 Vdc)

IOL 5.01015

1.6 — —

— — —

1.6 — —

3.26.012

— — —

1 — —


Three–State Leakage Current ITL 15 — ± 0.1 — ±0.00001 ± 0.1 —

Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 —


IDD 5.01015

— — —

5.01020

— — —

0.0050.0100.015

5.01020

— — —

Total Supply Current at an**External Load Capacitance of**130 pF (4.)

IT 5.010

IT = (2.0 µA/kHz) f + IDDIT = (4.0 µA/kHz) f + IDDIT = (6.0 µA/kHz) f + IDD


MC14598B



SWITCHING CHARACTERISTICS (5.) (TA = 25 C, CL = 130 pF + 1 TTL Load)

VDDAll Types



tTLH, tTHL = (0.5 ns/pF) CL + 35 nstTLH, tTHL = (0.2 ns/pF) CL + 25 ns


tTLH,

tTHL 5.010

15

— —

—

10050

40


Enable to Output

tPLH,

tPHL 5.0

10

15

—

—

—

160

125

100

Strobe to Output 5.0

10

15

—

—

—

200

100

80

Reset to Output 5.0

10

15

—

—

—

175

90

70

Pulse Width

Enable

tWH,

tWL 5.0

10

15

320

240

160

160

120

80

Strobe 5.0

10

15

200

100

80

100

50

40

Increment 5.0

10

15

200

100

80

100

50

40

Reset 5.0

10

15

300

160

100

150

80

50

Setup Time

Data

tsu

5.0

1015

100

5035

50

2520

Address 5.0

10

15

200

100

70

100

50

35

Hold Time

Data

th5.0

10

15

100

50

35

50

25

20

Address 5.010

15

10050

35

5025

20


10

15

20

20

20

– 25

– 15

– 10

5 Th f l i f th t i l h t i ti l t 25 C

MC14598B



MC14598B FUNCTION DIAGRAM

ENABLE 4

RESET 2

STROBE 6

DATA 3

TO OTHER

LATCHES

VDD

VSSEACH LATCH

ZERO

SELECT

ADDRESS

DECODERADDITIONAL 7 LATCHES

A0 7

A1 8

A2 10

TO OTHER

LATCHES

(M.S.B)

MC14598B TIMING DIAGRAM

*1.4 V with VDD = 5.0 V

NOTES:

1. High–impedance output state (another device controls bus).

2. Output Load as for MC14597B.

D7

RESET

A0, A1, A2

DATA

STROBE

ENABLE

90%10%50%

50%

tPHLtPLH

1

tTHL tPLH

90%10%

tTLH

tW50%

290%10%

tsu th

thtsu90%10% 50%

90%10%

20 ns tW20 ns

tW

*

MC14598B



TRUTH TABLE FOR MC1459

Address

Increment Enable Reset Counter

X 1 Count Up

X 1 No Change

X 1 0 Reset to Ze

X 0 1 No Change

If at

X 1 1 ADDRESS

X = Don’t care

LATCH TRUTH TABLE

Address Other

Strobe Reset Latch Latches

0 1 * *

1 1 Data *

X 0 0 0

*= No change in state of latch

X = Don’t care

TEST LOAD

ALL OUTPUTS

Dn

+5.0 V

RL = 2.5 k

11.7 k130 pF

Circuit diagrams external to or containing Motorola

products are included as a means of illustration only.Complete information sufficient for construction purposesmay not be fully illustrated. Although the information hereinhas been carefully checked and is believed to be reliable.Motorola assumes no responsibility for inaccuracies.Information herein does not convey to the purchaser anylicense under the patent rights of Motorola or others.

The information contained herein

with no warranty of any type, exMotorola reserves the right to makinformation and the product(s) to wapplies and to discontinue manufactuany time.



CH

CMOS R

RELIABILITY ll d i f il



RELIABILITY

Paramount in the mind of every semiconductor user is thequestion of device performance versus time. After theapplicability of a particular device has been established, itseffectiveness depends on the length of troublefree service it

can offer. The reliability of a device is exactly that — anexpression of how well it will serve the customer. Thefollowing discussion will attempt to present an overview of ON Semiconductor’s reliability efforts.

BASIC CONCEPTS

It is essential to begin with an explanation of the variousparameters of Reliability. These are probably summarizedbest in the Bathtub Curve (Figure 1). The reliability

performance of a device is characterized by three phases:infant mortality, useful life, and wearout. When a device isproduced, there is often a small distribution of failuremechanisms which will exhibit themselves under relativelymoderate stress levels and therefore appear early. Thisperiod of early failures, termed infant mortality is reducedsignificantly through proper manufacturing controls andscreening techniques. The most effective period is that inwhich only occasional random failure mechanisms appear.The useful life typically spans a long period of time with avery low failure rate. The final period is that in which thedevices literally wear out due to continuous phenomenawhich existed at the time of manufacture. Using strictlycontrolled design techniques and selectivity in applications,this period is shifted well beyond the lifetime required by theuser.

Figure 1.

TIME (HOURS)

F A I L U R E R A T E

INFANT MORTALITY

(SUCH AS EARLY

BURN–IN FAILURES)

WEAROUT

FAILURESUSEFUL LIFE

1,000,000100,00010,000100010010

usually expressed in percent failureOther forms include FIT (Failures in 10–4 = 10–9 failures per hour) and MFailure) or MTBF (Mean Time Bebeing equal to 1/ λ and having units o

Since reliability evaluations usuallyof an entire population of devices,Central Limit Theorem apply and λdistribution through the equation:

x2 (x, 2r +

2ntλ

100 – Cwhere x =

100

CL = Confidence Limit in pr = Number of rejectsn = Number of devicest = Duration of test

The confidence limit is the degree oin the calculation. The Central Limit Tvalues of any sample of units out of aproduce a normal distribution. A 50

termed the best estimate and is the meA 90% confidence limit is a very coresults in a higher λwhich represents tof the area of the distribution is to (Figure 2). The term (2r + 2) is called tand is an expression of the numbersuitable to x2 tables.

Figure 2.

50% CL

F R E Q U E N C Y

λ, FAILURE RATE

The number of rejects is a critdefinition of rejects often differs beWhile ON Semiconductor uses ddetermine failures, sometimes rejectthey are catastrophic Due to the incre

Y f i d t d i t ti h h th t d i ill b d (Fi 3) F D



Years of semiconductor device testing has shown thattemperature will accelerate failures and that this behaviorfits the form of the Arrhenius equation:

R (t) = R0(t)e – θ /kT

where R(t) = Reaction rate as a function of time andtemperature

R0 = A constantt = Timeθ = Activation energy in electron voltsk = Boltzman’s constantT = Temperature in degrees Kelvin

To provide time–temperature equivalents this equation isapplied to failure rate calculations in the form:

t = t0e θ /kTwhere t = time

t0 = A constant

The Arrhenius equation essentially states that reactionrate increases exponentially with temperature. Thisproduces a straight line when plotted in log–linear paperwith a slope expressed by Θ. Θ may be physicallyinterpreted as the energy threshold of a particular reaction orfailure mechanism. The activation energy exhibited bysemiconductors varies from about 0.3 eV. Although therelationships do not prohibit devices from having poorfailure rates and high activation energies, good performanceusually does not imply a high Θ. Studies by Bell TelephoneLaboratories have indicated that an overall Θ forsemiconductors is 1.0 eV. This value has been accepted bythe Rome Air Development Command fortime–temperature acceleration in powered burn–in. Datataken by ON Semiconductor on Integrated Circuits haveverified this number and it is therefore applied as ourstandard time–temperature regression for extrapolation of high temperature failure rates to temperatures at which the

devices will be used (Figure 3). For DeV is generally applied.

To accomplish this, the time in dtemperature (T1) of the test are plottedline is drawn at the temperature of in

with a 1.0 eV slope is drawn throughIts intersection with the vertical line

determines the number of equivalent dnumber may then be used with the x2

the failure rate at the temperature of iof 125 C at t1 of 10,000 hours, a t2results at a T2 of 50 C. If one rejectdevice hours of testing at 125 C, thtemperature will be 0.1%/1,000

confidence level. One reject at the edevice hours at 50 C will result in afailure rate, as illustrated in Figure 4.

Three parameters determine the faimanufacturer: the failure rate at theactivation energy employed, and the dtest temperature and the temperature ooften used in this manipulation is thewhich is simply the equivalent devi

temperature divided by the actual tesEvery device will eventually fail,

techniques in Semiconductor designwearout phase is extended far beyondDuring wearout, as in infant mortalchanging rapidly and therefore lparameter used to describe perform“Median Life” and is the point at whihave failed. There are currently only fe

mechanisms: electromigration of electrolytic corrosion in plastic devicePower devices.

1000 k

100 k

10 k

1.0 k

100

t2

1.2 1.6 2.0 2.4 2.8 3.2 3.6

P2

T I M E ( H O U R S )

100

10

1.0

0.01

λ2

1.2 1.6 2.0 2.4

R E R A T E ( % / 1 0 0 0 H O U

R S )

100 k

For increased flexibility in working with a broad range of where



For increased flexibility in working with a broad range of device hours, the time–temperature regression lines havebeen normalized to 500 C and the time scale omitted,permitting the user to define the scale based on his ownrequirements.

THERMAL MANAGEMENT

Circuit performance and long–term circuit reliability areaffected by die temperature. Normally, both are improved bykeeping the IC junction temperatures low.

Electrical power dissipated in any integrated circuit is asource of heat. This heat source increases the temperature of the die relative to some reference point, normally theambient temperature of 25 C in still air. The temperature

increase, then, depends on the amount of power dissipatedin the circuit and on the net thermal resistance between theheat source and the reference point.

The temperature at the junction is a function of thepackaging and mounting system’s ability to remove heatgenerated in the circuit — from the junction region to theambient environment. The basic formula for convertingpower dissipation to estimated junction temperature is:

TJ = TA + PD(θJC + θCA) (1)

or TJ = TA + PD(θJA) (2)

whereTJ = maximum junction tempTA = maximum ambient tempePD = calculated maximum pow

including effects of exter

Power Dissipation in secθJC = average thermal resistancθCA = average thermal resistancθJA = average thermal resistanc

ambient

This ON Semiconductor recommenapproved by RADC or DESC for calmaximum operating junction MIL–M–38510 (JAN) devices.

Only two terms on the right side ovaried by the user — the ambient device case–to–ambient thermal resisextent the device power dissipation cbut under recommended use the VCdictate a fixed power dissipation.) Bothe package mounting technique afresistance term. θJC is essentially inand external mounting method, but imaterial, die bonding method, and di

Thermal Resistance in Still Air

Package Description

No. Bod Bod Bod Die Die Area Fla Area

Leads Style Material W x L Bonds

(Sq. Mils)

(Sq. Mils) A

14

16

DIL

DIL

Epoxy

Epoxy

1/4″ x 3/4″

1/4″ x 3/4″

Epoxy

Epoxy

4096

4096

6,400

12,100

NOTES:

1. All plastic packages use copper lead frames.

2. Body style DIL is “Dual–In–Line.”

3. Standard Mounting Method: Dual–In–Line Socket or P/C board with no contact between bottom of package a

Figure 5. Thermal Resistance Values for Standard I/C Packages

For applications where the case is held at essentially afixed temperature by mounting on a large ortemperature–controlled heat sink, the estimated junction

temperature is calculated by:TJ = TC + PD(θJC) (3)

where TC = maximum case temperature and the otherparameters are as previously defined.

The maximum and average θJC resistance values fort d d IC k i i Fi 5

These figures show the proportio junction temperature of each dual in–passes over each device. For higher

change in junction temperature fromdown the airstream will be lower due

Power Dissipation

(mW)

Junction Te

( C

200

OPTIMIZING THE LONG TERM RELIABILITY OF Table 1 is graphically illustrated in



OPTIMIZING THE LONG TERM RELIABILITY OFPLASTIC PACKAGES

Todays plastic integrated circuit packages are as reliableas ceramic packages under most environmental conditions.However when the ultimate in system reliability is required,

thermal management must be considered as a prime systemdesign goal.

Modern plastic package assembly technology utilizesgold wire bonded to aluminum bonding pads throughout theelectronics industry. When exposed to high temperatures forprotracted periods of time an intermetallic compound canform in the bond area resulting in high impedance contactsand degradation of device performance. Since the formationof intermetallic compounds is directly related to device

junction temperature, it is incumbent on the designer todetermine that the device junction temperatures areconsistent with system reliability goals.

Predicting Bond Failure Time:

Based on the results of almost ten (10) years of +125 Coperating life testing, a special arrhenius equation has beendeveloped to show the relationship between junctiontemperature and reliability.

11554.267Eq. (1) T = (6.376 x 109)e273.15 + TJ

Where: T = Time in hours to 0.1% bond failureT = (1 failure per 1,000 bonds).

TJ = Device junction temperature, C.And:Eq. (2) TJ = TA + PDθJA = TA + ∆TJ

Where: TJ = Device junction temperature, C.

TA = Ambient temperature, C.PD = Device power dissipation in watts.θJA = Device thermal resistance, junction to air,

C/Watt.∆TJ = Increase in junction temperature due to

on–chip power dissipation.

Table 1 shows the relationship between junctiontemperature, and continuous operating time to 0.1%. bondfailure, (1 failure per 1,000 bonds).

Table 1. Device Junction Temperature versus Time

to 0.1% Bond Failures

Junction

Temperature C Time, Hours Time, Years

80 1,032,200 117.8

Table 1 is graphically illustrated in that the reliability for plastic and cesame until elevated junction teintermetallic failures in plastic devicfailure rates of plastic devices are

intermetallic mechanism.

Figure 7. Failure Rate ve

Junction Tempera

101

TIME, YEARS

N O R M A L I Z E D F A I L U R E R A T E

1

FAILURE RATE OF PLASTIC = CERAM

UNTIL INTERMETALLIC FAILURES OC

T J =

1 2 0 C °

T J =

1 3 0 C °

T J =

1 1 0 C °

T J =

1 0 0 C °

T J =

9 0 C °

Procedure

After the desired system failure rat

for failure mechanisms other thandevice in the system should be eva junction temperature. Knowing thetemperature, refer to Table 1 or Equatcontinuous operating time required tdue to intermetallic formation. Areliability departs from the desired Figure 7.

Air flow is one method of therma

should be considered for system longeused methods include heat sinks for hirefrigerated air flow and lower densityθCA is entirely dependent on the responsibility of the designer to determbe achieved by various techniques



P D ,

M A

X I M U M P O W E R D I S S I P A T I O N P E R

P A C K A G E ( m W )

Figure 8. Junction Temperature for Worst Case

CMOS Logic Device

150°C

125°C

100°C

75°C

50°C

125°C65°C25°C

TA, AMBIENT TEMPERATURE

137°C

134°C139°C

121°C

99°C

81°C

TJ PDIP

– 7 mW/ °C

PD

PDIP & SOIC

T J ,

J U N C T I O N T E M P E R A T U R

E ( C ) °

500

400

300

200

100

TJ SOIC

Figure 9. Junction Temperatu

CMOS Logic Devi

150°C

125°C

100°C

75°C

50°C 65°C25°C

TA, AMBIENT TEMPERAT

T J ,

J U N C T I O N T E M P E R A T U R

E ( C ) °

TJ SOIC

129°C

89°C

58°C

TJ PDIP

98°C

This graph illustrates junction temperature for the worst case CMOS

Logic device (MC14007UB) — smallest die area operating at

maximum power dissipation limit in still air. The solid line indicates

the junction temperature, TJ, in a Dual–In–Line (PDIP) package and

in a Small Outline IC (SOIC) package versus ambient temperature,TA. The dotted line indicates maximum allowable power dissipation

derated over the ambient temperature range, 25 C to 125 C.

This graph illustrates junction temperature

(MC14053B) — average die area opera

dissipation limit in still air. The solid lin

temperature, TJ, in a Dual–In–Line (PDIP

Outline IC (SOIC) package versus ambiedotted line indicates maximum allowable p

over the ambient temperature range, 25 C



CH

Equivalent G



The following is a list of equivalent gate counts for some of ON Semiconductor’s CMOS devices. Ithe number of equivalent gates is equal to the total number of transistors on chip divided by four. This l

devices with equivalent gate counts known at the time of this printing.EQUIVALENT EQUIV

DEVICE GATE COUNT DEVICE GATE

MC14001B 8 MC14081B 1

MC14001UB 4 MC14082B 8

MC14007UB 1.5 MC14093B 1

MC14008B 40 MC14094B 7

MC14011B 8 MC14099B 7

MC14011UB 4 MC14174B 43

MC14012B 7 MC14175B 39MC14013B 16 MC14490 13

MC14014B 74 MC14503B 1

MC14015B 53 MC14504B 37

MC14016B 8 MC14511B 5

MC14017B 62.5 MC14512B 17

MC14018B 38.25 MC14514B 5

MC14020B 84 MC14515B 6

MC14021B 74 MC14516B 6

MC14023B 9 MC14517B 1

MC14024B 59 MC14518B 43MC14025B 9 MC14520B 43

MC14028B 26 MC14526B 8

MC14029B 65.5 MC14528B 2

MC14040B 73 MC14532B 38

MC14042B 17.5 MC14536B 1

MC14046B 35 MC14538B 3

MC14049UB 3 MC14541B 9

MC14049B 9 MC14543B 5

MC14050B 6 MC14549B 12

MC14051B 48.5 MC14551B 3MC14052B 38.5 MC14553B 14

MC14053B 38 MC14555B 2

MC14060B 73.5 MC14556B 2

MC14066B 13 MC14557B 23

MC14067B 65 MC14559B 12

MC14069UB 3 MC14562B 2

MC14071B 10 MC14569B 15

MC14073B 10.5 MC14572UB 4

MC14076B 32.5 MC14584B 1



CH

Packaging Information Including Surfac



The standard package availability for each device is indicated on the front page of the individual dafor the packages are given in this chapter. Surface mount packages may be special ordered by specifying “D” (narrow SOIC), “DW” (wide SOIC), or “DT” (TSSOP). For example, to order a quad NOR gate,

1 7

14 8

B

ADIM MIN MAX

INCHES

A 0.715 0.770

B 0.240 0.260

C 0.145 0.185

D 0.015 0.021

F 0.040 0.070

G 0.100 BSC

H 0.052 0.095J 0.008 0.015

K 0.115 0.135

L

M ––– 10

N 0.015 0.039

NOTES:1. DIMENSIONING AND TO

Y14.5M, 1982.2. CONTROLLING DIMENS3. DIMENSION L TO CENTE

FORMED PARALLEL.4. DIMENSION B DOES NO5. ROUNDED CORNERS O

F

H G DK

C

SEATINGPLANE

N

–T–

14 PL

M0.13 (0.005)

L

M

J0.290 0.310

PDIP–14P SUFFIX

PLASTIC PACKAGECASE 646–06

ISSUE M

NOTES:1. DIMENSIONING A

Y14.5M, 1982.2. CONTROLLING D3. DIMENSIONS A A

MOLD PROTRUSI4. MAXIMUM MOLD

PER SIDE.5. DIMENSION D DO

PROTRUSION. ALPROTRUSION SHIN EXCESS OF THMAXIMUM MATER

–A–

–B–

G

P 7 PL

14 8

71M0.25 (0.010) B M

FR X 45C

DIM MIN

MILLIMET

A 8.55

B 3.80

C 1.35

SOIC–14D SUFFIX

PLASTIC PACKAGECASE 751A–03

ISSUE F

(continued)



DIM MIN

MILLIMET

A 4.90

B 4.30

C –––

D 0.05

F 0.50G 0.65 BS

H 0.50

J 0.09

J1 0.09

K 0.19

K1 0.19

L 6.40 BS

M 0

NOTES:1. DIMENSIONIN

Y14.5M, 1982.2. CONTROLLING3. DIMENSION A

FLASH, PROTRUFLASH OR GATE (0.006) PER SIDE.

4. DIMENSION B FLASH OR PROTRPROTRUSION SH0.25 (0.010) PER S

5. DIMENSION K PROTRUSION. ALPROTRUSION SHEXCESS OF THE KMATERIAL CONDI

6. TERMINAL NUREFERENCE ONL

7. DIMENSION A AT DATUM PLANE

SU0.15 (0.006) T

2X L/2

SUM0.10 (0.004) V ST

L –U–

SEATING

PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)814

71

PIN 1IDENT.

HG

A

D

C

B

SU0.15 (0.006) T

–V–

14X REFK

N

N

TSSOP–14DT SUFFIX

PLASTIC PACKAGE

CASE 948G–01ISSUE O

HE

DIM MIN M

MILLIMETE

LE

Q1

NOTES:1. DIMENSIONING

Y14.5M, 1982.2. CONTROLLING D3. DIMENSIONS D A

MOLD FLASH OR PMEASURED AT THEOR PROTRUSIONS (0.006) PER SIDE.

4. TERMINAL NUMREFERENCE ONLY.

5. THE LEAD WIDTINCLUDE DAMBAR

DAMBAR PROTRUSTOTAL IN EXCESS ODIMENSION AT MAXDAMBAR CANNOT BRADIUS OR THE FOBETWEEN PROTRUTO BE 0.46 ( 0.018).

D

Z

E

1

14 8

7L

DETAIL P

M

SOEIAJ–14F SUFFIX


ISSUE O



NOTES:1. DIMENSIONING AND TO

Y14.5M, 1982.2. CONTROLLING DIMENS3. DIMENSION L TO CENT

FORMED PARALLEL.4. DIMENSION B DOES NO5. ROUNDED CORNERS O

–A–

B

F C

S

HG

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE –T–

MAM0.25 (0.010) T

DIM MIN MAX

INCHES

A 0.740 0.770

B 0.250 0.270

C 0.145 0.175

D 0.015 0.021F 0.040 0.70

G 0.100 BSC

H 0.050 BSC

J 0.008 0.015

K 0.110 0.130

L 0.295 0.305

M 0 10

S 0.020 0.040

PDIP–16P SUFFIX

PLASTIC PACKAGE

CASE 648–08ISSUE R


Y14.5M, 1982.2. CONTROLLING 3. DIMENSIONS A

MOLD PROTRUS4. MAXIMUM MOLD

PER SIDE.

5. DIMENSION D DPROTRUSION. APROTRUSION SIN EXCESS OF TMAXIMUM MATE

1 8

16 9

SEATINGPLANE

F

JM

R X 45

G

8 PLP –B–

–A–

M0.25 (0.010) B S

–T–

D

K

C

16 PL

SBM0.25 (0.010) A ST

DIM MIN

MILLIME

A 9.80

B 3.80

C 1.35

D 0.35

F 0.40

G 1.27 B

J 0.19

K0.10M 0

P 5.80

R 0.25

SOIC–16D SUFFIX

PLASTIC PACKAGECASE 751B–05

ISSUE J

(continued)



HE

A1

DIM MIN MAX

––– 2.05

MILLIMETERS

0.05 0.200.35 0.50

0.18 0.279.90 10.505.10 5.45

1.27 BSC7.40 8.200.50 0.851.10 1.500

0.70 0.90 ––– 0.78

A1

HE

Q1

LE

10

LE

Q1

NOTES:1. DIMENSIONING AN

Y14.5M, 1982.2. CONTROLLING DIM3. DIMENSIONS D AND

MOLD FLASH OR PROTMEASURED AT THE PAOR PROTRUSIONS SH(0.006) PER SIDE.

4. TERMINAL NUMBERREFERENCE ONLY.

5. THE LEAD WIDTH DINCLUDE DAMBAR PRODAMBAR PROTRUSIONTOTAL IN EXCESS OF DIMENSION AT MAXIMDAMBAR CANNOT BE RADIUS OR THE FOOTBETWEEN PROTRUSIOTO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

cA

b

e

M0.13 (0.005) 0.10 (0.004)

1

16 9

8

DZ

E

A

b

c

D

E

e

L

M

Z

SOEIAJ–16F SUFFIX


ISSUE O

DIM MIN M

MILLIMET

A 4.90

B 4.30

C –––

D 0.05

F 0.50

G 0.65 BS

H 0.18

J 0.09

J1 0 09


Y14.5M, 1982.2. CONTROLLING3. DIMENSION A

FLASH. PROTRUSFLASH OR GATE B

(0.006) PER SIDE.4. DIMENSION B FLASH OR PROTRPROTRUSION SHA0.25 (0.010) PER S

5. DIMENSION K PROTRUSION. ALPROTRUSION SHAEXCESS OF THE KMATERIAL CONDI

6. TERMINAL NUMREFERENCE ONL

7. DIMENSION A AT DATUM PLANE

SECTION N–N

IDENT.

PIN 1

1 8

16 9

J

J1

B

A

K

K1

M

L

2X L/2

–U–

SU0.15 (0.006) T

SU0.15 (0.006) T

SUM0.10 (0.004) V ST

–V–

0.25 (0.010)

16X REFK

N

N

TSSOP–16DT SUFFIX

PLASTIC PACKAGECASE 948F–01

ISSUE O

(continued)



D

14X

B16X

SEATINGPLANE

SAM0.25 B ST

16 9

81

h X 4 5

M

B

M

0 . 2

5

H

8 X E

B

A

e

T A 1

A

L

C

NOTES:1. DIMENSIONS AR2. INTERPRET DIME

PER ASME Y14.53. DIMENSIONS D A

PROTRUSION.4. MAXIMUM MOLD5. DIMENSION B DO

PROTRUSION. ALPROTRUSION SHOF THE B DIMENSCONDITION.

DIM MIN

MILLIMET

A 2.35

A1 0.10

B 0.35

C 0.23

D 10.15

E 7.40

e 1.27 BS

H 10.05

h 0.25

L 0.50

0

SOIC–16DW SUFFIX

PLASTIC PACKAGE

CASE 751G–03ISSUE B

NOTES:1. POSITIONAL TOLERANCE

SHALL BE WITHIN 0.25 (0.MATERIAL CONDITION, INSEATING PLANE AND EAC

2. DIMENSION L TO CENTERFORMED PARALLEL.

3. DIMENSION B DOES NOTFLASH.

1

SEATING

10

9

18

M

A

B

K

C

N

F DJ

LDIM MIN MAX

MILLIMETERS

A 22.22 23.24

B 6.10 6.60

C 3.56 4.57

D 0.36 0.56

F 1.27 1.78

G 2.54 BSC

H 1.02 1.52

J 0 20 0 30

PDIP–18P SUFFIX

PLASTIC PACKAGECASE 707–02ISSUE C



NOTES:1. POSITIONAL TOLERA

SHALL BE WITHIN 0.25MATERIAL CONDITIONSEATING PLANE AND

2. DIMENSION L TO CENFORMED PARALLEL.

3. DIMENSION B DOES NFLASH.

DIM MIN MAX

MILLIMETERS

A 31.37 32.13

B 13.72 14.22

C3.94 5.08D 0.36 0.56

F 1.02 1.52

G 2.54 BSC

H 1.65 2.03

J 0.20 0.38

K 2.92 3.43

L 15.24 BSC

M 0 15

N 0.51 1.02

1 12

1324

B

H

A

F

DG

K

SEATINGPLANE

N

C

M J

L

PDIP–24P SUFFIX

PLASTIC PACKAGE

CASE 709–02ISSUE C

NOTES:1. DIMENSIONING AND TOL

Y14.5M, 1982.

2. CONTROLLING DIMENSI3. DIMENSIONS A AND B DOMOLD PROTRUSION.

4. MAXIMUM MOLD PROTRPER SIDE.

5. DIMENSION D DOES NOTPROTRUSION. ALLOWABPROTRUSION SHALL BEEXCESS OF D DIMENSIOMATERIAL CONDITION.

–A–

–B– P12X

D24X

12

1324

1

M0.010 (0.25) B M

SAM0.010 (0.25) B ST

–T–

G22X

SEATINGPLANE K

C

R X 45

M

F

J

DIM MIN MAX

MILLIMETERS

A 15.25 15.54

B 7.40 7.60

C 2.35 2.65

D 0.35 0.49F 0.41 0.90

G 1.27 BSC

J 0.23 0.32

K 0.13 0.29

M 0 8

P 10.05 10.55

R 0.25 0.75

SOIC–24DW SUFFIXPLASTIC PACKAGE

CASE 751E–04ISSUE E

ON SEMICONDUCTOR MAJOR WORLDWIDE SALES OF

UNITED STATES CANADA INTERNATIONAL



UNITED STATES

ALABAMAHuntsville (256)464–6800. . . . . . . . . . . . . . . . . .

CALIFORNIAIrvine (949)753–7360. . . . . . . . . . . . . . . . . . . . . .

San Jose (408)749–0510. . . . . . . . . . . . . . . . . .COLORADO

Denver (303)337–3434. . . . . . . . . . . . . . . . . . . .

FLORIDASt. Petersberg (813)524–4177. . . . . . . . . . . . . .

GEORGIAAtlanta (770)338–3810. . . . . . . . . . . . . . . . . . . .

ILLINOISChicago (847)413–2500. . . . . . . . . . . . . . . . . . .

MASSACHUSETTSBoston (781)932–9700. . . . . . . . . . . . . . . . . . . .

MICHIGANDetroit (248)347–6800. . . . . . . . . . . . . . . . . . . . .

MINNESOTAPlymouth (612)249–2360. . . . . . . . . . . . . . . . . .

NORTH CAROLINARaleigh (919)870–4355. . . . . . . . . . . . . . . . . . . .

PENNSYLVANIAPhiladelphia/Horsham (215)957–4100. . . . . . .

TEXASDallas (972)516–5100. . . . . . . . . . . . . . . . . . . . .

CANADA

ONTARIOOttawa (613)226–3491. . . . . . . . . . . . . . . . . . . .

QUEBECMontreal (514)333–3300. . . . . . . . . . . . . . . . . . .

INTERNATIONAL

BRAZILSao Paulo 55(011)3030–5244. . . . . . . . . . . . .

CHINABeijing 86–10–65642288. . . . . . . . . . . . . . . . . . .

Guangzhou 86–20–87537888. . . . . . . . . . . . . .

Shanghai 86–21–63747668. . . . . . . . . . . . . . . .

FRANCEParis 33134 635900. . . . . . . . . . . . . . . . . . . . . .

GERMANYMunich 49 89 92103–0. . . . . . . . . . . . . . . . . . . .

HONG KONGHong Kong 852–2–610–6888. . . . . . . . . . . . . . .

INDIABangalore 91–80–5598615. . . . . . . . . . . . . . . . .

ISRAELTel Aviv 972–9–9522333. . . . . . . . . . . . . . . . . . .

ITALYMilan 39(02)82201. . . . . . . . . . . . . . . . . . . . . . . .

JAPANTokyo 81–3–5487–8345. . . . . . . . . . . . . . . . . . .

INTERNATIONAL

KOREASeoul . . . . . . . . . . .

MALAYSIAPenang . . . . . . . . .

MEXICOGuadalajara . . . . .

PHILIPPINESManila . . . . . . . . . .

PUERTO RICOSan Juan . . . . . . .

SINGAPORESingapore . . . . . . .

SPAINMadrid . . . . . . . . . .

or . . . . . . . . . . . . . .

SWEDENStockholm . . . . . .

TAIWANTaipei . . . . . . . . . .

THAILANDBangkok . . . . . . . .

UNITED KINGDOAylesbury . . . . . . .

ON SEMICONDUCTOR STANDARD DOCUMENT TYPE DEFINITIONS



REFERENCE MANUAL

A Reference Manual is a publication that contains a comprehensive system or device–specific description of th(operation) of a particular part/system; used overwhelmingly to describe the functionality of a microprocessor, m

other sub–micron sized device. Procedural information in a Reference Manual is limited to less than 40 percent

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A User’s Guide contains procedural, task–oriented instructions for using or running a device or product. A Ua Reference Manual in the following respects:* Majority of information (> 60%) is procedural, not functional, in nature* Volume of information is typically less than for Reference Manuals* Usually written more in active voice, using second–person singular (you) than is found in Reference Manuals* May contain photographs and detailed line drawings rather than simple illustrations that are often found in Re

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pocket guides include block diagrams, pinouts, alphabetized instruction set, alphabetized registers, alphabetizedtheir products, etc.

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A documentation Addendum is a supplemental publication that contains missing information or replaces prelimprimary publication it supports. Individual addendum items are published cumulatively. Addendums end with primary document.

APPLICATION NOTE

An Application Note is a document that contains real–world application information about how a specdevice/product is used with other ON Semiconductor or vendor parts/software to address a particular technical issmust already exist and be available.

A document called “Application–Specific Information” is not the same as an Application Note.

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A Selector Guide is a tri–fold (or larger) document published on a regular basis (usually quarterly) by many,contains key line–item, device–specific information for particular product families. Some Selector Guides are pand contain previously published information.

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A Product Preview is a summary document for a product/device under consideration or in the early stages of dePreview exists only until an “Advance Information” document is published that replaces it. The Product Previewsection or chapter in a corresponding reference manual. The Product Preview displays the following disclaimer page: “ON Semiconductor reserves the right to change or discontinue this product without notice.”

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The Advance Information document is for a device that is NOT fully MC–qualified. The Advance Informatiowith the Technical Data document once the device/part becomes fully MC–qualified. The Advance Informationfollowing disclaimer at the bottom of the first page: “This document contains information on a new product. Specifherein are subject to change without notice.”

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The Technical Data document is for a product/device that is in full production (i.e., fully released). It replaces tdocument and represents a part that is M X XC or MC qualified The Technical Data document is virtually th

c mos- ic''s -data -book

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