c 2015 andrew r. stillwell - university of illinois urbana

DIFFERENTIAL POWER PROCESSING FOR SERIES-STACKEDPROCESSORS

BY

ANDREW R. STILLWELL

THESIS

Submitted in partial fulfillment of the requirementsfor the degree of Master of Science in Electrical and Computer Engineering

in the Graduate College of theUniversity of Illinois at Urbana-Champaign, 2015

Urbana, Illinois

Adviser:

Assistant Professor Robert Pilawa-Podgurski

ABSTRACT

The series-stacked architecture provides a method to increase power delivery

efficiency to multiple processors. With a series-stack, differential power pro-

cessing (DPP) is needed to ensure that processor voltages remain within de-

sign limits as the individual loads vary. This work demonstrates a switched-

capacitor (SC) converter to balance a stack of four ARM R© Cortex-A8 based

embedded computers. A model of a series-stack with no DPP is first dis-

cussed for the case when loads can be controlled with no power electronics.

We investigate hard-switched and resonant modes of operation in a ladder

SC DPP converter, implemented with GaN transistors. Excellent 5 V regu-

lation of each embedded computer is demonstrated in a 4-series-stack config-

uration, with realistic computational workloads. Moreover, we demonstrate

hot-swapping of individual computers with maintained voltage regulation at

all nodes. A peak stack power delivery of 99.8% is demonstrated, and DPP

switching frequencies from 250 kHz to 2 MHz. Finally, the reliability of a

series-stacked system is compared to an electrically parallel system.

ii

To my wife, who provides the motivation, competition and inspiration.

iii

ACKNOWLEDGMENTS

Special thanks to my parents, who got up way too early on Saturday morn-

ings to drop me off at math competitions.

I’d like to thank Professor Sauer for help guiding me through my first

semester at UIUC.

I’d like to thank the ECE department and the Grainger Foundation for

funding my work.

Finally, I’d like to thank my advisor, Professor Pilawa-Podgurski, for tak-

ing me on so I didn’t have to go back to the “real world.”

iv

TABLE OF CONTENTS

CHAPTER 1 BACKGROUND . . . . . . . . . . . . . . . . . . . . . 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Series-Stack Model . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Element-to-Element Optimal Order . . . . . . . . . . . . . . . 51.4 Voltage Regulation of a Series-Stack . . . . . . . . . . . . . . . 11

CHAPTER 2 EXPERIMENTAL WORK . . . . . . . . . . . . . . . . 142.1 Experimental Prototype . . . . . . . . . . . . . . . . . . . . . 142.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 162.3 Hot-Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4 Series-Stacked Availability Modeling . . . . . . . . . . . . . . 262.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

APPENDIX A SUPPORT CODE . . . . . . . . . . . . . . . . . . . . 41A.1 Series-Stacked Model . . . . . . . . . . . . . . . . . . . . . . . 41A.2 Model Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42A.3 PWM and Light Load Operation . . . . . . . . . . . . . . . . 46A.4 PWM Sweeping . . . . . . . . . . . . . . . . . . . . . . . . . . 62

REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

v

CHAPTER 1

BACKGROUND

1.1 Introduction

Current trends in semiconductor scaling are driving down processor supply

voltages to optimize performance in constrained power limits. In order to

continue to improve system performance, suppliers have increasingly moved

to parallelism. These two trends have led to increasing current levels, which

are proving a challenge for typical 12 V to 1 V VRM applications that must

process large currents. In systems today, all processors are connected electri-

cally in parallel. Recently, it has been proposed to connect processor loads

electrically in series so that the processors share the stack current [1], [2].

In order to regulate the voltages of the individual loads, differential power

processing is applied to handle the mismatch currents. This series-stacked

architecture allows the DPP circuitry to only process the mismatch current

rather than the full current of the load. In the case of multiple processors

with similar loads, this leads to low power processed and low power losses.

The series-stacked architecture has also been applied to multiple server

applications [3–5] to reduce DC conversion power loss. The differential power

processing circuitry for series-stacked systems could be implemented in many

ways. Previous work has considered a “buck-boost” type converter similar

to those used for battery charging [6], solar panel strings [7–9] and stacked

digital circuits [10, 11]. Recent work has also considered the SC resonant

ladder for solar PV strings [12]. Switched-capacitor converters offer high

power density due to the higher energy density of capacitors compared to

inductors. SC converters also have the potential to be implemented in CMOS

[13], which would be beneficial in space constrained mobile applications.

This work describes a method to power a stack of four Texas Instruments

BeagleBone Black ARM R© based embedded computers. Each stacked com-

1

puter load consists of a AM335x 1GHZ ARM R© Cortex-A8 processor with

512MB RAM and consumes up to 460 mA at 5 V. The ARM R© based com-

puters were chosen because they feature a single core processor, extensive

Linux support, and present a realistic load for such a system. When imple-

menting a series-stack, start-up is a challenge. The stack should be balanced

before any loads are connected or else a load may see an input voltage that

is out of range. Also, an ideal stack would have provisions for hot-swapping

out a load in the case of maintenance or outage. This work demonstrates

one implementation that allows for a safe start-up and hot-swapping loads

as needed. Finally, in cases where all loads are well matched, the power

processed by the DPP converter is minimal and presents a light load condi-

tion. This thesis details a light load control scheme that improves converter

efficiency at low power processed.

This work is the first to regulate the voltages on a series-stack of processors

running application software. It also is the first to use a resonant ladder SC

converter on a series-stack of active processor loads and actively hot-swap a

processor. This work is organized as follows: Section 1.2 discusses a model

of the behavior of the series-stack without DPP. When analyzing the series-

stack with element-to-element DPP, it was found that the power processed

by the stack is dependent on the order of the loads. Section 1.3 discusses

the mathematical derivation for this behavior and formulates the optimal or-

der into an equation. Section 1.4 discusses how differential power processing

can be applied to a series-stack and Section 2.1 discusses a prototype (Fig-

ure 1.1) built based on this analysis. The experimental results taken from the

prototype are discussed in Section 2.2. One of the most common concerns

about series-stacked implementations is the reliability of the system since

often one DPP failure will result in the failure of the entire stack of loads.

Section 2.4 gives a brief analysis of a series-stacked converter in comparison

with a parallel architecture. Finally, Section 2.5 presents the conclusion of

this work.

1.2 Series-Stack Model

In an ideal case, a series-stack of loads would not need DPP. This section

models and provides the behavior of a series-stack without DPP applied to

2

P1

P1

P1

P2

P2

P2

P2

CPU1

EN1

EN1

EN2

EN2

EN3

EN3

EN4

EN4

P1

Cout1

Cout2

Cout3

Cout4

Cf1

Cf2

Cf3

Lf1

Lf2

Lf3

Microcontroller

TI5C2000

CPU2

CPU3

CPU4

Level5Shifter Gate5Driver

S1

S2

S3

S4

S5

S6

S7

S8




Level5Shifter

Level5Shifter

Level5Shifter

Level5Shifter

S9

S10

S11

S12

S13

S14

S15

S16

S1S2S3S4S5S6S7S8

S9S10S11S12S13S14S15S16

p−

Vstack ENs

S17Level5Shifter S17

Hot5Swapping Resonant5Ladder Resonant5Ladder

Figure 1.1: Block diagram of resonant ladder converter on a series-stack.

determine voltage swings given certain loads, and provides a foundation for

future work. This model could also be used for simulation of a stack of

controllable CPU loads. If the loads can be controlled by the processing

tasks given to the individual processors in the stack, then the stack could be

balanced over time even if it could not be balanced at a particular instant.

Assuming that a processor or load can allow for some voltage swing in the

supply voltage, the model shows how much the node voltages would swing in

a particular imbalance. Figure 1.2 shows a simple stack of CPUs. Depending

on the architecture and onboard power electronics, a processor can be mod-

eled as a constant current, constant resistance or constant power load. In

each case, the equations for solving for the node voltages are different. The

following equations solve for the kth node voltage. Each relies on KCL and

KVL of the stack.

Constant Current:

ICPU = I (1.1)

IStack = ICPU + IC (1.2)

IStack =n∑

i=1

ICPUi

Ci

1Ci

(1.3)

Vck =IckCk

t+ V0k (1.4)

3

+−

IStack

VStack

ICPU1

ICPU2

.

.

.

ICPUn

VC1

VC2

VCn

Figure 1.2: A series-stack of CPUs with no DPP applied.

Constant Resistance:

ICPU =VkRk

(1.5)

IStack =VkRk

+ IC (1.6)

IStack =VStack −

∑nk=1EkV0k∑n

k=1Rk(1− Ek)(1.7)

Vck = V0kEk + (1− Ek)IStackRk (1.8)

Ek = e−t

RkCk (1.9)

Constant Power:

ICPU =Pk

Vk(1.10)

IStack =Pk

Vk+ IC (1.11)

4

IStack =n∑

i=1

ICPUi

Ci

1Ci

(1.12)

Vck = ProductLog (1.13)

Equation 1.13 uses a second order Runge-Kutta approximation.

When applied to the same load mismatch, the behavior of each model

becomes apparent. Figure 1.3 shows how each model calculates the node

voltages when presented with the same loads, specifically I1 = .9 A, I2 = .8

A, I3 = 1.2 A and I4 = 1.1 A. The initial voltages were set at 1 V and the

capacitors were set to 10 µF. In the case of constant current, the node voltage

is linear. For constant resistance the node voltage is exponential, as expected

of an RC circuit. The constant power model diverges as a logarithmic func-

tion. Figure 1.4 compares the node voltages directly. Note that all three

models initially follow the same linear divergence from the balanced stack,

and only diverge from each other over time. How quickly they diverge is a

function of the load mismatch and capacitor values. Appendix Section A.1

contains the actual code.

1.3 Element-to-Element Optimal Order

Much as solar cells can be stacked in series to produce a large voltage for

optimal power conversion, loads (specifically CPUs) can also be stacked to

eliminate a conversion stage. The CPU series string faces a challenge similar

to series solar cells in that the series current must be the same through all el-

ements in the string, which is not the typical situation with CPUs processing

varied loads. To compensate for this, differential power processors (DPP) can

be applied to the series stacked CPUs. One topology of DPP is element-to-

element as shown in Figure 1.5. These element-to-element converters transfer

power/current between loads to allow individual CPUs to operate at their

desired voltage and current while still being stacked in series with other loads.

While the element-to-element topology has the benefit of modularity and

relatively low component stress, one downside is that the total power pro-

cessed by the converters for N loads is dependent on the order/position of

5

0 0.5 1 1.5

x 10−5

0.8

1

1.2

1.4Current Model

time

Nod

e V

olta

ge (

V)

Node 1Node 2Node 3Node 4

0 0.5 1 1.5

x 10−5

0.8

1

1.2

1.4Resistor Model

time

Nod

e V

olta

ge (

V)


0 0.5 1 1.5

x 10−5

0

0.5

1

1.5Power Model

time

Nod

e V

olta

ge (

V)


Figure 1.3: Node voltages diverge in the constant current, resistance andpower models.

the loads within the strings. This is evident in the derivations explained

below. However, for stacked CPU loads a central controller can assign the

load currents to desired locations within the stack to minimize the power

processed and the power lost. This section seeks a closed form solution to

6

0 0.5 1 1.5

x 10−5

1

1.2

1.4Node 1

time

Nod

e V

olta

ge (

V)

CurrentResistancePower

0 0.5 1 1.5

x 10−5

1

1.5Node 2

time

Nod

e V

olta

ge (

V)


0 0.5 1 1.5

x 10−5

0

0.5

1Node 3

time

Nod

e V

olta

ge (

V)


0 0.5 1 1.5

x 10−5

0.8

0.9

1Node 4

time

Nod

e V

olta

ge (

V)


Figure 1.4: A comparison of the node voltages of the different models.

the order that minimizes the power processed, given a list of CPU currents

to distribute.

7

+−

DPP1

DPP2

DPP3

IStack

VStack

ICPU1

ICPU2

ICPU3

ICPU4

Id2

ID2

ID1

Id1

Id3

ID3

.

.

.

.

ICPUn

DPPn-1

IDn-1

Id4

.

.

....

.

Figure 1.5: CPU stack with element to element DPP.

8

1.3.1 The Problem

In this analysis, it is assumed that the CPU currents are known and that

they can be assigned to any position within the stack. Given N CPU currents

in a voltage balanced stack with ideal (100% efficient) DPP converters, the

stack current, IStack, will just be the mean of the CPU currents. This can

be derived from a power balance of the whole stack. From Figure 1.5 and

KCL we can express the relationship of the DPP currents (Idi, IDi) in terms

of IStack and CPU current (ICPUi).

Idi − IDi−1 = IStack − ICPUi (1.14)

Since the CPU voltages are matched throughout the string, and if it is

assumed that power transfer between the two nodes is lossless, one can make

the simplification that Idn = IDn.

One can see that the mismatch from the stack current (the average of the

CPU currents in the ideal case) determines the power processed so one can

simplify the right half of the equation to just the mismatch:

Im,i = IStack − ICPUi (1.15)

The whole stack in terms of matrices takes the form:

1 0 0 · · · 0

−1 1 0 · · · 0

0 −1 1 · · · 0...

......

. . ....

0 · · · 0 −1 1

Id1

Id2...

Idn−2

Idn−1

=

Im,1

Im,2

...

Im,n−2

Im,n−1

Solving for the DPP currents:

Id1

Id2...

Idn−2

Idn−1

=

−1 0 0 · · · 0

−1 −1 0 · · · 0

−1 −1 −1 · · · 0...

......

. . ....

−1 −1 −1 · · · −1

Im,1

Im,2

...

Im,n−2

Im,n−1

The power processed by DPP number k is the CPU voltage, Vk, times the

DPP current, Idk. Since this is a voltage balanced stack every Vk is the same:

9

V = VStack/N . Note that the DPP current can be positive or negative but

for this analysis we only care about the magnitude. From this, we can see

that the power processed for each DPP is:

Pk = Vk|Idk| = V |k∑

i=1

Im,i| (1.16)

Total power is then:

Ptotal = Vn−1∑k=1

|k∑

i=1

Im,i| (1.17)

Finally, to bring this back in terms of given variables:

Ptotal = Vn−1∑k=1

|k∑

i=1

∑nj=1 ICPUj

n− ICPUi| (1.18)

Since the CPU currents are given, the problem thus boils down to finding

the ordering of said currents to minimize the sum of the DPP currents, as

given in Equation 1.18. While this can be done with a brute-force approach

the question is whether an closed form solution can be obtained that is less

computationally intensive. The brute force approach is an order N! problem

to solve and very computationally intensive to solve for large stacks. No

closed form solution was found in literature to solve for the optimal order,

but two algorithms were investigated. The first was a “greedy” algorithm

that started with a position in the stack, and found the optimal load for that

position. It then moved on to each position until the stack was populated.

The second was a less computationally complex “interleaved” algorithm that

took advantage of the fact that if two loads of equal but opposite mismatches

are placed side by side then they cancel out as far as the rest of the stack is

concerned. It also took into account that the greatest mismatches should be

placed in the middle of the stack so that they are balanced from above and

below. The interleaved algorithm ordered the loads, and placed the extremes

(largest and smallest loads) in the middle side by side. It then continued to

work its way out on the stack, interleaving positive and negative mismatches.

Figure 1.6 shows the results when simulating 100 random data sets of loads

for a stack of 8 processor loads. As expected, the brute force approach to

try every possible combination of loads results in the lowest average power

processed, but the longest computation time. The greedy algorithm is slightly

10

0 5 10 15 20

10−2

10−1

100

101

AverageFPowerFProcessedF(W)

Com

puta

tionF

Tim

eF(m

S)

PowerFProcessedFvs.FComputationFTime

BruteFForceGreedyInterleavedUnsorted

0

Figure 1.6: Simulation results of the sorting algorithms.

better at finding the optimal order than the interleaved, but at two orders

of magnitude more computation time. Finally, the unsorted result is by far

the fastest, but at more than double the average power processed.

1.4 Voltage Regulation of a Series-Stack

1.4.1 Differential Power Processing

Traditional power architectures process all of the power delivered to a load.

While many advancements have led to increased efficiency in the convert-

ers, the power losses still scale proportionally to the load. By electrically

connecting loads in series, current through the loads is shared from load to

load. However, if the current draws of all loads are not the same then the

voltage at each node will drift. In order to regulate the voltage of each node,

differential power processing can be applied to the stack. Since DPP only

processes the mismatch in load current, the losses are now proportional to

the current mismatches rather than the full system load. In the case of pro-

cessors with similar loads, the current mismatches will be low, leading to

greatly reduced power conversion loss and increased system efficiency. DPP

architectures are typically classified as element-to-element (or load-to-load),

bus-to-element (bus-to-load), or a hybrid of implementations of each [2]. For

11

this work the element-to-element architecture is applied in the form of a SC

ladder converter.

1.4.2 Resonant Ladder SC Converter

The ladder converter is a popular SC topology because all capacitors and

switches share the same low voltage rating, enabling high switching fre-

quency with correspondingly small-sized passives, and high bandwidth con-

trol. When applied to a series-stack, the output capacitors at the load com-

bine with the flying capacitors to form the SC network as shown in Figure 1.7.

The capacitors and switches must be rated to the node voltage, in this case

the input voltage range of the embedded computers (4.5 V-5.5 V). Each flying

capacitor acts as the energy storage element for a differential power processor

and the switches are shared to reduce component count. Resonant operation

can be achieved with the addition of inductors in series with the flying ca-

pacitors. Resonant operation allows for zero current switching, which lowers

switching losses and improves system efficiency. For a given flying capac-

itance, Cf , and a flying inductance, Lf , Equation 1.19 gives the resonant

frequency. Note that this equation is derived assuming a constant voltage at

each node. For a large current mismatch at a given node, this is not a valid

assumption. However, with a sufficiently large output capacitance relative

to the expected maximum current mismatch and the expected change dur-

ing a switching period, the equation gives an adequate approximation for a

switching period that will allow for zero current switching.

fsw =1

2π√LfCf

(1.19)

12

P1

P1

P1

P2

P2

P2

P2

CPU1

EN1

EN1

EN2

EN2

EN3

EN3

EN4

EN4

P1

Cout1

Cout2

Cout3

Cout4

Cf1

Cf2

Cf3

Lf1

Lf2

Lf3

Microcontroller

TI C2000 CPU2

CPU3

CPU4

Level Shifter Gate Driver

S1

S2

S3

S4

S5

S6

S7

S8




Level Shifter

Level Shifter

Level Shifter

Level Shifter

S9

S10

S11

S12

S13

S14

S15

S16

S1S2S3S4S5S6S7S8

S9S10S11S12S13S14S15S16

+−

Vstack

ENs

S17

Level Shifter S17

Hot Swapping Resonant Ladder

Figure 1.7: Ladder converter schematic.

13

CHAPTER 2

EXPERIMENTAL WORK

2.1 Experimental Prototype

Level Shifters Switches

Level Shifters

Power Stage

Hot-Swap Circuitry

Ladder Converter

Figure 2.1: Experimental Prototype.

Figure 2.1 shows an annotated photograph of the experimental prototype.

The TI C2000 microcontroller generates the high resolution PWM waveforms

for the two control signals and uses general purpose I/O signals to enable the

soft-start/hot-swapping circuitry. Level shifters were used to power the gate

14

drivers for the GaN transistors of the converter and to transmit the isolated

control signals. Level shifters were also used to drive the enable switches

directly. Gate drivers were not used for the hot-swapping and enable switches

since the enable switches are high-current, low-speed MOSFETs which do

not require fast switching transitions. Table 2.1 provides a listing of the

components used. For a stack of 4 embedded computers, the stack voltage

was set at 20 V so that a balanced stack would supply 5 V to each load.

Experimental measurements have been done in conventional and resonant

modes of operation, with switching frequencies ranging from 250 kHz to

2 MHz.

DPP Converter TI C2000

Embedded PCs

Measurement System

Measurement Display

Power Supply

Figure 2.2: Test setup.

The stack voltage and four node voltages were measured with the National

Instruments PXIe-4300 data acquisition board. The stack current and four

node currents were measured with 50 mΩ sense resistors, also with a NI

PXIe-4300. All measurements were made with the 10 kHz input low-pass

filter enabled and sampled at 20 kS/s. Current measurements were calibrated

with an Agilent 34410A 6.5 digit DMM to ensure adequate accuracy in the

high efficiency measurements. Figure 2.2 shows an annotated photograph of

the test setup. For all test cases using the ARM R© embedded computers,

the HDMI ports, IO and USB ports were unused to ensure the processor

15

provided the main power draw.

Table 2.1: Component listing of the Resonant Ladder Converter

Component Part Number Parameters

S1 − S8 EPC 2014 40 V, 16 mΩ, 10 ACf1, Cf2, Cf3 CL10A106MQ8NNNC 6.3 V, 10 µFLf1, Lf2, Lf3 LQH31HN54NK03L 54 nH, 35 mΩ, 940 mACout1 − Cout4 CL31A476MPHNNNE 16 V, 47µFGate drivers LM5113 Half-bridge GaN driver

Gate resistors ERJ-2GEJ1R1X 1.1 ΩGate driver Capacitors GRM188R71A474KA61D 10 V, .47 µF,

Level-shifting ADUM5210Micro-controller TMS320F28035

2.2 Experimental Results

2.2.1 Resonant Operation

The component values for flying capacitance and inductance were used with

Equation 1.19 to find an initial estimate for resonant frequency operation on

the prototype. It is well known that ceramic capacitors operating under a

DC bias will suffer from a derating in capacitance, which leads to an increase

in resonant frequency. In addition, parasitic inductance from PCB traces

leads to a decrease in resonant frequency. Due to these component char-

acteristics and parasitics, the resonant frequency was found experimentally

to be 250 kHz. Figure 2.3 shows the inductor current in the case of CPU1

and CPU2 at 100% CPU utilization using the Linux “stress” utility [14] and

CPU3 and CPU4 idle.

For this system, there are two efficiency metrics that characterize the con-

verter performance. The system or “stack” efficiency is the ratio of the power

delivered to the loads (Pout, which represents the sum of all computer input

power) to the power supplied to the system (Pin, drawn from the supply),

given in Equation 2.1:

ηstack =Pout

Pin

(2.1)

16

Figure 2.3: Inductor currents of the ladder converter.

As the DPP converter only processes the mismatch in load currents, it is

not directly proportional to the power supplied to the loads. Therefore the

converter efficiency is a measure of how efficiently the converter processes the

mismatch power, given in Equation 2.2:

ηconverter =Pprocessed − Ploss

Pprocessed

(2.2)

Four embedded computers were stacked in series and balanced by the con-

verter. With the network port connected but the processor idle on all boards,

all node voltages were regulated to within 44 mV of 5 V. Table 2.2 shows

the performance metrics for this case as Case 1. Note that the converter

efficiency is relatively low at 89.7% for this operating mode, which can be

considered an extreme light load case. However, in this case the loads are

well balanced, and the converter does not process much power. This results

in a total stack efficiency of 99.8%. Next, CPU1 and CPU2 were set to 100%

CPU utilization with the Linux ‘stress’ utility while CPU3 and CPU4 were

at idle (Case 2). In this case, the converter efficiency is higher because it is

17

processing more power, but the stack efficiency is decreased to 98.7% because

more total power is lost in processing. With a greater load mismatch, the

node voltages were still held within 90 mV in this scenario. The converter

was designed to handle the full mismatch currents of a stack of embedded

computers so the final test case (Case 3) was to power a single processor. The

node voltage at the powered load (CPU1) was held within 80 mV of 5 V. It

should be noted that this scenario represents a poor use case for the series-

stack architecture, and for which the converter was not optimized. Even so,

the converter still runs at a 94.1% efficiency and the stack efficiency is 92.9%.

The efficiency of the stack is lower than the converter efficiency because in

this case the converter processes more power than the stack delivers to the

loads, as seen in Case 3 of Table 2.2. This is not unexpected in the element-

to-element architecture when the load mismatches are at extremes [2].

Table 2.2: Converter Performance

Metric Case 1 Case 2 Case 3

Pout(W) 5.02 5.35 1.28Ploss (W) 8.8m 89.7m 102mPprocessed (W) 85.8m 1.99 1.71Converter η 89.7% 95.5% 94.1%Stack η 99.8% 98.7% 92.9%

To generate a plot of the converter efficiency, three loads were held constant

at the same load while the fourth was swept from minimal mismatch to a

large mismatch. The power processed varied with the mismatch generated

by the fourth load. Results are shown in Figure 2.4 with a peak efficiency of

98.7%. Note that this is the efficiency of the DPP power conversion (power

loss vs power processed) rather than the efficiency of the stack (power loss

vs power delivered to the loads).

Electronic loads were used to induce current steps to simulate CPU load

transients. Figure 2.5 shows the recorded node voltages in response to the

load currents (Figure 2.6). Initially, all loads are relatively well matched and

thus the node voltages are well balanced. Just before the 10 second mark, the

current in load 2 (I2) drops from above 300 mA to just above 200 mA. This

creates a mismatch, which the converter handles, and keeps the stack node

voltages balanced to within 70 mV. Note that the node voltage, V2, slightly

increased with the drop in current. This is because the drop in current is

18

0 1 2 3 4 575

80

85

90

95

100

Power Processed (W)

Eff

icie

ncy

(%)

Resonant Operation

Figure 2.4: Converter efficiency vs power processed.

equivalent to a rise in load input impedance. This impedance is in series

with the other loads and the stack behaves like a voltage divider. As the

impedance at the lightly loaded CPU is higher than the other loads, the

node voltage is also slightly higher. The DPP converter works to reduce this

mismatch but is not completely successful because of switching losses. At the

15 second mark, I2 returns to the previous load and the stack rebalances. At

the 20 second mark, I3 steps up to above 400 mA and the node voltages again

change. In this case, the impedance of load 3 is the least, so it experiences the

lowest node voltage. In both cases, the converter handles the current steps

without oscillation on the outputs within the measured frequency bandwidth

(10 kHz).

2.2.2 Light Load Operation

While the DPP converter must be able to handle a suitable mismatch load,

in cases where stacked processors are all processing similar loads mismatch

currents are low and DPP is not needed. Matched loads introduce the need

19

0 10 20 304.9

4.95

5

5.05

Stack Voltages

Time (S)

Nod

e V

olta

ge (

V)

V1

V2

V3

V4

V1

V2

V3

V4

V1

V3

Figure 2.5: Node voltages with load transients.

for light load operation of the DPP to further improve the efficiency of the

system. To detect a light load condition, the controller must determine

whether the loads are well balanced. One way to do this would be a current

sense measurement of each load current. However, most practical current

sense measurements for currents at this level are lossy and would lead to

losses proportional to the power process. Another option is to measure just

the mismatch currents, again introducing losses but only proportional to

the mismatch currents. Both methods would require amplified current sense

measurements level-shifted to the node stack voltage.

Rather than add this additional complexity, the scaled node voltages were

measured with the C2000 onboard ADC. As noted previously, under heavy

load the converter is not able to perfectly regulate the node voltages but

under light load the node voltages are well regulated. By sensing the node

voltages the controller is thus able to determine whether to enter light load

operation. In light load operation, the switching frequency was reduced by

10x of the resonant frequency to 25 kHz. This reduction in switching fre-

quency reduces switching losses and further improves efficiency at light loads.

20

0 10 20 300.2

0.25

0.3

0.35

0.4

0.45

0.5Stack Currents

Time (S)

Nod

e C

urre

nt (

A)

I1

I2

I3

I4

Istack

I3

I2

I4

I1

Istack

Figure 2.6: Stack currents during load transients.

Hysteresis control was applied as follows: if all node voltages were within the

hysteresis limit of the average of the node voltages, then the controller went

into light load operation. If any of the node voltages were outside of the hys-

teresis limit then the controller went back into resonant operation. Appendix

Section A.3 contains the code on the C2000 that implements the light load

control.

Figure 2.7 shows the PWM control signals and the resulting inductor cur-

rents of IL3 with 4 embedded PCs operating at idle. In light load operation

the switching frequency is lower, and the inductor current is not resonant but

does show the expected damped LC ringing. When the converter engages

resonant mode the resonant current increases in magnitude as the node volt-

ages are rebalanced before settling back into resonant steady state operation.

Figure 2.8 shows the results with the same loads over a longer period of time.

In this case, the controller leaves light load for only a short period of time

before the nodes are rebalanced and the controller re-enters light load oper-

ation.

As mentioned, light load operation should improve efficiency in cases when

loads are well matched. Figure 2.9 shows the converter efficiency vs. power

21

IL3

Light Load Opera tion Resonant Opera tion

Figure 2.7: In light load operation, switching no longer occurs at the zerocrossing.

processed with light load operation applied for low power processed. For

power processed less than 0.5 W, light load operation is shown to increase

efficiency over resonant operation.

Thus far efficiency plots have not taken into account the power required to

drive the LM5113 gate drivers. As this power is a function of switching fre-

quency and light load operation reduces the average switching frequency, the

gate driver power was recorded for light load and resonant operation modes.

Figure 2.10 shows the measured power to the LM5113 gate drivers for vari-

ous power loads with resonant operation and with light load control enabled.

Since the switching frequency was constant in resonant operation, the power

to the gate drivers was constant relative to the power processed. With light

load control enabled, at lower power processed the controller engaged light

load operation heavily, which led to lower average switching frequency and

lower gate driver power. As the power processed increased, the controller

spent less time in light load operation and the gating power increased until it

converged with the resonant operation. This convergence was expected since

22

Light Load Resonant Light Load

IL3

Figure 2.8: With balanced loads the converter is only briefly in resonantoperation.

the node mismatch was large enough that the controller would never engage

light load mode.

Figure 2.11 shows the efficiency of the converter with the gating losses

included. Light load operation still improved the converter efficiency at low

power processed. Even with gating losses included, the converter reached a

peak efficiency of 97% and a peak stack efficiency of 99.2%.

2.2.3 Hard-Switched Operation

The flying inductors were removed to evaluate the converter in non-resonant

operation. The flying capacitors were kept at the same values for this compar-

ison. The switching frequency was swept and the power losses were measured

to determine an optimal switching frequency. As shown in Figure 2.12, the

ladder converter operated in the slow switching limit [15] up to 100 kHz af-

ter which it entered the fast switching limit. The converter was successfully

operated up to 2 MHz but the efficiency suffered and the switching losses in-

23

0 1 2 3 4 575

80

85

90

95

100

Power Processed (W)

Eff

icie

ncy

(%)

Resonant OperationLight Load Enabled

Figure 2.9: Light load operation improves the converter efficiency whenloads are well balanced.

creased. Appendix Section A.4 contains the code that sweeps the switching

frequency.

The converter was set to a fixed switching frequency of 200 kHz and the

procedure used to characterize the resonant operation was applied to the hard

switched converter. Figure 2.13 compares the resonant operation efficiency

to the non-resonant efficiency across power levels.

2.3 Hot-Swapping

Figure 2.14 shows the hot-swap circuitry implemented for this converter.

The circuit implemented a “high impedance” path that is enabled first. The

high impedance path provides a“soft-start” for the load and limits any input

current pulses resulting from load capacitance. This protects the load and

prevents the converter node voltages from becoming out of balance. The

impedance is provided in the form of a series resistor, Rlimit. After the load

capacitances have charged up, the high impedance path is no longer desired,

24

0 0.5 1 1.5 2 2.5 315

20

25

30

35

Power Processed (W)

Gat

e D

rive

r Po

wer

(m

W)


Figure 2.10: The gate driver power is reduced in light load operation.

so a low impedance path is enabled. The delay to the low impedance path is

provided by a simple RC filter formed by RD and CD shown in Figure 2.14.

The diode is provided to ensure that turn-off is not similarly delayed. For

these tests, RD and CD were set to 30 kΩ and 10 µF respectively to form

an RC time constant of 300 mS. The large delay was introduced not only

to charge up the input capacitors but to account for the power-up delay

incorporated in the PMIC on the embedded computer.

The hot-swap circuitry was tested by removing a single embedded com-

puter from a balanced stack. Figure 2.15 shows the node voltages and

Figure 2.16 shows the node currents during a hot-swap event. At the be-

ginning of the measurement, all embedded computers are connected to the

network but idle, resulting in a well balanced stack. At the 3 second mark,

CPU2 is disconnected from the stack via the hot-swapping circuitry. Note

that in this case, the node voltages were measured at the converter side so

the node voltages show V2 still within limits, but the voltage to CPU2 is 0 V.

The series-stack sees a high impedance at Node 2 so it has the highest volt-

age, but still within the safe operating range of the embedded computer. At

25

0 0.5 1 1.5 2 2.5 30

20

40

60

80

100

Power Processed (W)

Eff

icie

ncy

(%)


Figure 2.11: Efficiency of light load and resonant operation with gate drivelosses included.

the 5 second mark CPU2 is reconnected with a soft start and goes through

the boot process. The voltage mismatch is reduced and the node voltages

further rebalance.

2.4 Series-Stacked Availability Modeling

In an effort to increase the power efficiency of servers, some manufacturers are

moving to multi-processor solutions (such as the HP Moonshot servers [16]).

For many, small, highly parallel operations, these servers can provide better

performance with high energy efficiency when compared to traditional servers

with a single large CPU. Currently these multiple processors are powered

with traditional power electronics, typically a switching step-down converter

in which all of the power to the CPU must flow through the converter. In

this case, the power loss of the system is proportional to the CPU power.

As the CPU power increases, so too does the power loss. By electrically

connecting multiple processors in series, one can power multiple processors

26

101

102

103

10−2

10−1

100

Switching Frequency (kHz)

Pow

er L

oss

(W)


while providing a voltage step-down to meet the input voltage specifications

of the processors [1]. In the case of mismatched loads, differential power

processing (DPP) can be applied to route the mismatch current and regulate

the node voltages. In the case of DPP, the power loss is proportional to

the mismatch (from other CPUs in the stack) in CPU power rather than the

CPU power. This means that if the CPUs are all well matched in power load,

very little power is processed and lost. This mechanism allows for very high

conversion efficiency even when supplying high power to multiple processors.

While there have been many applications of DPP on a series stack [1,2,7,

12, 13] none have performed a detailed analysis on the reliability of the ar-

chitecture compared to a traditional parallel architecture. Figure 2.17 shows

the typical parallel case for four CPUs. Each CPU is powered from a DC-DC

converter in parallel. For reliability analysis, each DC-DC converter will be

considered a component. A system failure will occur when all four DC-DC

converters are down at the same time. Each can be repaired independently.

Figure 2.18 shows a series-stack of four CPUs with a load-to-load [2] DPP

27

0 0.5 1 1.5 2 2.5 30

20

40

60

80

100

Power Processed (W)

Eff

icie

ncy

(%)

Resonant OperationHard Charging Operation


EN+

ENdelay+

RLIMIT

LevelShifter

CPUN+

COUTN+

RLIMIT

LevelShifter

CPUN-

COUTN-

EN+

EN-

EN-

ENdelay-

EN_CPU1

ENdelay+

ENdelay-

RD

RD CD

CD

Figure 2.14: Hotswap circuitry for CPUN .

28

0 2 4 6 8 104.8

4.9

5

5.1

5.2

ConverterdStackdVoltages

Timed(S)

Nod

edV

olta

ged(

V)

V1

V2

V3

V4

V2

V1

V3

V4

Figure 2.15: Node voltages currents while Node 2 is hot-swapped.

structure. Only three DPP converters (specifically, DPP1, DPP2, DPP3) are

needed to balance a stack of four CPUs. Each can be considered a component

with a failure rate. In the case of three DPPs, a single component failure will

result in unsuitable voltage regulation to the CPUs, so a single failure will

result in a system failure. However, the addition of a single DPP, DPP4 in

Figure 2.18, adds a level of redundancy such that two DPPs must fail before

the system fails. This is considered a hybrid DPP. It should be noted that

in this system, it is not feasible to repair a DPP while the system is still in

operation so no repairs will occur until two DPPs have failed.

This section uses Markov models to compare the availability of the paral-

lel, load-to-load, and hybrid systems. Since reliability data are not readily

available for the different converters, relative values are used with sensitivity

analysis added to show the impact of these values. In addition to considering

the mean time to failure (MTTF) for the system, the analysis considers the

average downtime for the four processors in a ten year period. This metric

will give a more relevant comparison of the system architectures and allow for

an analysis of the failure rates that lead to equal downtime for the different

29

0 2 4 6 8 10−0.2

0

0.2

0.4

0.6

0.8

1

1.2Stack Currents

Time (S)

Nod

e C

urre

nt (

A) I

1

I2

I3

I4

Istack

I2

Is tack

Figure 2.16: Nodes currents while Node 2 is hot-swapped.

DC

DC CPU1

DC

DC CPU4

+48V

+48V

Figure 2.17: Traditional parallel architecture.

systems.

2.4.1 Markov Availability Models

The parallel, load-to-load and hybrid architectures result in significantly dif-

ferent Markov availability models. Table 2.3 summarizes the failure and

repair rates for each system.

30

CPU1

CPU2

+48V

DPP1

DPP2

DPP3

CPU3

CPU4

DPP4

Figure 2.18: Series-stacked architecture with DPP.

2.4.2 Parallel Power Supplies

The traditional parallel architecture (Figure 2.17) can be modeled as four

parallel components since computation still takes place unless all four con-

verters are offline at the same time. For the purpose of this analysis, a

best in class 48 V SynQor PQ60120QEx25 48 V to 12 V DC-DC converter

will be used as the comparison. The SynQor converter specifies [17] a mean

time before failure (MTBF) of 106 h leading to a failure rate (λ) of 10−6

failures/hour. This failure rate is extremely low and, when the original cal-

culations were made, led to extremely high reliability. For the purposes of

this analysis, the failure rate was adjusted to 10 × 10−6 h. While a repair

rate is not specified, in a practical case the failing server blade would just

be removed from the rack and replaced with a new functioning unit while

31

Table 2.3: Failure and Repair Rates for Each System

System λ (h−1) µ (h−1)

Parallel 10× 10−6 1Load-to-load 10× 10−6 1Hybrid 10× 10−6 1

the failed unit would be serviced off line. For the purposes of this analysis,

the repair rate (µ) is fixed at 1 repair/h. It is assumed that if multiple com-

ponents have failed, they are all repaired. The incremental time to repair

multiple servers is considered negligible because whether repairing one server

or four, most of the repair time is consumed by dispatching a technician to

perform the repair. Figure 2.19 shows the reduced Markov availability model

of the parallel architecture.

1 2 3 4

4λ

μ

3λ 2λ

μμ

5

λ

μ

Figure 2.19: Markov availability model state-transition diagram for parallelpower supplies.

2.4.3 Load-to-Load Differential Power Processing

In the load-to-load structure (Figure 2.18), if a single DPP converter fails,

the node voltage is not guaranteed to operate within the safe operating range

of the processor. In order to regulate the voltage at a node, a DPP must be

present to conduct mismatch current around a particular node. For example,

if DPP1 fails, the only path for the stack current is through CPU1, so the

voltage at that node cannot be regulated. Therefore, the converters can be

modeled as series connected components for the sake of reliability analysis.

It should be noted that for a stack of N nodes, only N − 1 DPP converters

are needed to regulate the stack. Figure 2.20 shows the Markov availability

model state-transition diagram. There are no commercial power supplies

specifically designed for DPP operations, but the complexity of a typical DPP

32

converter is similar to a traditional switching power converter. In addition,

for the purposes of start-up and extreme mismatches, DPP converters should

be rated to handle full (or potentially double) current of a single processor

but for the majority of their operation will be processing a much smaller

percentage of the rated current. This means that a DPP converter could

not only share failure rates with a similar parallel converter, but in typical

conditions surpass them. For the case of this analysis, the DPP failure rate

is considered equal to the comparison converter, with sensitivity analysis

included later.

1 2

3λ

μ

Figure 2.20: Markov availability model state-transition diagram for theload-to-load DPP structure.

2.4.4 Hybrid Differential Power Processing

The hybrid architecture adds one level of redundancy at the cost of an addi-

tional DPP converter. As shown in Figure 2.18, this redundancy is achieved

by adding DPP4 that regulates the voltage between top and bottom halves

of the stack. In the case mentioned previously, if DPP1 were to fail, the

mismatch current from CPU1 can be processed by DPP4. At first glance, it

appears that DPP1 and DPP3 can fail with DPP4 handling the mismatch

current of each, but in addition to handling the mismatch current the DPP

basically matches the voltages between the two nodes it services. Without

DPP1 or DPP3, there is no mechanism to ensure that the voltages at nodes

1 and 4 match the voltages at nodes 2 and 3. It should be noted that DPP4

in Figure 2.18 has to handle double the voltage of the other DPP converters.

However, for this thesis it is assumed that this converter has the same failure

rate as the other converters. This assumption is made because for practical

33

purposes, the components that make up DPP1, DPP2, and DPP3 would be

rated at higher than the node voltage for the case of start-up or shorts. For

the failure case, it would not be practical to repair a DPP while the stack is

still operating, nor is this study considering detection of a single DPP fail-

ure. Therefore, no repairs will occur until two DPP converters have failed,

causing the system to fail. Figure 2.21 shows the state-transition diagram

for the hybrid DPP architecture.

1 2 3

4λ 3λ

μ

Figure 2.21: Markov availability model state-transition diagram for thehybrid DPP structure.

Equation 2.3 gives the Chapman-Kolmogorov equations for the parallel

architecture, where πi(t) gives the probability of the system being in state i

at time t.

π1(t)

π2(t)

π3(t)

π4(t)

π5(t)

T

=

π0(t)

π1(t)

π2(t)

π3(t)

π4(t)

T

×

−4λ 4λ 0 0 0

µ −(3λ+ µ) 3λ 0 0

µ 0 −(2λ+ µ) 2λ 0

µ 0 0 −(λ+ µ) λ

µ 0 0 0 −µ

(2.3)

Equation 2.4 gives the Chapman-Kolmogorov equations for the load-to-

load architecture:

[π1(t)

π2(t)

]T

=

[π1(t)

π2(t)

]T

×

[−3λ 3λ

µ −µ

](2.4)

Equation 2.4 gives the Chapman-Kolmogorov equations for the hybrid ar-

chitecture:

34

π1(t)π2(t)

π3(t)

T

=

π1(t)π2(t)

π3(t)

T

×

−4λ 4λ 0

0 −3λ 3λ

µ 0 −µ

(2.5)

2.4.5 Availability Results

Matlab was used to solve the Chapman-Kolmogorov equations given above

for the three different architectures. The long-term probabilities for each

state in the parallel case are given in Table 2.4. As States 1-4 represent

operational states, the long term reliability of this system is virtually 1 (1−2.4× 10−19 to be exact).

Table 2.4: Long-Term Probabilities of the Parallel Structure

State Long-term probability

1 π1 = 0.9999600015999362 π2 = 0.0000399972001483 π3 = 0.0000000011998924 π4 = 0.0000000000000245 π5 = 2.4× 10−19

Table 2.5 shows the long-term probabilities for the states in the load-to-

load architecture. As there are only three converters to fail rather than four

in the cases of the parallel and hybrid structures, the probability of no failures

(π1) is the highest for this case, but as one component failure results in a

system failure the long term availability is the lowest at .99997.

Table 2.5: Long-Term Probabilities of the Load-to-Load DPP Structure


1 π1 = 0.9999700008999732 π2 = 0.000029999100027

The addition of one level of redundancy but no repairs while operating has

an interesting effect on the long-term probabilities, as shown in Table 2.6.

Since repairs do not occur when just a single component has failed, the long

term probability that the system is in a state with a single component failure

(π2) is actually higher than that with no component failures. Also, the one

35

level of redundancy leads to a slightly higher availability (0.99998) than the

load-to-load case.

Table 2.6: Long-Term Probabilities of the Hybrid DPP Structure


1 π1 = 0.4285640817585982 π2 = 0.5714187756781313 π3 = 0.000017142563270

The mean time to failure (MTTF) of each architecture is given in Table 2.7.

Note that the parallel architecture MTTF is high enough that in reality

the failure rate could no longer be considered constant and would be better

modeled as a function decreasing with time. This analysis is not included in

this thesis.

Table 2.7: MTTF for Each Configuration

Configuration MTTF (hours)

Parallel 4.24× 1018

Load-to-load 3.33× 104

Hybrid 5.83× 104

A more interesting metric is to look at the total number of down hours over

a ten year period. In the parallel case, recall that the system is considered

operational if a single processor is operational, so some time may be spent

with one or more processors nonoperational. For example, in State 2 only

three processors are operational and in State 3 only two are operational but

both states are considered operating states in this analysis. For both the

load-to-load and hybrid cases, all processors are operational or none are.

Equations 2.6, 2.7, and 2.8 give the number of down hours for the parallel,

load-to-load, and hybrid cases respectively:

downpar = 87660(4− (4π1 + 3π2 + 2π3 + π4)) (2.6)

download = 87660(4− 4π1) (2.7)

downhybrid = 87660(4− (4π1 + 4π2) (2.8)

36

Each equation is derived by considering the number of processors opera-

tional in each state and the probability of the system being in that state.

Table 2.8 shows the results for downtime over a ten year period. This

comparison is much more favorable to the DPP architectures. While the

parallel architecture virtually never has all four processors offline at the same

time, it does spend time with one or more processors down.

Table 2.8: Downtime for Four Processors Operating over 10 Years

Configuration Downtime (hours)

Parallel 3.5064Load-to-load 10.5189Hybrid 6.0109

As stated earlier, as the DPP converters are likely to be overrated for the

typical current that they will be processing, it is reasonable to suggest that

the DPP converters’ failure rate can be lower than that of a traditional power

supply. To determine to what extent the failure rate needs to improve, the

failure rate was swept from 10 × 10−6 to 10 × 10−7. Figure 2.22 shows the

results plotted with the constant downtime of the parallel configuration.

As can be seen, the relationship between the DPP failure rate and down-

time is linear. Using this relationship, the failure rates at which the down-

times for all systems are the same can be found. These results are shown in

Table 2.9. Basically the failure rate of the DPP would need to be one third

of the failure rate of the parallel converter in the load-to-load case and less

than half for that of the hybrid case.

Table 2.9: Failure Rates that Lead to Equal Downtime.

Configuration Failure Rate (h−1)

Parallel 10× 10−6

Load-to-load 3.33× 10−6

Hybrid 5.83× 10−6

Generally speaking, this requirement is within reason as thermal break-

down is a known detriment to long-term reliability. Since the DPP converters

are processing less power, they would have less power loss and less thermal

dissipation than a parallel converter of the same efficiency. However, at the

already low failure rates of the reference supply it becomes harder to make

37

0 0.2 0.4 0.6 0.8 1 1.2

x 10−5

0

2

4

6

8

10

12

DPP Failure Rate (per hour)

Dow

ntim

e (h

ours

)

Load−to−LoadHybridParallel

Figure 2.22: A lower failure rate on DPP converters leads to lowerdowntime.

that argument. It should be noted that this ratio of the failure rates between

the DPP converters and parallel converter that leads to the same downtime

is constant over failure rates. In other words, if you compare the DPPs to

less reliable parallel converters, the DPP converters still need to be one third

and less than one half for the load-to-load and hybrid respectively.

2.4.6 Availability Future Work

This analysis has focused on the availability of the systems, but future work

should incorporate reliability, which was excluded due to space constraints.

For a stack of four processors, only a single DPP is needed for one additional

level of redundancy, but for larger stacks this would not be the most likely

implementation. In order to keep the voltage ratings down the most likely

scenario would be to add an additional hybrid DPP for each additional pair of

processors added. In other words, in addition to the N −1 load-to-load DPP

converters, one would want N/2− 1 hybrid DPP converters. The interesting

38

part of this is that depending on which DPPs failed, it could take more than

two component failures to result in the system failure. The complexity of

the Markov state transition diagram would increase proportionally and could

yield some interesting results.

2.4.7 Availability Conclusion

This section has provided a Markov availability analysis of three methods to

power four processors. The traditional parallel approach processes all of the

power delivered to the loads but exhibits the highest MTTF and availabil-

ity. The load-to-load DPP architecture only processes the load mismatch and

thus may have a lower failure rate but, at the same failure rate as the parallel

case, exhibits the lowest MTTF and availability. Adding one DPP results in

a hybrid DPP structure with one level of redundancy. This hybrid DPP ap-

proach retains the load-to-load benefits of power processing and increases the

MTTF and availability, though not up to the levels of the parallel structure.

In both DPP cases, if the failure rates of the DPP converters can be shown

to be decreased by one third (load-to-load) or less than half (hybrid) of the

parallel converters failure rate, then the availability of the four processors is

equalized.

2.5 Conclusion

This work presented a resonant ladder SC converter that performed differen-

tial power processing on a series-stack of four embedded computers. A model

of a series-stack with no DPP was developed and discussed with respect to

constant current, resistance and power modes. The benefits of DPP, and

specifically of a resonant ladder converter, were analyzed. A prototype was

built using GaN transistors controlled by a TI C2000 microcontroller. Four

embedded computers were powered in a stack and regulated by the resonant

ladder converter with a peak conversion efficiency of 98.1% and a peak stack

efficiency of 99.8%. Hard switching operation was evaluated compared to

resonant operation and found to be less efficient in this converter. Current

steps were induced in loads and the resulting node voltage responses were

discussed. Light load operation was included through hysteresis control and

39

successfully demonstrated efficiency improvements at lower power mismatch.

In addition, an embedded computer was actively hot-swapped from a stack

and successfully reinserted with a soft-start. Finally, the availability of a

series-stacked system was compared to that of a parallel system and it was

found that if the failure rate of the DPP used in a series-stack is half that of

the parallel system, the total downtime in a 10 year period is the same.

40

APPENDIX A

SUPPORT CODE

A.1 Series-Stacked Model

This function calculates an array of stack voltages V , given a number of loads

(N), stack voltage (Vstack), array of loads (Load), array of CPU capacitors

(CCPU), array of initial voltages (V 0), and the load model (CPUModel).

The CPU model (‘current’, ‘resistance’, or ‘dcdc’) determines the units of

the loads.

function V = Series_Model(N, Vstack, Load, Ccpu,t, V0, CPU_Model)

%Initial Calculations

if (~exist(’V0’))

V0 = ones(1,N)*Vstack/N; %Initial voltages if none given,

assumes evenly distributed load

end

if (~exist(’CPU_Model’))

CPU_Model = ’current’; %use current model if none given

end

switch CPU_Model

case ’current’ %constant current model for a CPU

%String current - weighted by the caps, see derivation on page 2 of

%notebook

IStack = sum(Load./Ccpu)/sum(ones(1,N)./Ccpu);

Ic = IStack - Load; %capacitor current

41

V = Ic./Ccpu*t + V0; %assuming Ic is constant, Vc

changes linearly over time

case ’resistance’ %constant resistance model for a CPU

%see derivation in notebook page 16-20

E = exp((-t*ones(1,N))./Ccpu./Load);

IStack = (Vstack - sum(E.*V0))/sum(Load.*(1-E));

V = (V0 - IStack*Load).*E +IStack*Load;

case ’dcdc’ %DC/DC load - basically constant power

%since dv/dt = -P/(CV) + Istack/C, this is a non-linear ODE

%the solution is a Wronskian/Product Log... no fun to work with

%therefore using a 2nd order Runge-Kutta approximation with a time

%step of tStep - this may need to be raised/lowered based on

%accuracy/computation needs. Could also consider Adams-Bashforth

tStep = 1e-9; %time step determines accuracy, might need to

lower this

V = V0;

for i=1:floor(t/tStep)

IStack = sum(Load./V./Ccpu)/sum(ones(1,N)./Ccpu);

f = -Load./Ccpu./V + IStack./Ccpu;

k1 = tStep*f;

k2 = tStep*(-Load./Ccpu./(V+k1) + IStack./Ccpu);

V = V + (k1+k2)/2;

end

otherwise

warning(’Invalid CPU model declared in Series_Model’);

end

end

A.2 Model Test

This code generates plots of the three models with a given mismatch. Uses

the Series-stacked model function above.

42

%model of a bunch of CPUs (Current sources in parallel with caps)

in series

clear; clc

%Inputs

Vstack = 4; %stack voltage in volts

N = 4; %number of processors

t = .5e-6; %timestep

Icpu1 = [.5 .6 .4 .5]; %N CPU load in amps - should this be in PU?

Icpu2 = [1 .6 .4 .5];

Icpu3 = [.5 .6 .4 .5];

C = 1e-6*[10,11,12,13];

V0 = [1,1,1,1];

Vplot1 = zeros(4,N);

Vplot1(1,:) = V0;

V0 = Series_Model(N, Vstack, Icpu1, C, t,V0);

Vplot1(2,:) = V0;


Vplot1(3,:) = V0;


Vplot1(4,:) = V0;

%subplot(3,2,1), plot(Vplot1);

[p1,pt1] = E2E_Power(Icpu1, Vstack);



iter = 28;

ILoad = [.9 .8 1.2 1.1];

V0 = [1,1,1,1];

43

Iplot = zeros(iter+1, N);

Icheck = zeros(1, iter+1);

taxis = zeros(1, iter+1);

Iplot(1,:) = V0;

Icheck(1) = sum(V0);

for i = 1:iter

Iplot(i+1,:) = Series_Model(N, Vstack, ILoad, C, t*i, V0,

’current’);

Icheck(i+1) = sum(Iplot(i+1,:));

taxis(i+1) = i*t;

end

figure(1)

set(gca,’FontSize’,14, ’FontName’,’Times New Roman’)

set(gcf,’Color’,’w’)

subplot(3,1,1), plot(taxis,Iplot,’LineWidth’,1.5);


title(’Current Model’)

xlabel(’time’)

ylabel(’Node Voltage (V)’)

hleg1 = legend(’Node 1’,’Node 2’, ’Node 3’, ’Node 4’);

set(hleg1,’Location’,’EastOutside’);

%subplot(3,2,2), plot(taxis,Icheck);

RLoad = 1./[.9 .8 1.2 1.1];

V0 = [1,1,1,1];

Rplot = zeros(iter+1, N);

Rcheck = zeros(1, iter+1);

Rplot(1,:) = V0;

Rcheck(1) = sum(V0);

for i = 1:iter

Rplot(i+1,:) = Series_Model(N, Vstack, RLoad, C, t*i, V0,

’resistance’);

Rcheck(i+1) = sum(Rplot(i+1,:));

44

end

subplot(3,1,2), plot(taxis,Rplot,’LineWidth’,1.5);


title(’Resistor Model’)

xlabel(’time’)




%subplot(3,2,4), plot(taxis,Rcheck);

PLoad = [.9 .8 1.2 1.1];

V0 = [1,1,1,1];

Pplot = zeros(iter+1, N);

Pcheck = zeros(1, iter+1);

Pplot(1,:) = V0;

Pcheck(1) = sum(V0);

for i = 1:iter

Pplot(i+1,:) = Series_Model(N, Vstack, PLoad, C, t, Pplot(i,:),

’dcdc’);

Pcheck(i+1) = sum(Pplot(i+1,:));

end

subplot(3,1,3), plot(taxis,Pplot,’LineWidth’,1.5);


title(’Power Model’)

xlabel(’time’)




%subplot(3,2,6), plot(taxis,Pcheck);

figure(2)


set(gcf,’Color’,’w’)

for i = 1:N

subplot(N,1,i),

45

plot(taxis,Iplot(:,i),taxis,Rplot(:,i),taxis,Pplot(:,i),’LineWidth’,1.5);


top = sprintf(’Node %d’,i);

title(top)

xlabel(’time’)


hleg4 = legend(’Current’,’Resistance’, ’Power’);


end

A.3 PWM and Light Load Operation

This code generates the high resolution PWMs used to control the resonant

converter. It also includes light load control based off of the deviation of the

node voltages.

//###########################################################################

//!

//! \b External \b Connections \n

//! Monitor ePWM1-ePWM4 pins on an oscilloscope as described

//! below:

//! - ePWM1A is on GPIO0

//! - ePWM1B is on GPIO1

//!



//!



//!



#include "DSP2803x_Device.h" // DSP2803x Headerfile

#include "DSP2803x_Examples.h" // DSP2803x Examples Headerfile

46

#include "DSP2803x_EPwm_defines.h" // useful defines for

initialization

#include "DSP28x_Project.h" // Device Headerfile and Examples

Include File

#include "SFO_V6.h"

// Declare your function prototypes here

//---------------------------------------------------------------

void HRPWM1_Config(Uint16);




void HRPWM1_Update(Uint16);


void Adc_Config(void);

__interrupt void MainISR(void);

__interrupt void adc_isr(void);

// General System nets - Useful for debug

Uint16 j, DutyFine, n,update;

Uint32 i;

// Global variables used in this example:

Uint16 LoopCount;

Uint16 ConversionCount;

Uint16 Voltage1[10];




Uint32 temp;

int32 V1;

int32 V2;

int32 V3;

int32 V4;

int32 N1;

int32 N2;

47

int32 N3;

int32 N4;

int32 Vav;

int16 pRes;

int16 pSample;

int16 tol;

int32 llimit;

int32 ulimit;

int32 check;

int32 outbnds;

int32 inbnds;

int32 tav;

int32 t1;

int32 t2;

int32 t3;

int32 t4;

Uint16 PFMflag; // 1 = light load operation, 0 = normal resonant

Uint16 UpdatePeriod;

Uint16 IsrTicker;

void main(void)

PFMflag = 0;

DutyFine = 0;

temp=0;

// *************** Counter Stuff **************************

// Step 1. Initialize System Control:

// PLL, WatchDog, enable Peripheral Clocks

// This example function is found in the DSP2803x_SysCtrl.c file.

InitSysCtrl();

// Step 2. Initalize GPIO:

// This example function is found in the DSP2803x_Gpio.c file and

48

// illustrates how to set the GPIO to its default state.

// InitGpio(); // Skipped for this example

// For this case, just init GPIO for EPwm1-EPwm4

// For this case just init GPIO pins for EPwm1, EPwm2, EPwm3, EPwm4

// These functions are in the DSP2803x_EPwm.c file

InitEPwm1Gpio();

InitEPwm2Gpio();

InitEPwm3Gpio();

InitEPwm4Gpio();

// Step 3. Clear all interrupts and initialize PIE vector table:

// Disable CPU interrupts

DINT;

// Initialize the PIE control registers to their default state.

// The default state is all PIE interrupts disabled and flags

// are cleared.

// This function is found in the DSP2803x_PieCtrl.c file.

InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:

IER = 0x0000;

IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell

Interrupt

// Service Routines (ISR).

// This will populate the entire table, even if the interrupt

// is not used in this example. This is useful for debug purposes.

// The shell ISR routines are found in DSP2803x_DefaultIsr.c.

// This function is found in DSP2803x_PieVect.c.

InitPieVectTable();

// Step 4. Initialize all the Device Peripherals:

// This function is found in DSP2803x_InitPeripherals.c

// InitPeripherals(); // Not required for this example

49

// For this example, only initialize the EPwm

// Step 5. User specific code, enable interrupts:

// counter interupts

// Reassign ISRs.

EALLOW; // This is needed to write to EALLOW protected registers

PieVectTable.EPWM1_INT = &MainISR;

EDIS;

// Enable PIE group 3 interrupt 1 for EPWM1_INT

PieCtrlRegs.PIEIER3.bit.INTx1 = 1;

// Enable CNT_zero interrupt using EPWM1 Time-base

EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable EPWM1INT generation

EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable interrupt

CNT_zero event

EPwm1Regs.ETPS.bit.INTPRD = 1; // Generate interrupt on the 1st

event

EPwm1Regs.ETCLR.bit.INT = 1; // Enable more interrupts

// Enable CPU INT3 for EPWM1_INT:

IER |= M_INT3;

// Enable global Interrupts and higher priority real-time debug

events:

EINT; // Enable Global interrupt INTM

ERTM; // Enable Global realtime interrupt DBGM

update =1;

DutyFine =0;

outbnds = 0;

inbnds = 0;

EALLOW;

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;

50

EDIS;

// Some useful Period vs Frequency values

// SYSCLKOUT = 60 MHz

// ---------------------------

// Period Frequency

// 1000 60 kHz

// 800 75 kHz

// 600 100 kHz

// 500 120 kHz

// 250 240 kHz

// 200 300 kHz

// 100 600 kHz

// 50 1.2 Mhz

// 25 2.4 Mhz

// 20 3.0 Mhz

// 12 5.0 MHz

// 10 6.0 MHz

// 9 6.7 MHz

// 8 7.5 MHz

// 7 8.6 MHz

// 6 10.0 MHz

// 5 12.0 MHz

//====================================================================

// ePWM and HRPWM register initialization

//====================================================================

pRes = 260; //250 for res operation

pSample = 1000;

HRPWM1_Config(pRes); // ePWM1 target, Period = 10


HRPWM3_Config(pSample); // ePWM3 target, Period = 10

HRPWM4_Config(30000000); // ePWM4 target, Period = 20

EPwm1Regs.CMPA.half.CMPAHR = 0; // Left shift by 8 to write into

MSB bits

EPwm2Regs.CMPA.half.CMPAHR = 100 << 8; // Left shift by 8 to write

51

into MSB bits

// ************ ADC Stuff *********************

ConversionCount = 0;

// Interrupts that are used in this example are re-mapped to

// ISR functions found within this file.

EALLOW; // This is needed to write to EALLOW protected register

PieVectTable.ADCINT1 = &adc_isr;

EDIS; // This is needed to disable write to EALLOW protected

registers




InitAdc(); // For this example, init the ADC

Adc_Config();


// Enable ADCINT1 in PIE

PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE

IER |= M_INT1; // Enable CPU Interrupt 1


ERTM; // Enable Global realtime interrupt

DBGM

LoopCount = 0;

// VtHi = 6800;

// VtLo = 5800;

for (i=0;i<100000;i++)

tol = 750;

// start clocks

EALLOW;


EDIS;

52

while (update ==1)

N1 = (Voltage1[0])*64.68-1610; //*8/4

N2 = (Voltage2[0])*48.62-1246; //*6/6

N3 = (Voltage3[0])*32.52-862; //*4/4

N4 = (Voltage4[0])*16.21-435; //*2/4

V1 = N1-N2;

V2 = N2-N3;

V3 = N3-N4;

V4 = N4;

Vav = N1/4;

llimit = Vav - tol;

ulimit = Vav + tol;

check = (V1 > ulimit)||(V1 < llimit)||(V2 > ulimit)||(V2 <

llimit)||(V3 > ulimit)||(V3 < llimit)||(V4 > ulimit)||(V4 <

llimit);

if (check==1)

outbnds++;

temp=0;

if(check==0)

inbnds++;

if ((check==0)&&(temp==0))

temp=1;

for (i=0;i<1000;i++)

if ((check==1)&&(PFMflag ==1))

pRes = 260;

UpdatePeriod = 1;

PFMflag = 0;

for (i=0;i<1000;i++)

else if ((check==0)&&(Vav > 49000)&&(PFMflag == 0)&&temp==1)

pRes = 260*10;

UpdatePeriod = 1;

53

PFMflag = 1;

temp = 0;

// for (i=0;i<10;i++)

void HRPWM1_Config(Uint16 period)

// ePWM1 register configuration with HRPWM

// ePWM1A toggle low/high with MEP control on Rising edge

EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Immediate load

EPwm1Regs.TBPRD = period-1; // PWM frequency =

1 / period

EPwm1Regs.CMPA.half.CMPA = period / 2-1; // set duty 50%

initially

EPwm1Regs.CMPA.half.CMPAHR = (1 << 8); // initialize HRPWM

extension

EPwm1Regs.CMPB = period / 2; // set duty 50%

initially

EPwm1Regs.TBPHS.all = 0;

EPwm1Regs.TBPHS.half.TBPHS = 1; //accounts for delay

EPwm1Regs.TBCTR = 0;

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;

EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; // EPwm1 is the Master

EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;

EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle

low/high

54

EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;

EPwm1Regs.AQCTLB.bit.ZRO = AQ_CLEAR;

EPwm1Regs.AQCTLB.bit.CBU = AQ_SET;

EALLOW;

EPwm1Regs.HRCNFG.all = 0x0;

EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on Rising

edge

EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP;

EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;

EDIS;




EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set Immediate load


1 / period


initially


extension


initially




EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // EPwm2 is the

Master

EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;




55




EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // PWM toggle

high/low - ARS

EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;

EPwm2Regs.AQCTLB.bit.ZRO = AQ_CLEAR;

EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;

EALLOW;


EPwm2Regs.HRCNFG.bit.EDGMODE = HR_REP; //MEP control on

Rising edge



EDIS;



// ePWM3A toggle high/low with MEP control on falling edge

EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load

EPwm3Regs.TBPRD = 1000-1; // PWM frequency = 1

/ period

EPwm3Regs.CMPA.half.CMPA = 1000 / 2; // set duty 50%

initially


extension




EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // EPwm3 is the Master

EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;

56








high/low


EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;

EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;

EALLOW;


EPwm3Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on

falling edge



EDIS;



// ePWM4A toggle high/low with MEP control on falling edge



1 / period

EPwm4Regs.CMPA.half.CMPA = period / 2; // set duty 50%

initially


extension


initially


57



EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // EPwm4 is the

Master

EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;








high/low


EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;

EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;

EALLOW;


EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP; //MEP control on

falling edge



EDIS;

void HRPWM1_Update(Uint16 period)





1 / period


58

initially


extension


initially



void HRPWM2_Update(Uint16 period)





1 / period


initially


extension


initially



void Adc_Config()

EALLOW;

AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 1; // Enable non-overlap

mode. This will eliminate 1st sample issue and improve INL/DNL

performance.

AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; // ADCINT1 trips 1 cycle

prior to ADC result latching into its result register

AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enabled ADCINT1

AdcRegs.INTSEL1N2.bit.INT1CONT = 0; // Disable ADCINT1

Continuous mode

59

AdcRegs.INTSEL1N2.bit.INT1SEL = 3; // setup EOC5 to trigger

ADCINT1 to fire. SEE below two lines. This is why EOC5 sets

ADCINT1- it corresponds to the last conversion

AdcRegs.ADCSOC0CTL.bit.CHSEL = 0;//0;//8; // set SOC0 channel

select to ADCINB0; SOCx can be set to any ADCINyz


select to ADCINB1


select to ADCINB2

AdcRegs.ADCSOC3CTL.bit.CHSEL = 3;//;//11; // set SOC3 channel

select to ADCINB3

AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 9; // set SOC0 start trigger

on EPWM3A


on EPWM3A, due to round-robin SOC0 converts first then SOC1





AdcRegs.ADCSOC0CTL.bit.ACQPS = 20; // set SOC0 S/H Window to 7

ADC Clock Cycles, (6 ACQPS plus 1)







EDIS;

// Assumes ePWM1 clock is already enabled in InitSysCtrl();

EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group

EPwm3Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from CPMA on

upcount

EPwm3Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event

EPwm3Regs.CMPA.half.CMPA = 1500; // Set compare A value

60

EPwm3Regs.TBPRD = 3000; // Set period for ePWM1

EPwm3Regs.TBCTL.bit.CTRMODE = 0; // count up and start

__interrupt void adc_isr(void)

Voltage4[ConversionCount] = AdcResult.ADCRESULT0;




AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //Clear ADCINT1 flag

reinitialize for next SOC

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt

to PIE

return;

//MainISR - interrupts at ePWM1 TBCTR = 0.

// This ISR updates the compare and period registers for all ePWM

modules within the same period.

// User must ensure that the PWM period is large enough to execute

all of the code in the ISR before TBCTR = Period for all ePWM’s.

__interrupt void MainISR(void)

// Sweep frequency coarsely

if(UpdatePeriod==1)

EPwm1Regs.TBPRD = pRes-1;

EPwm1Regs.CMPA.half.CMPA = pRes/2-1; // set duty 50%

EPwm2Regs.TBPRD = pRes-1;

EPwm2Regs.CMPA.half.CMPA = pRes/2-2; // set duty 50%

UpdatePeriod=0;

IsrTicker++;

// Enable more interrupts from this EPWM

EPwm1Regs.ETCLR.bit.INT = 1;

// Acknowledge interrupt to receive more interrupts from PIE group

3

61

PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

A.4 PWM Sweeping

This code generates the high resolution PWMs used to control the resonant

converter. It also sweeps the frequency through the frequency list included.

Only the main code is included, it uses the same function calls as the previous

code.

//###########################################################################

//! \b External \b Connections \n

//! Monitor ePWM1-ePWM4 pins on an oscilloscope as described

//! below:



//!



//!



//!



#include "DSP2803x_Device.h" // DSP2803x Headerfile

#include "DSP2803x_Examples.h" // DSP2803x Examples Headerfile

#include "DSP2803x_EPwm_defines.h" // useful defines for

initialization

#include "DSP28x_Project.h" // Device Headerfile and Examples

Include File

#include "SFO_V6.h"

// Declare your function prototypes here

//---------------------------------------------------------------

62







void Adc_Config(void);

__interrupt void MainISR(void);

__interrupt void adc_isr(void);

// General System nets - Useful for debug

Uint16 j, DutyFine, n,update;

Uint32 i;

// Global variables used in this example:

Uint16 LoopCount;

Uint16 ConversionCount;





Uint32 flist[16];

int32 findex;

Uint32 temp;

int32 V1;

int32 V2;

int32 V3;

int32 V4;

int32 N1;

int32 N2;

int32 N3;

int32 N4;

int32 Vav;

int16 pRes;

63

int16 pSample;

int16 tol;

int32 llimit;

int32 ulimit;

int32 check;

int32 outbnds;

int32 inbnds;

int32 tav;

int32 t1;

int32 t2;

int32 t3;

int32 t4;

Uint16 PFMflag; // 1 = light load operation, 0 = normal resonant

Uint16 UpdatePeriod;

Uint16 IsrTicker;

void main(void)

PFMflag = 0;

DutyFine = 0;

temp=0;

findex=0;

// *************** Counter Stuff **************************

// Step 1. Initialize System Control:

// PLL, WatchDog, enable Peripheral Clocks

// This example function is found in the DSP2803x_SysCtrl.c file.

InitSysCtrl();

// Step 2. Initalize GPIO:

// This example function is found in the DSP2803x_Gpio.c file and

// illustrates how to set the GPIO to its default state.

// InitGpio(); // Skipped for this example

// For this case, just init GPIO for EPwm1-EPwm4

64

// For this case just init GPIO pins for EPwm1, EPwm2, EPwm3, EPwm4

// These functions are in the DSP2803x_EPwm.c file

InitEPwm1Gpio();

InitEPwm2Gpio();

InitEPwm3Gpio();

InitEPwm4Gpio();

// Step 3. Clear all interrupts and initialize PIE vector table:

// Disable CPU interrupts

DINT;

// Initialize the PIE control registers to their default state.

// The default state is all PIE interrupts disabled and flags

// are cleared.

// This function is found in the DSP2803x_PieCtrl.c file.

InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:

IER = 0x0000;

IFR = 0x0000;

// Initialize the PIE vector table with pointers to the shell

Interrupt

// Service Routines (ISR).

// This will populate the entire table, even if the interrupt

// is not used in this example. This is useful for debug purposes.

// The shell ISR routines are found in DSP2803x_DefaultIsr.c.

// This function is found in DSP2803x_PieVect.c.

InitPieVectTable();




// For this example, only initialize the EPwm


65

// counter interupts

// Reassign ISRs.

EALLOW; // This is needed to write to EALLOW protected registers

PieVectTable.EPWM1_INT = &MainISR;

EDIS;

// Enable PIE group 3 interrupt 1 for EPWM1_INT

PieCtrlRegs.PIEIER3.bit.INTx1 = 1;

// Enable CNT_zero interrupt using EPWM1 Time-base

EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable EPWM1INT generation

EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable interrupt

CNT_zero event

EPwm1Regs.ETPS.bit.INTPRD = 1; // Generate interrupt on the 1st

event

EPwm1Regs.ETCLR.bit.INT = 1; // Enable more interrupts

// Enable CPU INT3 for EPWM1_INT:

IER |= M_INT3;

// Enable global Interrupts and higher priority real-time debug

events:


ERTM; // Enable Global realtime interrupt DBGM

update =1;

DutyFine =0;

outbnds = 0;

inbnds = 0;

EALLOW;


EDIS;

// Some useful Period vs Frequency values

66

// SYSCLKOUT = 60 MHz

// ---------------------------

// Period Frequency

// 1000 60 kHz

// 800 75 kHz

// 600 100 kHz

// 500 120 kHz

// 250 240 kHz

// 200 300 kHz

// 100 600 kHz

// 50 1.2 Mhz

// 25 2.4 Mhz

// 20 3.0 Mhz

// 12 5.0 MHz

// 10 6.0 MHz

// 9 6.7 MHz

// 8 7.5 MHz

// 7 8.6 MHz

// 6 10.0 MHz

// 5 12.0 MHz

//====================================================================

// ePWM and HRPWM register initialization

//====================================================================

pRes = 200; //250 for res operation

pSample = 1000;



HRPWM3_Config(pSample); // ePWM3 target, Period = 10

HRPWM4_Config(30000000); // ePWM4 target, Period = 20

EPwm1Regs.CMPA.half.CMPAHR = 0; // Left shift by 8 to write into

MSB bits

EPwm2Regs.CMPA.half.CMPAHR = 100 << 8; // Left shift by 8 to write

into MSB bits

67

// ************ ADC Stuff *********************

ConversionCount = 0;

// Interrupts that are used in this example are re-mapped to

// ISR functions found within this file.

EALLOW; // This is needed to write to EALLOW protected register

PieVectTable.ADCINT1 = &adc_isr;

EDIS; // This is needed to disable write to EALLOW protected

registers




InitAdc(); // For this example, init the ADC

Adc_Config();


// Enable ADCINT1 in PIE

PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable INT 1.1 in the PIE

IER |= M_INT1; // Enable CPU Interrupt 1


ERTM; // Enable Global realtime interrupt

DBGM

LoopCount = 0;

// VtHi = 6800;

// VtLo = 5800;

for (i=0;i<100000;i++)

tol = 750;

// start clocks

EALLOW;


68

EDIS;

flist[0] = 50000;

flist[1] = 100000;

flist[2] = 150000;

flist[3] = 200000;

flist[4] = 250000;

flist[5] = 300000;

flist[6] = 400000;

flist[7] = 500000;

flist[8] = 600000;

flist[9] = 800000;

flist[10] = 1000000;

flist[11] = 1200000;

flist[12] = 1400000;

flist[13] = 1600000;

flist[14] = 1800000;

flist[15] = 2000000;

UpdatePeriod =0;

while (update ==1)

// while (UpdatePeriod == 1)

//ensure that period is even

pRes = 30000000/flist[findex];

pRes = pRes*2;

UpdatePeriod = 1;

for(i=0;i<100000;i++)

for(j=0;j<300;j++)

findex = findex+1;

if (findex == 12)

findex = 0;

69

REFERENCES

[1] P. Shenoy, S. Zhang, R. Abdallah, P. Krein, and N. Shanbhag, “Over-coming the power wall: Connecting voltage domains in series,” in EnergyAware Computing (ICEAC), 2011 International Conference on, Nov2011, pp. 1–6.

[2] P. S. Shenoy and P. T. Krein, “Differential power processing for DCsystems,” Power Electronics, IEEE Transactions on, vol. 28, no. 4, pp.1795–1806, April 2013.

[3] E. Candan, P. S. Shenoy, and R. C. Pilawa-Podgurski, “A series-stackedpower delivery architecture with isolated differential power conversionfor data centers,” in Telecommunications Energy Conference (INT-ELEC), 2014 IEEE 36th International. IEEE, 2014, pp. 1–8.

[4] J. McClurg, R. C. Pilawa-Podgurski, and P. S. Shenoy, “A series-stackedarchitecture for high-efficiency data center power delivery,” in EnergyConversion Congress and Exposition (ECCE), 2014 IEEE. IEEE, 2014,pp. 170–177.

[5] J. McClurg, Y. Zhang, J. Wheeler, and R. Pilawa-Podgurski, “Re-thinking data center power delivery: Regulating series-connected voltagedomains in software,” in IEEE Power and Energy Conference at Illinois(PECI), 2013, pp. 147–154.

[6] G. Brainard, “Non-dissipative battery charger equalizer,” Dec. 26 1995,US Patent 5,479,083.

[7] P. Shenoy, B. Johnson, and P. Krein, “Differential power processingarchitecture for increased energy production and reliability of photo-voltaic systems,” in Applied Power Electronics Conference and Exposi-tion (APEC), 2012 Twenty-Seventh Annual IEEE, Feb 2012, pp. 1987–1994.

[8] S. Qin, S. Cady, A. Dominguez-Garcia, and R. Pilawa-Podgurski, “Adistributed approach to maximum power point tracking for photovoltaicsub-module differential power processing,” IEEE Transactions on PowerElectronics, vol. 30, no. 4, pp. 2024–2040, April 2015. [Online]. Available:http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6832650

70

[9] C. Schaef and J. Stauth, “Multilevel power point tracking for partialpower processing photovoltaic converters,” Emerging and Selected Top-ics in Power Electronics, IEEE Journal of, vol. 2, no. 4, pp. 859–869,Dec 2014.

[10] K. Kesarwani, C. Schaef, C. Sullivan, and J. Stauth, “A multi-levelladder converter supporting vertically-stacked digital voltage domains,”in Applied Power Electronics Conference and Exposition (APEC), 2013Twenty-Eighth Annual IEEE, March 2013, pp. 429–434.

[11] C. Schaef and J. Stauth, “Efficient voltage regulation for microprocessorcores stacked in vertical voltage domains,” Power Electronics, IEEETransactions on, vol. PP, no. 99, pp. 1–1, 2015.

[12] J. Stauth, M. Seeman, and K. Kesarwani, “Resonant switched-capacitorconverters for sub-module distributed photovoltaic power management,”Power Electronics, IEEE Transactions on, vol. 28, no. 3, pp. 1189–1198,March 2013.

[13] S. Sanders, E. Alon, H.-P. Le, M. Seeman, M. John, and V. Ng, “Theroad to fully integrated DC-DC conversion via the switched-capacitorapproach,” Power Electronics, IEEE Transactions on, vol. 28, no. 9, pp.4146–4155, Sept 2013.

[14] “Debian packages site.” [Online]. Available: https://packages.debian.org/sid/stress

[15] M. Seeman and S. Sanders, “Analysis and optimization of switched-capacitor DC,” Power Electronics, IEEE Transactions on, vol. 23, no. 2,pp. 841–851, March 2008.

[16] Hewlett Packard, “HP Moonshot System.” [Online]. Avail-able: http://h20565.www2.hp.com/hpsc/doc/public/display?docId=emr na-c03724617

[17] SynQor, “Technical Specification PQ60120QEx25,” Mar. 2015. [Online].Available: www.synqor.com

71

c 2015 andrew r. stillwell - university of illinois urbana

Documents