by: shay amosi & jasmin amitai mentor: mony orbach spring 2013
TRANSCRIPT
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Encryption/Decryption systemMidterm Presentation
By: Shay Amosi & Jasmin Amitai
Mentor: Mony Orbach
Spring 2013
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Our project
Our project goal is to create a hardware
system that
encrypts the data quickly and efficiently.
The system will simulate real-time
encryption
between a PC and USB using FPGA.
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Twofish
The Twofish is a symmetric key 128-bit Block Feistel network.
Twofish can work with variable key length from 128 to 256
bits.
Twofish exhibits fast and versatile performance across most
platforms.
The Twofish structure offers a great deal of flexibility in
terms of space versus speed tradeoffs.
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The Twofish algorithn
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The Twofish algorithn
The Twofish Consists of the following steps:The plaintext is split into 4 words Input Whitening16 rounds of the F functionOutput Whitening
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Implementation methods
Pipeline: Good choice when it comes to performance, best for
pipes that contain pure logic flow without too many stalls resulting from control lines. Requires the use of many resources.
Iterative: Good choice when it comes to cost reduction, best when
we are not required to meet high performance.
Combining both: Good choice when we want to achieve the optimal
performance under resource constraints, yet the implementation is more complex.
f f f f
f
f f
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Pipeline is our choice!
Since the goal of our project as we have defined
earlier is a high-performances, and the core of
our hardware performs many serial permutations and logic calculations,
the right choice is to pipe our computational
unit.
During the project we will have to match the
dimensions of our design to the FPGA’s size.
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TOP LEVEL SCHEME
Fifo in
Twofish
Fifo out
SRAM
Twofish control
Keys ROM
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TWOFISH ALGORITHEM
DATA I
N
f
H
H
PHT
f
H
H
PHT
DATA
OUT
X 16
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Twofish top level
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Twofish control
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Twofish (Encoder/Decoder)
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Twofish pipe
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F-component
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f-function
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H-function
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Interfacing with SRAM
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Hardware environment
FPGA
TWOFISH
FIFOIN
FIFO OUT
CTRL
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Hardware Test
Phase #1: Defining a set of unique inputs as the test blocks to be
encrypted and save the plaintext in a separate file.
Phase #2: Encrypt the set of inputs (henceforth- Twofished blocks).
Phase #3: Save the ciphered text in a separate file and compare it with the
expected output. (This comparison is necessary to verify the correctness of the encryption and avoid possible double errors)
Phase #4: Decrypt the Twofished blocks and compare it to the initial test
blocks via automated script.
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Hardware Test (Phase #1-3)
256KB
256KB
FPGA
TWOFISH
FIFOIN
FIFO OUT
CTRL
PHASE #3
PHASE #1
PLAINTEXT
CIPHERTEXT
PHASE #2
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Hardware Test (Phase #4)
256KB
256KB
FPGA
TWOFISH
FIFOIN
FIFO OUT
CTRL
PLAINTEXT????????
CIPHERTEXT
PHASE #4
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Project timeline
7-2013
• סיו
ם כתי
בת
קוד
ההצפנה T
wofishוכתי
בת
קוד
ה-
Controll
er
8-2013
• תקו
פת
מבחני
ם
9-2013
• קו
מפי
לצי
ה ו
סי
מולצי
ה כללי
ת
ב-
Modelsi
m
9-2013
• בדי
קת
תאי
מו
ת
תכולה
ב-FPGA ו
הו
ספת
השינויי
ם
המתאי
מי
ם
9-2013
• סי
מולצי
ה
הי
קפי
ת
ב-
Modelsi
m
10-
2013
• סינתזה
ב-
Quartus
10-
2013
• הורדת
התכן ל-FPGA
10-
2013
• הרצת
המערכת
בחו
מרה ובניי
ת Tests
מוגדרי
ם
מראש
12-
2013
• בדי
קה וני
תו
ח
בי
צו
עי
ם