by praveen venkataramani 11 techniques for test power reduction in leading edge ip using cadence...
TRANSCRIPT
By Praveen Venkataramani
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Techniques for Test Power Reduction in Leading Edge IP Using Cadence Encounter Test -ATPG:
Objective
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To reduce dynamic power during test in scan based designs
To obtain test vector sequences with minimum switching and pattern count without any loss in test coverage
Overview[1]
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Test power consumption is 3x – 5x the functional power Can cause false failures due to IR drop as a result of high
switching in scan test Shift Power
Cause High toggle during shift
Fix Reduction in overall toggle activity- Use fill techniques
Capture PowerCause
Toggle Activity due to circuit responseFix
Using clock gating technique – Functional clock is gated from areas that are not required for functional operation at that time
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Experimental Setup
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45nm Cortex A8 ARM IP Functional clock - 600 MHz Flop Count – 130,000 Clock Domains – 5 (only 1 Domain with 97%of flops is used
for the experiments) Launch on Capture Length of Scan chains
FULSCAN – 8 chains Average chain length : 17281 flip flops Longest chain length : 17344 flip flops
Compression- 904 chains Average chain length: 152 flip flops Longest chain length: 155 flip flops
Tool Used – Cadence Encounter Test (Cadence ET)Default setting
Compaction Effort – Ultimate Fill – Random fill All Flops switch at capture
Vector Compression
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Vector Compression
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Multiple chips are tested on an automated test equipment (ATE).
Number of available scan channels(ports) from ATE is small compared to the ports in the CUT
Available storage in ATE for test vectorsNeed for decompress and compress the
test vectors used for test
Compression Structure[2]
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Compression Modes
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BroadcastOne channel from the ATE fanouts
(“broadcasts”)to multiple scan chainsUsing XOR gates
The vector on the scan chain is a function of the input and the XOR gates
Broadcast Decompression/Spreader
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Scan Chain 1
Scan Chan 2
Scan Chain 3
Scan Chain n-2
Scan Chain n-1
Scan Chain n
ATE
Broadcast spreader XOR Compression
ATE
Compressed OutputS
can c
hannels
Mask Enable pins
Internal Clock
generator
Scan Enable Pin
Tester clock pin
Masking logic
XOR Spreader and Decompressor
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Scan Chain 1
Scan Chan 2
Scan Chain 3
Scan Chain n-2
Scan Chain n-1
Scan Chain n
Compressed Output
XOR Compression
XOR spreader ATE
Sca
n c
hannels
Mask Enable pins
Internal Clock
generator
Scan Enable Pin
Tester clock pin
Masking logic ATE
Channel Masking
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Channel Masking
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X
X
X
X
XX
X X
XX
From
the S
can c
hain
s
To
ATE
Channel Masking- Types [3]
•Types Wide 0, Wide1, Wide 2•CUT uses Wide2 Mask logic•Contains 2 Mask registers R0 and R1•Mask register is pre-loaded before scan out. •Sets the ‘X’ to value in the Mask bit•Prevents output data from corruption•Some good values could be masked13
Scan Shift Toggle Reduction
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Fill Techniques in Cadence ET[4]
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Toggle activity during scan test is highReduce toggle activity using fill techniques
RandomRepeat‘0’ or ‘1’
Method 1: explicitly specify the fill technique
Method 2: specify the allowed percentage toggle activity
Method 3: Dual fill, combination of repeat and random fill.
Filling of “Don’t-care” Bits- Fullscan Mode (Cadence ET®)
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0
10
20
30
40
50
60
1
356
711
1066
1421
1776
2131
2486
2841
3196
3551
3906
4261
4616
4971
5326
5681
6036
6391
6746
7101
7456
7811
8166
8521
8876
9231
9586
9941
1029
6
1065
1
1100
6
1136
1
1171
6
1207
1
1242
6
1278
1
1313
6
Test Sequence
To
gg
le A
ctiv
ity
Default Setting
Repeat Fill
Zero Fill
Filling of “Don’t-care” Bits- Fullscan Mode (Cadence ET®)
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0
10
20
30
40
50
60
1
184
367
550
733
916
1099
1282
1465
1648
1831
2014
2197
2380
2563
2746
2929
3112
3295
3478
3661
3844
4027
4210
4393
4576
4759
4942
5125
5308
5491
5674
5857
6040
6223
6406
6589
6772
Test sequence
To
gg
le A
ctiv
ity
%
Default setting switching
50% SFF switching
25% SFF switching
Average Toggle Activity during scan shift in Fullscan Mode
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0
10
20
30
40
50
60
0 2000 4000 6000 8000 10000 12000 14000
Test Sequence
To
gg
le A
ctiv
ity
Default Setting
With 50% of scan flops switching
With 25% of scan flops switching
Random fill after TC>70%
Random fill after TC>85%
Repeat fill after TC>70%
Full Repeat Fill
Repeat fill after TC>85% Full Zero Fill
Fault Analysis-Fullscan ModeDynamic Fault Analysis Report
Fill Type Total Faults Test Coverage % Test Sequence
Random 4937768 88.51 6536
Zero 4937768 88.41 13217
Repeat 4937768 88.47 8187
100 4937768 88.51 6536
50 4937768 88.52 6649
25 4937768 88.53 6797
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Summary of Percentage Reduction in Peak Toggle Activity
Fill Type Total Faults
Full Scan Broad Cast XOR Compression
Test sequence increase
% Reduction in Toggle
Test sequence increase
% Reduction in Toggle
Test sequence increase
% Reduction in Toggle
Maxscan_50 5270394 1.02 42.17 1.02 41.17 0.97 0.64
Maxscan_25 5270394 1.04 50.13 0.89 51.30 1.00 9.53
repeat 5270394 1.25 79.72 1.00 53.94 1.02 9.54
one 5270394 1.36 77.01 1.04 54.60 1.03 9.72
zero 5270394 2.02 87.62 1.28 53.23 1.35 14.98
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Average Power Analysis using Synopsys PrimeTime-PX [5]- Fullscan mode
Pattern
Sequential Switching Power (in mW)
Random
Repeat
Initial % Reduction Final % Reduction
3 0.0281 0.0166 40.9 0.0167 40.5
4 0.0293 0.0176 39.9 0.0174 39.9
5 0.0286 0.0176 38.4 0.0174 39.5
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IR Drop Analysis
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IR Drop
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IR Drop occurs due to interconnect resistance between VDD to cell or macro
VDD domains vdd_mpu and vddlsw_mpu result in maximum IR drops
For proper operation of the circuit, the minimum allowable voltage must not be below15% of the reference VDD, in this case 1.08 V.
Max Dynamic IR Drop Gradient map-Random Fill vector
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Max Dynamic IR Drop Gradient map- Repeat Fill Vector
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Switching Histogram- Random Fill Vector
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Switching Histogram- Repeat Fill Vector
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Scan Capture Toggle ReductionReason for toggle during scan captureWhat is clock gating?Results from Cadence ET
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Capture ToggleCapture toggle occurs due to the circuit
responseDifficult to control through scan in vectorsOption- to mask the flip flops that don’t
need to be toggledUse clock gates available in the circuit
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Clock gate Information of the CUT
Test Clock Domain (MHz)
Total Number of Flip flops
Number of flip flops not
controllable with clock gates
Number of flip flops controllable with clock gates
Percentage flip flops
controllable
Lowest Max capture setting
available
200 539 4 535 99.26 1
600 127825 0 127825 100 0
150 64727 2 375 57.96 1
200 749 6 743 99.2 1
150 3859 2117 1742 45.14 230
Toggle Activity during Capture- Fullscan
Compaction EffortMax Permitted Toggle% during
captureMax Toggle activity % observed
during capture
Ultimate
none Specified 41.68
40 41.61
30 41.61
20 41.61
10 41.61
None
none Specified 41.66
40 41.51
30 41.51
20 41.51
10 41.51
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Future work
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Pattern Generation and analysis for reduction in toggle activity during scan capture.
Use the generated vector on ATE to test the CUT
References
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1. Ravi, S. , "Power-aware test: Challenges and solutions," Test Conference, 2007. ITC 2007. IEEE International , vol., no., pp.1-10, 21-26 Oct. 2007 doi: 10.1109/TEST.2007.4437660
2. http://www.cadence.com/rl/Resources/conference_papers/3.7Presentation.pdf
3. Vivek Chickermane, Brian Foutz, and Brion Keller. 2004. Channel Masking Synthesis for Efficient On-Chip Test Compression. In Proceedings of the International Test Conference on International Test Conference (ITC '04). IEEE Computer Society, Washington, DC, USA, 452-461.
4. Encounter Test Low Power user guide
5. Synopsys PrimeTime PX user guide
6. Apache Redhawk user guide
7. “The Power of RTL Clock-gating”, by Mitch Dale, http://chipdesignmag.com/display.php?articleId=915