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IMPROVE LOGIC TEST WITH A HYBRID ATPG/BIST SOLUTION

RON PRESS, VIDYA NEERKUNDAR. MENTOR GRAPHICS

SEPTEMBER 2013

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Improve Logic Test with a Hybrid ATPG/BIST Solution

INTRODUCTIONTwo test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics industry. More recently, the use of logic BIST has increased with the higher demand to be able to test chips in a system or with limited tester interface, such as for burn-in test, board test, and MCM (multi-chip module).

Recently, the differences between the two test approaches have slightly blurred, and now DFT implementations can efficiently share logic between the two approaches. Thus, for some designs, the decision isn’t between using ATPG or logic BIST but to how to use them together. This paper will describe how ATPG and logic BIST work, explain the differences between them, and offer guidelines on when to use one, the other, or a mixture of both.

OVERVIEW OF ATPG To verify the correct fabrication of digital circuits, test engineers apply test patterns created using an ATPG test-creation and compression tool. Patterns are applied to the chip using scan channels at the device’s primary IO pins. This means that the ATPG patterns are stored on the external tester not on the chip itself.

While ATPG requires the use of an external tester, it provides a very high precision of pattern application. By precision, we mean that ATPG provides very specific values with each pattern that allow you to apply tests on specific paths or to control individual clock gaters throughout the design. Thus, ATPG can support specialized fault targeting that improves defect detection, including timing-aware, cell-aware, path delay, bridge, and more. ATPG offers high pattern efficiency, low-power support, high stuck-at coverage, and support for various fault models.

The high number of patterns necessitates the use of embedded compression of the patterns. Compression works by dividing the chip’s scan chains into smaller balanced chains that are connected between a decompressor and a compactor, as shown in Figure 1. Only a small number of primary IOs need to be connected to the external tester in order to apply the compressed ATPG scan patterns. Compressed scan patterns still need to be stored in the external tester, but the volume of data stored is reduced by a couple of orders of magnitude.

Using embedded test compression speeds up test, allows more patterns to target other fault models, and can also reduce the test interface to just a few pins. Today, embedded compression ATPG is the standard approach in most designs.Figure 1. The basic ATPG setup. Compressed test patterns

(stimuli) are sent to the device under test by the automatic test equipment (ATE).

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Improve Logic Test with a Hybrid ATPG/BIST Solution

OVERVIEW OF LOGIC BIST Many designs need to be tested or re-tested on a system or board. For this, you need logic BIST as the pattern generator. The BIST engine is implemented as a physical block on the chip and is activated through an access mechanism like the test access port (TAP), shown in Figure 2. When a device is powered on, BIST can also check that the logic is working properly before starting any functional applications. BIST works by sending out test patterns generated by a pseudo-random pattern generator (PRPG) along scan chains, then collecting the responses to those patterns in a multiple input signature register (MISR). The final content of the MISR is a signature that

determines the pass/fail result. The signature is typically sent out via the TAP then compared to a pre-calculated, or expected, signature.

All of this can be done internally or via a simple interface such as a TAP and does not need an external testing machine to send the test stimuli. Thus, the only patterns that need to be stored on the external tester are instructions to start the BIST, which are very small when compared to the compressed ATPG scan patterns.

Logic BIST provides a few important advantages compared to ATPG. One is that the test can be initiated and verified in any test environment, even if an external tester is not available. This autonomous nature of logic BIST (LBIST) makes it a necessity for field-testing requirements, such as system self-test in a flight control system, satellite, or automobile, as well as some common test environments such as burn-in test.

Another important use of LBIST is for additional detection of “unmodeled” defects for high-quality products. Lastly, LBIST has been very practical for plug-and-play design support. Blocks with LBIST can be reliably reused in any IC without additional run time for pattern generation or risk of unknown coverage. LBIST reduces test time because shift is not limited by external data; patterns are generated on-chip and results are compressed into a simple signature.

COMPARING ATPG AND LOGIC BISTDesigns that require very low defects-per-million (DPM), as in the automotive space or medical field, often require LBIST as one of the test methods in combination with ATPG (possibly in addition to in-house tests). On the design implementation side, LBIST has stricter rules than ATPG. For example, any black-box module or non-scan instance is a source of an unknown value, which LBIST cannot tolerate. During LBIST, any unknown value in the circuit will corrupt some test responses and result in an unpredictable signature. These black-box, or non-scan instances, pose no problem in ATPG because ATPG can ignore any unknown (X) values at the tester. Thus, the design impact is higher for inserting BIST than for ATPG compression.

With the pseudo-random patterns used in LBIST, some faults are difficult to observe and difficult to control. These designs benefit from observe and control testpoints, shown in Figure 3. Testpoints may not be necessary in the deterministic ATPG designs, although in some cases they may help to reduce pattern volume.

Regardless of your method of testing, multi-cycle paths and false paths in the functional design need to be identified and provided as input during test and pattern generation. Typically, these are present in the functional design constraints file, which are read in to a tool like Mentor Graphics’ Tessent FastScan or Tessent TestKompress

Figure 2. Logic BIST setup. The logic BIST physical block contains sequencing logic accessed through the TAP. Random test patterns are generated, loaded into scan chains to test the logic, then collected. The collected responses are compared to expected responses.

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Improve Logic Test with a Hybrid ATPG/BIST Solution

for pattern generation, and are used during ATPG in creating deterministic patterns. ATPG considers multi-cycle paths and false paths when creating patterns to test them at the appropriate frequency or number of capture cycles, or mask their capture points as unknown states when necessary.

To deal with multi-cycle and false paths in LBIST, hardware circuitry can be automatically added on the source flop of a path to hold its value for the desired number of functional clock cycles. The BIST controller then holds the data value during those clock cycles on a per-pattern basis. Synchronous clock domains are honored in both LBIST and ATPG targeted designs so they are tested as designed.

ATPG and LBIST deal with cross-domain communication on asynchronous clocks differently. Cross-domain communication on asynchronous clocks may exist in the design without affecting the functional design, but they do communicate during test and may give undesirable results. During ATPG, you can easily specify how to trigger the clocks, but in LBIST it is less convenient to specify how the clocks are triggered. For testing with LBIST, asynchronous interactions between clock domains need to be managed such that an unknown state cannot be captured, as shown in Figure 4.

Another consideration in test is handling the changes made to the design due to functional ECOs (engineering change orders). If ECOs result in only combinatorial logic changes, then with either ATPG or LBIST, you only need to regenerate the patterns. If the ECOs add only a few functional flops, then the easiest way to handle the new flops in designs targeted with ATPG is to not test them at all, but to mask them. To mask ECO flops when using LBIST, you need to add circuitry to keep them in shift-only, for example, holding the scan_enable high.

Both ATPG and LBIST can achieve the same level of diagnostic resolution, in terms of

applying test to scan chains, flops, and gates. Mostly, the diagnostics with LBIST designs are done off-line after collecting information on failing signatures. For ATPG, the diagnostics can be done on-line during production testing. A design implemented with both test techniques can use ATPG for on-line diagnostics to achieve the desired diagnostic resolution during production test.

Both ATPG and LBIST support low power shift, which is attractive for low and ultra-low power design applications. In both test implementations, there are options to control the toggle rate percentage of the flops during shift and is honored during pattern generation.

Figure 4. Example of logic needed to prevent unknown values from propagating between asynchronous clock domains during logicBIST.

Figure 3. Example of the use of testpoints shows how it can be difficult to produce a logic 0 value at the output of the 3-input AND gate with pseudo-random patterns. The control testpoint (gate) will provide this value via the control flop with random scanned in values.

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Improve Logic Test with a Hybrid ATPG/BIST Solution

DIFFERENCES IN FAULT COVERAGE WITH ATPG AND LBISTThe goal of test is to attain maximum coverage using the fewest number of tester cycles. Fewer cycles mean less test time and less use of tester memory to store patterns. Designs using ATPG scan patterns require multiple sets of patterns to target known fault models like stuck-at, transition, path delay, small delay faults etc. They are capable of achieving very high coverage of those targeted faults. Designs that use LBIST require a single set of patterns that can detect many types of faults in the circuit but with less coverage on faults that need special targeting, such as small delay.

LBIST requires a large number of patterns (in the order of 64k – 150k) to be applied to achieve high stuck-at fault coverage. They are internally produced so there is no tester data impact with the number of LBIST patterns. The N-detect value, which denotes how many times a specific fault has been detected, is very high with LBIST (typically 15 or higher). The N-detect value is positively correlated to defect coverage. As with ATPG, transition fault coverage is very high with LBIST patterns because the circuit is made very testable as part of the LBIST DFT process.

With ATPG, deterministic patterns target a specific fault set, say stuck-at or transition faults, and can be tuned to specific design requirements. Some specific fault sets that require deterministic targeting, like path delay and small delay defect, can be targeted with ATPG deterministic patterns. The pattern set size for ATPG can be high, so embedded compression techniques are commonly used to reduce the pattern application time and data by two orders of magnitude. Embedded compression ATPG is commonplace today.

In ATPG, if a particular flop captures a wrong value because of a design issue, then that flop can be masked (not compared), making the loss of fault coverage mild. In logic BIST however, if a specific flop captures a wrong value there can’t be any masking on the patterns; the entire chain between the PRPG and MISR would be masked. With the specific chain that is causing the X in the MISR being masked with a constant value, the fault coverage can be calculated for the rest of the chains that do capture. The chain masking can be done on the output only or both at the input and output. Some of the key comparisons between LBIST and ATPG, plus benefits of using a hybrid approach, are shown in the table below:

Logic BIST ATPG Combined ATPG/LBIST

Test quality High quality. Additional high N-detect patterns

High quality. Additional detection with patterns for small delay, cell-internal, and other defects

Highest Quality

Design Impact high low high

Test Environment Minimal interface - retest in system and burn-in

Needs a tester - manufacturing test

All environments

Design Type Designs that need re-test on system

Any digital circuit chip Mission critical, such as automotive and medical

Test Application Time Short if design is not pseudo-random resistant

Depends on the number of pattern sets (stuck-at, transition, small delay, path-delay, cell-internal) desired

Shortest. A combination of logic BIST for quick detection and ATPG to top-up the undetected faults

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Improve Logic Test with a Hybrid ATPG/BIST Solution

BENEFITS OF A HYBRID ATPG/LBIST APPROACHSome DFT engineers previously felt compelled to adopt one methodology over the other. However, the two methods really are complementary to each other and can result in the shortest test-time and very high test coverage when used together. For example, shift speed of at-speed deterministic ATPG is limited by the shift path length and the speed of the pad I/O used. At-speed LBIST can significantly increase the speed of the shift clock.

Recently, compressed ATPG and LBIST have offered more common features between them. For example, compressed ATPG now supports a type of plug-and-play capability for blocks that is similar to LBIST reuse with pattern retargeting (using block-level patterns at higher levels). LBIST now supports low-power test similar to what you can do with compressed ATPG. Also, you can now do MISR diagnosis that has the precision of ATPG but uses the LBIST MISR signatures.

The demand for LBIST has increased in recent years, and in most of these cases, users also want compressed ATPG for the reasons mentioned above. As a result, both compressed ATPG and LBIST are increasingly being used together. Using this hybrid ATPG plus LBIST approach has many advantages. For products that need field system test, then this hybrid approach will always be taken because you get high test quality of ATPG with the autonomous testing of LBIST.

Earlier attempts at implementing a hybrid compression ATPG/LBIST methodology had the drawback of using completely separate logic for the LBIST LFSR (linear feedback shift register) and the ATPG compression decompressor (as well as MISR and compression compactor) even though their functional purposes are similar. This presented an obvious opportunity to reap big area savings by combining the logic from embedded compression ATPG and LBIST, as shown in Figure 5. In terms of chip size, a hybrid ATPG/LBIST test structure has minimal area impact because the most common logic of these two test methodologies is now merged.

A more detailed look at the architecture of the hybrid approach, shown in Figure 6, illustrates that compression ATPG and LBIST are shared within each design block, and there is an additional LBIST controller at the top level. The LBIST controller is accessed and managed using the IEEE P1687 IJTAG for plug-and-play control. With the hybrid approach, ATPG only needs to target the faults that are not already detected by LBIST. As a result, we have seen test time savings in the range of 30%.

Figure 5. Hybrid compression ATPG and L BIST shares common test logic.

Figure 6. The hybrid compressed ATPG/LBIST shares logic within each block and has a top-level LBIST controller to manage clocking and sequences of LBIST tests.

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Improve Logic Test with a Hybrid ATPG/BIST Solution

HYBRID ATPG/LBIST TEST METHODOLOGYThe hybrid ATPG/LBIST test methodology supports a top down or bottom-up flow. With a top-down flow, the test logic is inserted from the top-level design and local ATPG/LBIST logic is placed in each block. No other wrapper or isolation logic is needed.

The bottom-up flow is a plug-and-play approach based on the concept of core isolation, which allows having two overlapping modes--external mode and internal mode. In external mode, only the block interface/peripheral registers are connected to dedicated chains. The remaining registers, which are the core registers of the block, are not part of these external chains. The internal mode includes all scannable registers of the blocks inside multiple chains, including the peripheral registers. To fully isolate the block from external logic, the input interface registers are kept in shift-only mode so they do not capture unknown values from the upper level.

When cores are integrated in the top level within a bottom-up flow, Tessent TestKompress reads the patterns previously generated at the core level and retargets them from the top level without requiring any new fault simulation or DRC check. This process is referred to as pattern reuse.

CONCLUSIONUsing a combination of embedded compression ATPG and logic BIST, you can test/retest chips during burn-in and in-system, you get very low DPM, and can check for small delay, timing-aware, cell-aware, and path delay defects. The designs that require both ATPG compression and LBIST can use combined hardware to achieve the test goals by sharing the PRPG and compactor, which provides an additional reduction in hardware cost.

Because more designs are using this hybrid ATPG/LBIST approach, EDA vendors like Mentor Graphics now provide tools to reuse logic between embedded compression ATPG and LBIST. A number of automotive and medical designs are being tested with a combination of deterministic ATPG and pseudo-random LBIST patterns. Results showed the same high coverage as ATPG independently running, but with a shorter test time than when ATPG was run alone. In addition, the LBIST infrastructure makes ATPG and compression more efficient.

The hybrid methodology may require more development time and more chip area to support LBIST, and test time reduction might vary from one block to another. The tradeoff is that adopting a hybrid methodology provides a higher quality test with a high level of flexibility.