bsim: industry standard compact mosfet models

Y. S. Chauhan1 and Chenming Hu2

1IIT Kanpur, India

2UC Berkeley, USA

BSIM: Industry Standard Compact

MOSFET Models

SPICE Transistor Modeling

2

Simulation Time ~ 10μs per DC data point

No complex numerical method

allowed

Accuracy requirements

~ 1% RMS Error after fitting

Excellent Convergence

Example: BSIM-CMG

5,000 lines of VA code

50+ parameters

Open-source software

implemented in major EDA tools

Medium of

information

exchange

Yogesh S. Chauhan, IIT Kanpur

Compact MOSFET Modeling Approaches

Threshold Voltage based Models (e.g. BSIM3,

BSIM4)

Fully Analytical solution (easy to implement) – Fast

Currents expressed as functions of Voltages

Different equations for

Sub-threshold and above-threshold

Linear/saturation regions

Use interpolation function to get smooth current

3

21

2gs

WI C V V V V

Lds ox th ds ds


Compact MOSFET Modeling Approaches

Surface Potential based Models (e.g. PSP, HiSim,

BSIM-CMG, BSIM-IMG)

Implicit equation is solved either iteratively or analytically

Might be slower than threshold voltage based models

Charge based Models (e.g. BSIM5, BSIM6, EKV)

Solve for charge instead of surface potential

No iterations

Faster than Surface Potential based approach with similar

accuracy in charge/current

4

S

VV

V

t

V

toxSsi

ox

siSFBG

t

S

t

CHF

t

S

eeVeVCsignQC

QVV 11)(,

2


Outline

History of BSIM Models

BSIM6 Model

BSIM-CMG Model

BSIM-IMG Model

5Yogesh S. Chauhan, IIT Kanpur


BSIM1 Model

Defined as an engineering model (vs a purely physical model)

Focus on the implementation in circuit simulator

Only a fast demonstration for DC simulation (no attention on

derivatives)

BSIM2 Model

A semi-physical (semi-empirical) model

Improvement over BSIM1 to include better fitting to output

resistance and other first order derivatives

Huge attention placed on parameter extraction methodology

Still being used in many companies as internal model due to its

fitting ability and simple parameter extraction



BSIM3 Model

Starts as a simple physical model with very few parameters

First time – Continuous I-V and derivatives for fast convergence

The 3rd version (BSIM3v3) becomes industry standard

Need to fit many technologies from different foundries – many

new parameters added

Example – Need to have fitting parameters

Due to difficult to describe structural detail

7Source: Mansun ChanYogesh S. Chauhan, IIT Kanpur


BSIM4 model

Started as model for statistical simulation

Priority on physical effects (gate current, mobility models etc.)

Added gate and body resistance networks to emphasize accuracy

on RF simulation

Industry standard in 2000 and most widely used model by

semiconductor industry

Provides better fitting with more number of parameters

BSIM-SOI

Parallel work went on SOI modeling – PD/FD/DD

Real device effects same as BSIM3/BSIM4

Industry standard in 2002


BSIM Family of Compact Device Models

9

BSIM: Berkeley Short-channel IGFET Model

1990 20102000 20051995

BSIM1,2 BSIM3

BSIM4

BSIMSOI

BSIM-MG

BSIM5 BSIM6

Bulk MOSFET

Silicon on Insulator

MOSFET

Multi-Gate MOSFET

New


BSIM6: Charge based MOSFET model

BSIM6 – Next BSIM Bulk MOSFET model Charge based core derived from Poisson’s solution

Real device effects (SCE, CLM etc.) from BSIM4

Parameter names matched to BSIM4

Physical Capacitance model Short channel CV–Velocity saturation & CLM

Symmetry Currents & derivatives are symmetric @ VDS=0

Capacitances & derivatives are symmetric @VDS=0

Provide accurate results in Harmonic Distortion simulation

Continuous in all regions of operations

Better Statistical Modeling using physical parameters10Yogesh S. Chauhan, IIT Kanpur

Physics of BSIM6 Model

Gauss’ Law

Poisson’s solution for long channel MOSFET

Bulk charge density is given by

Combining these, we have



Defining Pinch-off potential ΨP = ΨS, when

Qi=0

For ΨS> few Vt, we have

Inversion Charge linearization

12

ΨP is evaluated

from implicit

equation

nq is the slope

factor

*Ref.: Tsividis book & J.M. Sallese et al., Solid State Electronics



Using linearization approach and normalization

No approximation to solve the charge equation

compared to other models.

Solved the charge equation analytically

13

chfpipii

qq

i vqqqnn

q 222222

ln)ln(

ACM/EKV/BSIM5 ignored

the circled term


Drain current with velocity saturation

Drain current

Mobility model (ensures symmetry)

Using charge linearization & normalization

14

dx

dQV

dx

dQWIII i

TS

idiffdriftD

Lv

V

VCL

Wn

Ii

VCn

Qqn

C

Q

sat

tvc

toxvq

Dd

Toxq

iSPq

ox

i 2,

2

,2

,2

dx

dQV

dx

dQW

dx

d

v

I iT

Si

S

sat

v

vD

2

1

2

22

112

1dsc

ddssd

qq

qqqqi


Normalized Qi-VG & derivatives

15

qi vs VG

1st derivative

2nd derivative

3rd derivative

Red – Numerical Surf. Pot. model

Blue – BSIM6 model


Normalized IDS-VGS & derivatives

16

1st derivative

IDS vs VG

2nd derivative 3rd derivative

Red – Numerical

Surf. Pot. model

Blue – BSIM6 model


Mobility Model

Mobility model has been adopted from BSIM4

17

UCS

bs

is

EU

effbsx

eff

q

q

UDEVUCUA

U

12

1

1

0

MV/cm

where

BSIM4

BSIM6


Saturation Voltage Vdsat

Vds to Vdsat – BSIM4 formulation causes asymmetry

New Vdsat evaluation:

18

eff

teffs

cLVSAT

V2

)1(2

11

2

12

sc

sscdsat

q

qqKSATIVq

1

22ln22

q

qdsatqdsat

dsatfp

t

dsatdsat

n

nqnqq

V

Vv

DELTADELTA

sdsat

ds

dsdseff

VV

V

VV

/1

1


CV Model

19

Physical Capacitance Model

Poly-depletion & Quantum Mechanical Effect

Channel Length Modulation

Velocity Saturation Effect

Charge conservation


Junction capacitance model

BSIM4 junction capacitance model gave

asymmetry

Updated diode junction capacitance model for

AC symmetry

20

Transition

point is at

Vj=0

Transition point is at

Vj=0.9V (pushed to

strong forward bias)


Junction capacitance model

U.C. Berkeley- 21

• Symmetry problem using old Qj

• New model is infinitely

differentiable @ VDS=0

BSIM6

BSIM4

BSIM6

BSIM4

BSIM6

BSIM4


IDS-VX Gummel Symmetry

22

XI

X

X

dV

dI

2

2

X

X

dV

Id

3

3

X

X

dV

Id

4

4

X

X

dV

Id

5

5

X

X

dV

Id 6

6

X

X

dV

Id

7

7

X

X

dV

Id

IX vs VX (VD=VX & VS=-VX)

All derivatives are continuous at VDS=0Yogesh S. Chauhan, IIT Kanpur

AC Symmetry test (C. McAndrew, IEEE TED, 2006)

23

Capacitance & derivatives are symmetric

Capacitances and derivatives are continuous at VDS=0Yogesh S. Chauhan, IIT Kanpur

Validation on Measured Data (Large device)

24

IDVG @ VDS=50mV

IDVG @ VDS=50mV

gmVG @ VDS=50mV

IDVG in saturation

IDVG in saturation gmVG in saturation

IDVDgdsVD IBVG for different VDS


Validation on Measured Data (Short device)

25

IDVG @ VDS=50mV

IDVG @ VDS=50mV gmVG @ VDS=50mV

IDVG in saturation

IDVG in saturation

gmVG in saturation

IDVD gdsVD

IBVG for different VDS


Harmonic Balance Simulation

BSIM6 gives correct slope for all harmonics

26

Slope=1

Slope=2Slope=3

Slope=4 Slope=5


BSIM6 model summary

Rapid development: Released BSIM6.0.0-beta8 in Aug. 2012

Charge based physical compact model

Physical effects & Parameter names matched to BSIM4

Smooth charge/current/capacitance & derivatives

Symmetric and continuous around VDS=0

Fulfills Gummel symmetry and AC symmetry

Shows accurate slope for harmonic balance simulation

BSIM4’s extraction methodology can be easily

used for BSIM6 – fast deployment & lower cost

Under standardization review in CMC


Outline


BSIM6 Model

BSIM-CMG Model

BSIM-IMG Model


Why next generation transistors?

MOSFET becomes “resistor” at small L.

Gate

Source Drain

OxideCg

Cd

C.Hu, “Modern Semicon. Devices for ICs” 2010, Pearson

9/27/201229Yogesh S. Chauhan, IIT Kanpur

Making Oxide Thin is Not Enough

Gate

Source Drain

Leakage Path

Gate cannot control the leakage

current paths that are far from the gate.

C.Hu, “Modern Semicon. Devices for ICs” 2010, Pearson


One Way to Eliminate Si Far from Gate

31

Thin body controlled

By multiple gates.

Gate

Gate

Source Drain

FinFET body

is a thin Fin.N. Lindert et al., DRC paper II.A.6, 2001

Gate Length

So

urc

e

Dra

in

Fin Width

Fin Height

Gate Length


New MOSFET Structures: Demonstration

32

K. Cheng et al. IEDM 2009 - (IBM / ST)

Y. Choi et al. IEEE EDL 2000- (UC Berkeley)X. Huang et al. IEDM 1999 (UC Berkeley)

C.C. Wu et al. IEDM 2010 (TSMC)

FinFETUTBSOI


Challenges in developing a new model

New Physics

Fully depleted channel

Quantum confinement etc.

When to include them?

Support Multiple Device architectures

Inertia with BSIM4 – Large user base

Familiarity with the parameters

Convergence – Model behavior in extreme cases

Balance Physics and Flexibility

Balance Speed and Accuracy


Multi-Gate Compact Model: BSIM-MG

34

Fin

BOX

Ga

te 1

Ga

te 2

BOX

p-sub

P+ back-gate

BSIM-IMG

BSIM-CMG

UTBSOI

BG-ETSOI

FinFETs on Bulk and

SOI Substrates

Vertical Fin

IMG


BSIM-CMG Core Models

Four device architectures

Three core models

Intrinsic Double Gate Core (Y. Taur et al., IEEE EDL, 2004)

Perturbation based DG Core for high-doping

Cylindrical Gate Core

Bulk and SOI Substrate

35

Double Gate Double Gate /

Trigate / FinFET

Quadruple GateCylindrical Gate /

Nanowire FET


Surface Potential Core – Double Gate

Solution of Poisson’s equation and Gauss’s Law.

Poisson’s equation inside the body can be written

as (Vch is channel potential)

Body doping complicates the solution of the

Poisson’s equation.

Perturbation approach is used to solve this problem.

36

NANA

M. Dunga et al., IEEE TED, Vol. 53, No. 9, 2006

M. Dunga et al., VLSI 2007Yogesh S. Chauhan, IIT Kanpur

Core Drain Current Model

No charge sheet approximation

37

0.0 0.5 1.0 1.50

500µ

1m

Vg = 0.9V

Vg = 1.2V

Vg = 1.5V

Na = 3e18cm-3

Dra

in C

urr

en

t (A

)

Drain Voltage (V)0.0 0.5 1.0 1.50

500µ

1m

Dra

in C

urr

en

t (A

)

Gate Voltage (V)

Na = 3e18 cm-3

Vd = 0.1

Vd = 0.2

Vd = 0.4

Vd = 0.6


Core Capacitance Model

Model inherently exhibits symmetry

Cij = Cji @ Vds= 0 V

Model matches TCAD data (No parameter used)

Accurate short channel behavior

38Symbols: TCAD Results; Lines: Model

0.5 1.0 1.50.0

0.5

1.0

Cdg

Csg

Cgg

Na = 3e18cm-3

Vds = 1.5V

Symbols : TCAD

Lines : Model

No

rma

lize

d C

ap

ac

ita

nc

e

Gate Voltage (V)

0.0 0.5 1.0 1.50.0

0.5

1.0

Model

Symmetry

Cgs

CgdCdg

Csg

Cgg

Na = 3e18

Vg = 1.5V

Symbols : TCAD

Lines : Model

No

rmalize

d C

ap

ac

ita

nce

Drain Voltage (V)


Short Channel (2D) Effects

Quasi-2D analysis

Analytical expressions model

39

Characteristic Length

Symbols: TCAD Results; Lines: Model

Auth and Plummer, IEEE EDL, 2007


Quantum Mechanical Effects

Predictive model for confinement induced Vth

shift due to band splitting present in the model

Effective Width model that accounts for reduction

in width for a triple/ quadruple/ surround gate

structure

40

Width reduction due to structural confinement of inversion charge. (Dotted lines represent the effective width perimeter)


FinFET Cfr Modeling – TCAD Verification

41

Cfg: fin gate

Ccg=Ccg1+Ccg2+Ccg3: contact gate

Both Cfg and Ccg agree well with 2D numerical simulations

0 10 20 30 40 50 60 70 800.16

0.18

0.20

0.22

0.24

0.26

Lext

=20nm Lext

=25nm

Lext

=30nm Lext

=35nm

Lext

=40nm

Cfg

(fF

)

Wg (nm)

20 25 30 35 40 45 500.06

0.09

0.12

0.15

Ccg (

fF)

Wg (nm)

Tc = 20nm --> 40nm

in steps of 2nm

Increasing Tc

Fin

Epi

-Si

Gate

Cfg

Ccg2

Ccg1

Wg

Lext

Tc

Ccg3

0 25 50 75 1000.0

0.1

0.2

0.3

0.4

0.5

Tc (nm)

Ccg

1 (

fF)

Increasing Lext

Lext = 15nm --> 40nm

in steps of 5nm

Tc = Wg + Tox

Tox = 1nm

Wfin=1um


Real Device Effects

42

Core

SPE

I-V C-V

Short

Channel

Effects

GIDL Current

Channel Length

Modulation and

DIBL

Mobility

Degradation

Direct tunneling

gate currentOverlap

capacitances

Temperature

Effects

Velocity

Saturation

S/D Resistance/

Parasitic

Resistance

Fringe

Capacitances

Noise models

Impact Ionization

current

Quantum

Effects


Bulk FinFET Fitting

Bulk FinFETs are fabricated by TSMC

TFIN=25nm, HFIN=27.5nm, EOT=2.42nm

43

Drain Current vs. Vgs (Lg = 50nm) Drain Current vs. Vds (Lg = 50 nm) Output Conductance (Lg = 50nm)

0.3 0.6 0.9 1.20

10µ

20µ

30µ

40µ

50µ

Vds = 1.2V

Vds = 50mV

Vds = 1.2V

Vds = 50mV

Lg = 50nm

Dra

in C

urr

ent (A

)

Gate Voltage (V)

1p

1n

1µ

1m

0.0 0.3 0.6 0.9 1.20

10

20

30

40

50

Lg = 50nm

Vgs

= 0.4V

Vgs

= 0.8V

Vgs

= 0.6V

Vgs

= 1.0V

Vgs

= 1.2V

Dra

in C

urr

ent (

A)

Drain Voltage (V)0.0 0.3 0.6 0.9 1.2

10n

1

100 Vgs = 1.2V --> 0.2V

(in steps of 0.2V)

Lg = 50nm

Ou

tpu

t C

on

du

cta

nce

(S

)

Drain Voltage (V)

0.0 0.3 0.6 0.9 1.21p

1n

1

1m

Vgs = 1.2V --> 0.4V

(in steps of 0.2V)

Lg = 0.97 m

Ou

tpu

t C

on

du

cta

nce

(S

)

Drain Voltage (V)

0.0 0.3 0.6 0.9 1.20

200n

400n

600n

800n

L = 0.97 m

Vds = 1.2V

Vds = 50mV

Tra

nsco

nd

ucta

nce

, g

m (

S)

Gate Voltage (V)

0

2µ

4µ

6µ

8µ

10µ

0.0 0.3 0.6 0.9 1.21p

10p

100p

Vds = 1.2V

Lg = 50nm

Sub

str

ate

Cu

rre

nt (A

)

Gate Voltage (V)

Transconductance (Lg = 0.97μm) Output Conductance (Lg = 0.97 μm) Substrate Current (Lg = 50nm)

µ

µ

Symbols: Data

Lines: Model


Asymmetric Vertical Nanowire fittiing

Lg=120nm, D=80nm, Tox=3nm

44

Transconductance Output Conductance Temperature Dependence

Drain Current vs. VdsDrain Current vs. Vgs

Symbols: Data

Lines: Model


Symmetry / Continuity Tests

45

Model passes both DC and AC

Symmetry Tests

Drain Current Capacitances (Cgg and Csd)

C.C.McAndrew, IEEE TED, Vol. 53, No. 9, 2006Yogesh S. Chauhan, IIT Kanpur

BSIM-CMG Summary

BSIM-CMG 106.0.0 is industry standard

production level model – standardized in

March 2012

Available in major EDA tools

Released BSIM-CMG 106.1.0 in Sept. 2012

Physical, Scalable Core Models for multiple

device architectures

Supports both SOI and Bulk Substrates

Many Real Device Effects captured

Validated on Hardware Data from different

technologies46Yogesh S. Chauhan, IIT Kanpur

Outline


BSIM6 Model

BSIM-CMG Model

BSIM-IMG Model


Device Structure & BSIM-IMG

Asymmetric structure

Different Gate Work-functions

Allows dissimilar Gate Potentials

Different Oxide thickness and Material !

Captures important features

Vth tuning through Back-Gate

Multi-Vth technology

48

Source Drain

x

y

NA

Vfg

Tsi

Tox1

Tox2

Back Gate

Front Gate

Vs Vd

VbgYogesh S. Chauhan, IIT Kanpur

Computationally Efficient Core Efficient Non-iterative Surface Potential calculation

Surface potential needs to solved at least twice -

Source and Drain side

Obtain ψs / Qis and ψd / Qid

49

0 2 4 6 8 100

20

40

60

80

100

Iterative

Method B

Cu

mu

lative

Pe

rce

nta

ge

Computational Time ( s)

Iterative

Method A

BSIM-IMG s

FAST

S. Khandelwal et al., "BSIM-IMG: A Compact

Model for Ultra-Thin Body SOI MOSFETs

with Back-Gate Control", IEEE TED, Aug.

2012.


Results: Surface-Potential

50

Comparison with

Numerical Solution Absolute Error (<nV)


Volume Inversion

Preserves Important Property like Volume

Inversion

In sub-threshold (Low field), the charge density Qi is

proportional to the body thickness Tsi

51

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.01E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

-1.0 -0.5 0.0

12345

Qi R

ati

o

sf (V)

Tsi = 5nm

Tsi = 10nm

Tsi = 20nm

Ch

arg

e D

en

sity,

Qi (

co

ul/m

2)

Front Surface Potential, sf (V)

Toxb = 10μm- - - - - - -

- - - - - - -- - - - - - -

Tsi ↑


Drain Current Model

52

dinvsinvssds

dinvsinv

ds QQq

kTQQ

L

WI ,,,1,1

,,

2

2

2

2

22

ssiinv

ssi

EQ

E Qinv: inversion carrier density

Es2: back-side electric field

ψs1: front-side surface potential

Drift Diffusion

0.0 0.2 0.4 0.6 0.8 1.00

50

100

150

200

250

Charge sheet

This Work

TCAD

Vfg = 0.2v, 0.4v, 0.6v, 0.8v, 1.0v

Dra

in C

urr

en

t (

A)

Drain Voltage (V)

-0.5 0.0 0.5 1.0-15

-10

-5

0

5

10

15

Charge-sheet Model

This Work

Err

or

Re

lative

to

TC

AD

(%

)

Front Gate Voltage (V)

No Charge-sheet Approximation Very high accuracy


Length Dependent γ Model

Capacitive coupling ratio

53

0.01 0.1 1

0.18

0.20

0.22

0.24

Ga

mm

a (

)

Gate Length ( m)

TCAD

Model

Vds = 1V

degraded at short channel

Tsi=8nm

Tbox=4nm

Front Gate

Back Gate

Source /

Drain

Cox1

Csi

Cox2

Cd1(Leff)

Cd2(Leff)

-0.2 0.0 0.2 0.4 0.6 0.8 1.010

-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

Vbg

= 10v, 15v,

20v, 25v

Cross: Measurements

Lines: BSIM-IMG

W=50 x 0.5 m

L = 50 nm

Dra

in C

urr

en

t (A

)

Gate Voltage (V)

Captures Vbg effect in I-V


QM Effect: Inv. Charge Centroid Model

54

0

10

20

30

40

50

60

0 0.5 1 1.5

Gate Voltage (V)

Cg

tota

l (f

F/

m^

2)

SCHRED_Clas

BSIM-IMG

SCHRED_QM

BSIM-IMG Fitted

EOTphys = 0.65nm

Tinv = 1.13nm

EOTeff = 0.95nm

Vdd = 0.9 V ; Vfb = 28 mV

TBOX = 140nm; Tsi = 6nm; Nsub = 1e16 cm-3

BOX

p-sub

Vgs↑


Self Heating Model

Thermal Node: Rth/Cth

methodology

Relies on Accurate physical

modeling of Temperature

Effects in the model

55

T

0.0 0.2 0.4 0.6 0.8 1.00

200

400

600

800

1000

Without Self Heating

With Self Heating

Vgs=0.4

Vgs=0.6

Vgs=0.8

Dra

in C

urr

en

t (

A)

Vds (V)

Vgs=1.0

M. A. Karim et al., “Extraction of Isothermal Condition and Thermal Network

in UTBB SOI MOSFETs”, to appear in IEEE Electron Device Letters, 2012.Yogesh S. Chauhan, IIT Kanpur

Global Extraction : Id-Vgs at different Vbg

Vbg=0, -0.2, -0.5, -0.8, -1.1 V; Vds=50mV

L= 11 um, 1.1 um, 270nm, 60 nm, 40 nm, 30 nm

56

TBOX=10nm


Gummel Symmetry Test

57

-0.10 -0.05 0.00 0.05 0.10

-0.06

-0.04

-0.02

0.00

0.02

Vfg=0.8

Vfg=0.6

Vfg=0.4

d3I x

/ d

Vx

3 (

A /

V3)

Vx (V)

Vfg=0.2

Vbg

=0

-0.10 -0.05 0.00 0.05 0.100

4

8

12

16

20

Vbg

=0

dcg

/ d

Vx (

V-1)

Vx (V)

Vfg=0.8

Vfg=0.6

Vfg=0.4

Vfg=0.2

-0.10 -0.05 0.00 0.05 0.100

2

4

6

8

10

dcs

d /

dV

x (V

-1)

Vx

Vbg

=0

Vfg=0.8

Vfg=0.6

Vfg=0.4

Vfg=0.2

C. C. McAndrew, TED 2006

Analog /RF Ready

Drain Current Symmetry

AC (charge) Symmetry


BSIM-IMG: Current Status & Future

Production level UTBSOI Model

Physical and Scalable for FDSOI devices

Plethora of Real Device Effects model

Release of BSIM-IMG 101 (April 2011)

Available in different EDA tools

Already being used by SOI Consortium

Under standardization at Compact Model Council

Verilog-A code and Well-documented Manual

Next BSIM-IMG Release – Oct. 2012


Acknowledgement

Models users

EDA Vendors

Agilent, Cadence

Synopsys, Proplus

Mentor Graphics

SRC/GRC

EPFL

Maria-Anna, Christian Enz

IIT Kanpur

Pragya Kushwaha

Chadan Yadav

Shantanu Agnihotri 59

SOITEC

LETI

ST Microelectronics

Analog Devices

Texas Instruments

IBM

TSMC

Global Foundries

All other CMC

MembersYogesh S. Chauhan, IIT Kanpur

BSIM6 Publications & References S. Venugopalan, K. Dandu, S. Martin, R. Taylor, C. Cirba, X. Zhang, A. M. Niknejad, and C.

Hu; “A non-iterative physical procedure for RF CMOS compact model extraction using BSIM6”; IEEE CICC, Sept. 2012.

M.-A. Chalkiadaki, A. Mangla, C. C. Enz, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Niknejad, C. Hu, "Evaluation of the BSIM6 Compact MOSFET Model’s Scalability in 40nm CMOS Technology", IEEE ESSDERC, Sept. 2012.

Y. S. Chauhan, M. A. Karim, S. Venugopalan, S. Khandelwal, P. Thakur, N. Paydavosi, A. B. Sachid, A. Niknejad and C. Hu, "BSIM6: Symmetric Bulk MOSFET Model", Workshop on Compact Modeling, June 2012.

Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, P. Thakur, N. Paydavosi, A. Niknejad, C. Hu, "BSIM Models: From Multi-Gate to the Symmetric BSIM6", MOS-AK Noida, March 2012.

Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, P. Thakur, N. Paydavosi, A. Niknejad, C. Hu, W. wu, K. Dandu, K. Green, T. Krakowsky, G. Coram, S. Cherepko, S. Sirohi, A. Dutta, R. Williams, J. Watts, M.-A. Chalkiadakim A. Mangla, A. Bazigos, W. Grabinski, C. Enz, "Transitioning from BSIM4 to BSIM6", MOS-AK Noida, March 2012.

Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad, C. Hu, W. wu, K. Dandu, K. Green, G. Coram, S. Cherepko, J. Wang, S. Sirohi, J. Watts, M.-A. ChalkiadakimA. Mangla, A. Bazigos, F. Krummenacher, W. Grabinski, C. Enz, "BSIM6: Symmetric Bulk MOSFET Model", The Nano-Terra Workshop on the next generation MOSFET Compact Models, Lausanne, Switzerland, Dec. 2011.

Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad and C. Hu, "BSIM6: Next generation RF MOSFET Model", MOS-AK Workshop, Washington DC, USA, Dec. 2011.


BSIM-MG Publications & References S. Venugopalan et al.“Compact models for real device effects in FinFETs”; IEEE SISPAD,

Sept. 2012.

M. A. Karim et al., "Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs“, IEEE Electron Device Letters, 2012.

S. Khandelwal et al., "BSIM-IMG: A Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control", IEEE Transactions on Electron Devices, Aug. 2012.

D. D. Lu et al., “A Computationally Efficient Compact Model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates", Solid State Electronics, 2011

S. Venugopalan et al., “BSIM-CG: A Compact Model of Cylindrical/Surround Gate MOSFETs for Circuit Simulations”; Solid State Electronics, Jan 2012.

S. Venugopalan et al., “Modeling Intrinsic and Extrinsic Asymmetry of 3D Cylindrical Gate/ Gate-All-Around FETs for Circuit Simulations”; IEEE NVMTS, China, Nov.2011

D. D. Lu et al., “Multi-Gate MOSFET Compact Model BSIM-MG", a chapter in Compact Modeling Principles, Techniques and Applications, Springer 2010

D. D. Lu et al. "A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation", IEDM 2007.

M. V. Dunga et al., “BSIM-MG: A Compact Model for Multi-Gate Transistors,” a chapter in FinFET and Other Multi-Gate Transistors edited by J. P. Colinge, 2005.

M. A. Karim et al., "BSIM-IMG: Surface Potential based UTBSOI MOSFET Model", Nano-Terra Workshop, Switzerland, Dec. 2011.

S. Venugopalan et al., "BSIM-CMG: Advanced FinFET Model", Nano-Terra Workshop, Switzerland, Dec. 2011.


bsim: industry standard compact mosfet models

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