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EXPLORINGBEAGLEBONE TOOLS AND TECHNIQUES FOR BUILDING WITH EMBEDDED LINUX www.ExploringBeagleBone.com The BeagleBone Black P9 Header s e t o N U P C 0 e d o M 1 e d o M 2 e d o M 3 e d o M 4 e d o M 5 e d o M 6 e d o M 7 e d o M e m a N O I P G R D D A S N I P $ n i P P9_01 44e10000 GND Ground P9_02 Offset from: GND Ground P9_03 44e10800 DC_3.3V 250mA Max Current V 3 . 3 _ C D 4 0 _ 9 P 250mA Max Current V 5 _ D D V 5 0 _ 9 P 1A Max Current V 5 _ D D V 6 0 _ 9 P 1A Max Current V 5 _ S Y S 7 0 _ 9 P 250mA Max Current V 5 _ S Y S 8 0 _ 9 P 250mA Max Current T U B _ R W P 9 0 _ 9 P 5V Level (pulled up PMIC) n T E S E R _ S Y S 0 1 _ 9 P RESET_OUT A10 7 1 T 0 t i a w _ c m p g s r c _ 2 i i m 4 n s c _ c m p g v d _ s r c _ 2 i i m r d c d s _ 1 c m m 2 x u m _ d x r _ 4 t r a u ] 0 3 [ 0 o i p g D X R _ 4 T R A U 0 3 0 7 0 / 0 7 8 x 0 8 2 1 1 _ 9 P All GPIOs to 4-6mA output 8 1 U n 1 e b _ c m p g l o c _ 2 i i m 6 n s c _ c m p g 3 t a d _ 2 c m m r i d _ c m p g 3 x u m _ r k l c a _ 0 p s a c m ] 8 2 [ 1 o i p g 8 2 _ 1 O I P G 0 6 8 7 0 / 8 7 8 x 0 0 3 2 1 _ 9 P and approx. 8mA on input. 7 1 U n p w _ c m p g r r e x r _ 2 i i m 5 n s c _ c m p g r r e x r _ 2 i i m r d c d s _ 2 c m m 2 x u m _ d x t _ 4 t r a u ] 1 3 [ 0 o i p g D X T _ 4 T R A U 1 3 4 7 0 / 4 7 8 x 0 9 2 3 1 _ 9 P 4 1 U 2 a _ c m p g 3 d x t _ 2 i i m 3 d t _ 2 i i m g r 1 t a d _ 2 c m m 8 1 a _ c m p g 1 x u m _ A 1 m w p r h e ] 8 1 [ 1 o i p g A 1 M W P R H E 0 5 8 4 0 / 8 4 8 x 0 8 1 4 1 _ 9 P 3 1 R 0 a _ c m p g n e x t _ 2 i i m g l t c t _ 2 i i m r n e x t _ 2 i i m 6 1 a _ c m p g t u p n i _ e n o z p i r t _ 1 m w p r h e ] 6 1 [ 1 o i p g 6 1 _ 1 O I P G 8 4 0 4 0 / 0 4 8 x 0 6 1 5 1 _ 9 P 4 1 T 3 a _ c m p g 2 d x t _ 2 i i m 2 d t _ 2 i i m g r 2 t a d _ 2 c m m 9 1 a _ c m p g 1 x u m _ B 1 m w p r h e ] 9 1 [ 1 o i p g B 1 M W P R H E 1 5 c 4 0 / c 4 8 x 0 9 1 6 1 _ 9 P 6 1 A 0 s c _ 0 i p s p w d s _ 2 c m m L C S _ 1 C 2 I i c n y s _ 0 m w p r h e d x t _ 0 t r a u _ 1 r p ] 5 [ 0 o i p g L C S _ 1 C 2 I 5 c 5 1 / c 5 9 x 0 7 8 7 1 _ 9 P 6 1 B 1 d _ 0 i p s p w d s _ 1 c m m A D S _ 1 C 2 I e n o z p i r t _ 0 m w p r h e d x r _ 0 t r a u _ 1 r p ] 4 [ 0 o i p g A D S _ 1 C 2 I 4 8 5 1 / 8 5 9 x 0 6 8 8 1 _ 9 P P9_19 95 2 C 2 I d e t a c o l l A 7 1 D n s t r _ 1 t r a u 5 r e m i t x r _ 0 n a c d L C S _ 2 C 2 I 1 s c _ 1 i p s n _ s t r _ 0 t r a u _ 1 r p ] 3 1 [ 0 o i p g L C S _ 2 C 2 I 3 1 c 7 1 / c 7 9 x 0 P9_20 94 2 C 2 I d e t a c o l l A 8 1 D n s t c _ 1 t r a u 6 r e m i t x t _ 0 n a c d A D S _ 2 C 2 I 0 s c _ 1 i p s n _ s t c _ 0 t r a u _ 1 r p ] 2 1 [ 0 o i p g A D S _ 2 C 2 I 2 1 8 7 1 / 8 7 9 x 0 7 1 B 0 d _ 0 i p s d x t _ 2 t r a u L C S _ 2 C 2 I B 0 m w p r h e n _ s t r _ 0 t r a u _ 1 r p 1 x u m _ 3 U M E ] 3 [ 0 o i p g D X T _ 2 T R A U 3 4 5 1 / 4 5 9 x 0 5 8 1 2 _ 9 P 7 1 A k l c s _ 0 i p s d x r _ 2 t r a u A D S _ 2 C 2 I A 0 m w p r h e n _ s t c _ 0 t r a u _ 1 r p 1 x u m _ 2 U M E ] 2 [ 0 o i p g D X R _ 2 T R A U 2 0 5 1 / 0 5 9 x 0 4 8 2 2 _ 9 P 4 1 V 1 a _ c m p g v d x r _ 2 i i m g v d x r _ 2 i i m g r 0 t a d _ 2 c m m 7 1 a _ c m p g o c n y s _ 0 m w p r h e ] 7 1 [ 1 o i p g 7 1 _ 1 O I P G 9 4 4 4 0 / 4 4 8 x 0 7 1 3 2 _ 9 P 5 1 D d x t _ 1 t r a u p w d s _ 2 c m m x r _ 1 n a c d L C S _ 1 C 2 I d x t _ 0 t r a u _ 1 r p 6 1 _ 1 3 r _ u r p _ 0 u r p _ 1 r p ] 5 1 [ 0 o i p g D X T _ 1 T R A U 5 1 4 8 1 / 4 8 9 x 0 7 9 4 2 _ 9 P P9_25 107 0x9ac/1ac 117 GPIO3_21 gpio3[21] pr1_pru0_pru_r31_7 pr1_pru0_pru_r30_7 EMU4_mux2 mcasp1_axr1 mcasp0_axr3 eQEP0_strobe mcasp0_ahclkx A14 Allocated mcasp0_pins 6 1 D d x r _ 1 t r a u p w d s _ 1 c m m x t _ 1 n a c d A D S _ 1 C 2 I d x r _ 0 t r a u _ 1 r p 6 1 _ 1 3 r _ u r p _ 1 u r p _ 1 r p ] 4 1 [ 0 o i p g D X R _ 1 T R A U 4 1 0 8 1 / 0 8 9 x 0 6 9 6 2 _ 9 P P9_27 105 0x9a4/1a4 115 GPIO3_19 gpio3[19] pr1_pru0_pru_r31_5 pr1_pru0_pru_r30_5 EMU2_mux2 mcasp1_fsx mcasp0_axr3 eQEP0B_in mcasp0_fsr C13 Allocated mcasp0_pins P9_28 103 0x99c/19c 113 SPI1_CS0 gpio3[17] pr1_pru0_pru_r31_3 pr1_pru0_pru_r30_3 eCAP2_in_PWM2_out spi1_cs0 mcasp0_axr2 ehrpwm0_synci mcasp0_ahclkr C12 Allocated mcasp0_pins P9_29 101 n i p _ 0 p s a c m d e t a c o l l A 3 1 B x s f _ 0 p s a c m B 0 m w p r h e 0 d _ 1 i p s 1 x u m _ d c d s _ 1 c m m 1 _ 0 3 r _ u r p _ 0 u r p _ 1 r p 1 _ 1 3 r _ u r p _ 0 u r p _ 1 r p ] 5 1 [ 3 o i p g 0 D _ 1 I P S 1 1 1 4 9 1 / 4 9 9 x 0 s P9_30 102 m d e t a c o l l A 2 1 D 0 r x a _ 0 p s a c m e n o z p i r t _ 0 m w p r h e 1 d _ 1 i p s 1 x u m _ d c d s _ 2 c m m 2 _ 0 3 r _ u r p _ 0 u r p _ 1 r p 2 _ 1 3 r _ u r p _ 0 u r p _ 1 r p ] 6 1 [ 3 o i p g 1 D _ 1 I P S 2 1 1 8 9 1 / 8 9 9 x 0 casp0_pins P9_31 100 s a c m d e t a c o l l A 3 1 A x k l c a _ 0 p s a c m A 0 m w p r h e k l c s _ 1 i p s 1 x u m _ d c d s _ 0 c m m 0 _ 0 3 r _ u r p _ 0 u r p _ 1 r p 0 _ 1 3 r _ u r p _ 0 u r p _ 1 r p ] 4 1 [ 3 o i p g K L C S _ 1 I P S 0 1 1 0 9 1 / 0 9 9 x 0 p0_pins C D A V 2 3 _ 9 P 1.8 ADC Volt. Ref. 4 N I A 3 3 _ 9 P C8 1.8V input D N G A 4 3 _ 9 P Ground for ADC 6 N I A 5 3 _ 9 P A8 1.8V input 5 N I A 6 3 _ 9 P B8 1.8V input 2 N I A 7 3 _ 9 P B7 1.8V input 3 N I A 8 3 _ 9 P A7 1.8V input 0 N I A 9 3 _ 9 P B6 1.8V input 1 N I A 0 4 _ 9 P C7 1.8V input 1 1 P f o 1 2 P o t h t o B 4 1 D 1 r t n i _ t n e v e _ a m d x n i k l c t 2 t u o k l c 1 x u m _ 7 r e m i t 6 1 _ 1 3 r _ u r p _ 0 u r p _ 1 r p 0 x u m _ 3 U M E ] 0 2 [ 0 o i p g 2 T U O K L C 0 2 4 b 1 / 4 b 9 x 0 9 0 1 A 1 4 _ 9 P P f o 1 2 P o t h t o B 3 1 D 1 r x a _ 0 p s a c m x e d n i _ 0 P E Q e 0 r x a _ 1 p s a c M 3 u m e 6 _ 0 3 r _ u r p _ 0 u r p _ 1 r p 6 _ 1 3 r _ u r p _ 0 u r p _ 1 r p ] 0 2 [ 3 o i p g 0 2 _ 3 O I P G 6 1 1 8 a 1 / 8 a 9 x 0 B 1 4 _ 9 P 11 P9_42A 89 0x964/164 7 GPIO0_7 gpio0[7] xdma_event_intr2 mmc0_sdwp spi1_sclk pr1_ecap0_ecap_capin_apwm_o spi1_cs1 uart3_txd eCAP0_in_PWM0_out C18 Both to P22 of P11 d e t a c o l l A 2 1 B r k l c a _ 0 p s a c M n i _ A 0 P E Q e 2 r x a _ o p s a c M x k l c a _ 1 p s a c M 4 _ 0 3 r _ u r p _ 0 u r p _ 1 r p 4 _ 1 3 r _ u r p _ 0 u r p _ 1 r p ] 8 1 [ 3 o i p g 8 1 _ 3 O I P G 4 1 1 0 a 1 / 0 a 9 x 0 B 2 4 _ 9 P mcasp0_pins D N G 3 4 _ 9 P - See Pg.50 of the SRM D N G 4 4 _ 9 P Ground D N G 5 4 _ 9 P Ground D N G ) 7 e d o M ( t a c 6 4 _ 9 P Ground P9 $PINS ADDR + GPIO NO. Name Mode 7 Mode 1 Mode 0 CPU Notes

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