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Ching-Yuan Yang

National Chung-Hsing UniversityDepartment of Electrical Engineering

Basic MOS Device Physics

類比電路設計(3349) - 2004

2-1 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Overview

Reading

B. Razavi Chapter 2.

Introduction

In studying the design of integrated circuits, one of two extreme approaches can be taken:

Begin with quantum mechanics and understand solid-state, semiconductor device physics, device modeling, and finally the design of circuits.

Treat each semiconductor device as a black box whose behavior isdescribed in terms of its terminal voltages and currents and design circuits with little attention to the internal operation of the device.

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2-2 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

General considerations

MOSFET as a switchIf the gate voltage, VG, is “high”, the transistor “connects” the source and the drain together.If the gate voltage, VG, is “low”, the transistor “isolates” the source and the drain.

MOSFET structure

2-3 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

MOS deviceSimple NMOS device Simple PMOS device

Cross section of CMOS n-well technology

MOS symbols

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2-4 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Operation of MOSFET

A MOSFET driven by a gate voltage Formation of depletion region

Onset of inversion Formation of inversion layer

2-5 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Threshold voltage

In semiconductor physics, the VTH of an NFET is defined as the gate voltage for which the interface is “as much n-type as the substrate is p-type”.

The threshold voltage can be provided that

φMS is the difference between the work functions of the polysilicon gate and the silicon substrate.

φF = (kT / q)ln(Nsub / ni), q is electron charge, Nsub is the doping concentration of the substrate.

Qdep is the charge in the depletion region.

Cox is the gate oxide capacitance per unit area.

ox

depFMSTH C

QV ++= φφ 2

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2-6 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

I/V characteristics – Triode region

Condition: VDS ≤ VGS − VTHEqual source and drain voltage Unequal source and drain voltage

Derivation

2/: ),( mFCVVWCQ oxTHGSoxd −= ])([)( THGSoxd VxVVWCxQ −−=

dxxdVVxVVWCvVxVVWCvxQI nTHGSoxTHGSoxdD

)(])([])([)( µ−−=⋅−−−=⋅−=

∫ ∫= =−−=

L

x

V

V THGSnoxDDS dxVxVVWCdxI

0 0])([µ x

LVxV DS=)(

2max,

2 )(21

21)( THGSoxnDDSDSTHGSoxnD VV

LWCIVVVV

LWCI −=

−−= µµ and

where

2-7 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Drain current versus drain-source voltage

Linear operation in deep triode region

With the condition VDS << 2(VGS −VTH),-- deep triode region

)(

1

THGSoxn

onVV

LWC

R−

=µ

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2-8 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

I/V characteristics – Saturation region

Condition: VDS ≤ VGS − VTH Pinch-off behavior

Saturated MOSFETs operatingas current sources

2)(21

THGSoxnD VVL

WCI −= µ

2)('2

1THGSoxnD VV

LWCI −= µ

2-9 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Transconductance

For amplification purposes, the transconductance of the device is calculated

MOS transconductance as a function

)(constant

THGSoxnVGS

Dm VV

LWC

VIg

DS

−=∂∂

==

µ

THGS

DDoxn VV

IIL

WC−

==22µ

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2-10 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Conceptual visualization of saturation and triode regions

2-11 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Second-order effects

Body effect

( )FSBFTHTH VVV φφγ 220 −−+=

oxsubSi CNq /2 εγ =wheredenotes the body effect coefficient.

No body effect Body effect

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2-12 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Example: Source follower with (a) no body effect and (b) body effect

Ignoring body effect:

As Vin varies, Vout closely follows the input because the drain current remains equal to I1. It can be written by

( )21 21

THoutinoxn VVVL

WCI −−= µ

2-13 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Channel-length modulation

L’ is a function of VDS.

Writing L’ = L − ∆L, i.e, 1/L’ ≈ (1+ ∆L / L)/L, and assuming ∆L/L = λVDS.

λ : the channel-length modulation coefficient

2)('2

1THGSoxnD VV

LWCI −= µ

)1()(21 2

DSTHGSoxnD VVVL

WCI λµ +−≈

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2-14 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Subthreshold conduction, VGS < VTH

where ζ > 1 is a nonideality factor and VT = kT/q.

If W increases while ID remains constant, then VGS VTH and the device enters the subthreshold region. As a result, the transconductance is calculated to gm = ID /( ζVT ), revealing that MOSFETs are inferior to bipolar transistors.The exponential dependence of ID upon VGS in subthreshold operation may suggestion the use of MOS devices in this regime so as to achieve a higher gain. However, since such conditions are met by only a large device width or low drain current, the speed of subthreshold circuits is severely limited.

T

GSD V

VIIζ

exp0=

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MOS devices

Bird’s eye of a MOS device

Vertical views of a MOS device

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2-16 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

MOS device capacitances

Oxide capacitance between the gate and the channel, C1 = WLCox.Depletion capacitance between the channel and the substrate, .Capacitance due to the overlap of the gate poly with the source and drain areas, C3 and C4.The overlap capacitance per unit width is denoted by Cov .Junction capacitance between the source/drain areas and the substrate.− bottom-plate capacitance associated with the bottom of the junction,

Cj = Cj0 /[1+VR/(2φF)]m.− sidewall capacitance due to the perimeter of the junction, CjSW. (note Cj : F/m2, CjSW : F/m)

)2/(2 FsubSi qNqWLC φε=

S/D junction cap.:

2-17 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Example: Calculate the source and drain junction capacitances

jswjSBDB CEWWECCC )(2 ++==

jswj

jswjSB

jswjDB

CEWWEC

CEWECWC

CEWECWC

)2(22

22

2

22

2

++=

++=

++=

Folded structure:

The geometry of the folded structure in Fig. (b) exhibits substantially less drain junction capacitance than that in Fig. (a) while providing the same W/L.

(a) (b)

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2-18 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Variation of CGS and CGD versus VGS

Example:For VX ≈ 0, M1 is in the triode region, CEN ≈ CEF = (1/2)WLCox + WCov, and CFB is maximum.

2-19 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

MOS small-signal model

Basic MOS small-signal model

Channel-length modulation represented by a depend current source

Channel-length modulation represented by a resistor

GS

Dm V

Ig∂∂

=

( ) DTHGSoxn

DSDD

DSo IVV

LWCVII

Vrλλµ

1

21

1/1

2≈

⋅−=

∂∂=

∂∂

=

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2-20 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Body effect represented by a dependent current source

In the saturation region, gmb can be expressed as

We also have

Thus

where η = gmb/gm .

( )

∂∂

−−=∂∂

=BS

THTHGSoxn

BS

Dmb V

VVVL

WCVIg µ

( ) 2/122

−+−=∂∂

−=∂∂

SBFSB

TH

BS

TH VVV

VV φγ

mSBF

mBS

Dmb g

Vg

VIg η

φγ

=+

⋅=∂∂

=22

2-21 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Example: Sketch gm and gmb of M1 as a function of the bias current I1.

Since , we have .

The dependence of gmb upon I1 is less straightforward.

As I1 increases, VX decreases and so does VSB .

Doxnm ILWCg )/(2µ= 1 Igm ∝

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2-22 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Complete MOS small-signal model

Reduction of gate resistance by folding

2-23 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

MOS SPICE models

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2-24 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

The parameters of Spice models are defined as below: