CHNG I

GVHD: Nguyn Hong Dng BTL:THIT K H THNG S V IC

ti: IU KHIN N GIAO THNG NG T.

Chng I: YU CU CNG NGHI.TNG QUAN V TI:

Ngy nay cng vi s pht trin kinh t, vic th ho cng ang gia tng nhanh chng. Dn n lng phng tin lu thng trong cc th cng tng theo.

Do vn m bo giao thng trong cc th , c bit ti cc nt giao thng din ra thng sut l rt quan trng.

vic i li ti cc nt giao thng c thng sut v thun li th chng ta c th nh n s gip ca lc lng Cnh st giao thng v cc lc lng khc.

Tuy nhin, vi cc th ln c s nt giao thng nhiu th kh c c lc lng m nhim cng vic ny. Mt khc vic nh n s gip ca Cnh st giao thng v cc lc lng khc cng kh khn v tn km.

Ngy nay cng vi s pht trin mnh m ca khoa hc k thut con ngi bit ng dng nhng thnh tu khoa hc k thut vo trong i sng.

n giao thng l mt trong nhng thnh tu . n giao thng l mt h thng n tn hiu hng dn cc phng tin v con ngi tham gia giao thng ti cc nt.

n giao thng ra i t rt lu v chng t cho con ngi thy rng vic s dng n giao thng l khng th thiu trong thi i ngy nay.

Vic iu khin n giao thng c rt nhiu cch, c th dng vi iu khin, dng PLC. S dng FPJA trong iu khin n giao thng c u im:

+ Lm vic chc chn, lin tc v c tui th cao.

+ C th lm vic trong nhiu iu kin khc nhau.

+ Hun luyn ngi s dng n gin.

II.GII THIU CNG NGH CA TI:Trong phm vi ti ny, em thit k chng trnh iu khin n giao thng ng t.

+ H thng n iu khin cc phng tin lu thng trn ng.

Trong :

- H thng iu khin cc phng tin tham gia giao thng trn ng gm 12 n, k hiu (XAC,XBC,VAC,VBC,AC,BC).

- Cc h thng n lm vic ba ch :

+ Ch lm vic bnh thng

+ Ch n vng nhp nhy

+ Ch iu khin ch u tin.

S m phng cch b tr n ti cc nt:

1.Ch lm vic bnh thng:

+Ch ny lm vic vo gi lu lng ngi tham gia giao thng trn ng vi mt bnh thng.

Khi n nt Start khi ng h thng th :

2.Ch vng nhp nhy:

Ch ny lm vic khi lu lng ngi tham gia lu thng trn ng t, nh vo lc khuya.

S dng nt n N3

3.Ch iu khin ch u tin:

CHNG II : GII THIU V VERILOGI.Tng quan v VERILOG.

Verilog l ngn ng m t phn cng (Hardware Description Language) c s dng trong vic thit k cc cc h thng s, cc mch tch hp... Cng vi ngn ng VHDL, Verilog l mt trong hai ngn ng m t phn cng ph bin nht hin nay.Verilogcng c cc c im nh tnh c lp v cng ngh, d dng trong thit k v debug, cng nh tnh n gin so vi cc thit k bng s khi (schematics), c bit l trong vic thit k cc h thng phc tp.

Verilog ln u c gii thiu vo nm 1984 bi cng ty Gateway Design Automatic. Verilog khng c chun ha v u c chnh sa hu ht cc phin bn sau t nm 1984 n nm 1990. Nm 1995 Verilog chnh thc c chun ha bi t chc IEEE.

Nhiu ngi cho rng Verilog d hc v s dng hn VHDL nh c php kh ging vi ngn ng C (ngn ng c dy trong hu ht cc trng i hc, cao ng). Tuy c hai ngn ng Verilog v VHDL u c sinh ra ti M nhng Verilog li c dng ph bin hn ti y.

Verilog c dng xy dng cc ng dng trn nn cc cng ngh nh FPGA, CPLDsCode Verilog dng m t cc h thng s c xy dng trong cc thit b lp trnh c ca cc hng nh Xilinx, Altera, hay Amtel2.Mt s u im ca ngn ng Verilog:

Nn tng mnh : chun ha nm 1995 bi IEEE, h tr cng nghip, ph bin cho cc nh ASIC v d hc, cho php m phng v tng hp hiu qu.

Tnh a nng: cho php qu trnh thit k thc th thc hin trong mi trng thit k c phn tch v kim tra. Tuy nhin Verilog khng thch hp lm cho cc thit k mc h thng phc tp, y l tr ngi chnh ca Verilog.

H tr cng nghip: ph bin cho cc nh thit k ASIC v d hc , cho php m phng nhanh v tng hp hiu qu

C kh nng m rng IEEE Std 1364 cha nh ngha ca PLI Verilog (Programming Language Interface) cho php m rng kh nng ca Verilog. N l mt tp hp cc b nh tuyn cho php cc chc nng bn ngoi truy nhp thng tin chc nng thit k Verilog.3.Phn mm lp trnh ngn ng Verilog

-Quartus II l phn mm h tr tt c mi qu trnh thit k mt mch logic,bao gm qu trnh thit k, tng hp, placement v routing (sp xp v chy dy), m phng (simulation), v lp trnh ln thit b (DE2).

-Nios II, mi trng pht trin tch hp ca h Nios II (IDE), n l cng c

pht trin ch yu ca h vi x l Nios II. Phn mm s l mi trng cung cp

kh nng chnh sa, xy dng, debug v m t s lc v chng trnh. IDE cn

cho php to cc chng trnh t n nhim (single-threaded) n cc chng trnh phc tp da trn mt h iu hnh thi gian thc v cc th vin middleware.4.Gii thiu v BAD DE2 ca ALTERA

a.Gii thiu

Board DE2 l board mch phc v cho vic nghin cu v pht trin v cc

lnh vc lun l s hc (digital logic), t chc my tnh (computer organization)

v FPGA.

b.Thnh phn

+FPGA:

- Vi mch FPGA Altera Cyclone II 2C35.

- Vi mch Altera Serial Configuration EPCS16.

Thc hnh thit kt mch s vi HDL 7 KTMT H. Bch Khoa TP.HCM Khoa KH&KTMT

+Cc thit b xut nhp:

- USB Blaster cho lp trnh v iu khin API ca ngi dung; h tr c 2 ch

lp trnh JTAG v AS.

- B iu khin Cng 10/100 Ethernet.

- Cng VGA-out.

- B gii m TV v cng ni TV-in.

- B iu khin USB Host/Slave vi cng USB kiu A v kiu B.

- Cng ni PS/2 chut/bn phm.

- B gii m/m ha m thanh 24-bit cht lng a quang vi jack cm line-in,

line-out, v microphone.

- 2 Header m rng 40-pin vi lp bo v diode.

- Cng giao tip RS-232 v cng ni 9-pin.

- Cng giao tip hng ngoi.

+B nh:

- SRAM 512-Kbyte.

- SDRAM 8-Mbyte.

- B nh cc nhanh 4-Mbyte (1 s mch l 1-Mbyte).

- Khe SD card.

+Switch, cc n led, LCD, xung clock

- 4 nt nhn, 18 nt gt.

- 18 LED , 9 LED xanh, 8 Led 7 on

- LCD 16x2

- B dao ng 50-MHz v 27-MHz cho ng h ngun.c. Mt vi ng dng ca board DE2

-ng dng lm TV box-Chng trnh v bng chut USB (paintbrush)- My ht Karaoke v my chi nhc SDCHNG III: THIT K CHNG TRNHI. LU THUT TON:1.Ch bnh thng: III.GIN THI GIAN:1. Ch t ng lc bnh thng:

2.Ch lm vic u tin

.

2.Ch n vng nhp nhy

IV.S khi ca chng trnh n Giao Thng

1.u vo v u ra

+u vo:

Xung clock 50Mb.Nt bm Lw thc hin chc nng reset.+u ra:

Led 7 thanh vi chc nng thc hin m thi gian chuyn trng thi.Led n hin th s chuyn trng thi.2.Khi m.Khi m thc hin chc nng m thi gian chuyn qua li gia cc ch lm vic u tin,bnh thng hoc l n vng nhp nhy.3.Khi trng thi.+Khi ng_1bt l trng thi ca ng 1 trong ch lm vic bnh thng.+Khi ng_1ut l trng thi ca ng 1 trong ch lm vic u tin.

+Khi ng_2bt l trng thi ca ng 2 trong ch lm vic bnh thng.

+Khi ng_2ut l trng thi ca ng 2 trong ch lm vic u tin.

4.Khi sepKhi sep l khi thc hin chc nng chia ra hng chc v hng n v hin th ra led 7 thanh

5.Khi seg7Khi seg7 l khi gii m led 7 thanh

Tuyn A

Tuyn B

XAC VBC BC

XAC VAC AC

BC

VBC

XBC

XBC

VBC

BC

Start

n XAC, BC sng ln.

29s

n VAC, BC sng ln

4s

n XBC, AC sng ln.

n VBC, AC sng ln

29s

4s

VAC,VBC sng ln

Khi n N3

3s

VAC,VBC tt

1s

Start

n XAC, BC sng ln.

34s

n VAC, BC sng ln

4s

n XBC, AC sng ln.

n VBC, AC sng ln

29s

4s

ng

Start

I0.0=0

I0.1=1

ng

Sai

I0.0=0;I2.0=1

ng

Q0.1=1;Q0.2=1

I0.0=0

I1.1=1

I1.0=1

Sai

29 s

ng

ng

Q0.3=1;Q0.6=1

Q0.1=0;Q0.2=1;Q0.3=1;

(2)

4 s

Q0.2=0;Q0.3=0;Q0.4=1;

Q0.5=1

3 s

Q0.3=0;Q0.6=0

1 s

ng

ng

Q0.3=1;Q0.6=1

ng

29s

I0.0=0; I2.0=1

Sai

Q0.4=1;Q0.5=0;Q0.6=1

4 s

ng

I0.0=0

I0.1=1

ng

ng

END

Q0.4=0;Q0.6=0;Q0.1=1;

Q0.2=1

Stop

Start

K

K1

K2

K3

K4

K5

K6

T37

T38

T39

T40

29 s

4 s

29 s

4 s

29 s

4 s

29 s

Stop

Start

K

K1

K2

K3

K4

K5

K6

T37

T38

T39

T40

34 s

4 s

29 s

4 s

29 s

4 s

34 s

Stop

N3

K9

K10

K11

T41

T42

3 s

3 s

1 s

1 s

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