IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 24, NO. 6, JUNE 2014 391

Balance-Compensated Asymmetric MarchandBaluns on Silicon for MMICs

Geliang Yang, Zhigong Wang, Senior Member, IEEE, Zhiqun Li, Member, IEEE, Qin Li, and Faen Liu

Abstract—The balance compensating techniques for asymmetricMarchand balun are presented in this letter. The amplitude andphase difference are characterized explicitly by and , fromwhich the factors responsible for the balance compensating are de-termined. Finally, two asymmetric Marchand baluns, which havenormal and enhanced balance compensation, respectively, are de-signed and fabricated in a 0.18 CMOS technology for demon-stration. The simulation and measurement results show that theproposed balance compensating techniques are valid in a very widefrequency range up to millimeter-wave (MMW) band.

Index Terms—Asymmetric, balance compensation, balun,CMOS, millimeter-wave.

I. INTRODUCTION

B ALUN, which splits the single-ended signal into two sig-nals of equal amplitude but 180 out of phase, plays an im-

portant role in balanced circuits. The insertion loss, balance per-formance and area efficiency are the most fundamental concernsespecially in MMW silicon-based balun design. The Marchand-type balun, which is well-known for easy realization and widebandwidth, is normally a preferred choice. Due to a tight cou-pling characteristic, the silicon-based 3-D baluns [1]–[4] featurewider bandwidth than their planar counterpart [5]. However,the common drawback in these works is the inferior in-bandphase balance which can be characterized explicitly by the scat-tering matrix. Nevertheless, only the symmetric baluns [1], [6]was analyzed using such a method. Based on that, a generalcompensation method for improving the baluns’ balance per-formances has been proposed [6]. For asymmetric baluns, anal-ysis simply in terms of port impedance has been presented in [4]which can not explicitly characterize the balun’s balance perfor-mance. In our previously published work [7], theoretical anal-ysis for the balance compensation from a symmetric point ofview has been presented, which cannot be applied for an asym-metric balun. Within this context, we explore the balun’s bal-ance compensating techniques directly using the S-parametersfrom an asymmetric perspective. Finally, two asymmetricMarc-hand baluns, which have normal and enhanced balance com-pensation, respectively, are designed and fabricated in a stan-dard1P6M 0.18 CMOS technology for demonstration.

Manuscript received December 14, 2013; revised February 25, 2014;accepted March 16, 2014. Date of publication April 08, 2014; date of currentversion June 03, 2014. This work was supported by National 973 Project ofChina (2010CB327404).G. Yang was with the Engineering Research Center of RF-ICs and RF-Sys-

tems, Ministry of Education, Nanjing 210096, China and is now with the 54thResearch Institute of China Electronics Technology Group Corporation, Shiji-azhuang 050081, China (e-mail: yglamen@gmail.com).Z. Wang, Z. Li, Q. Li, and F. Liu are with the Engineering Research Center

of RF-ICs and RF-Systems, Ministry of Education, Nanjing 210096, China(e-mail: zgwang@seu.edu.cn).Digital Object Identifier 10.1109/LMWC.2014.2313719

Fig. 1. Block diagram of a traditional asymmetric Marchand balun with twoidentical coupled-line sections.

II. DESIGN METHODOLOGY

A. Traditional Asymmetric Marchand Balun

Fig. 1 schematizes a traditional asymmetric Marchand balunwith two identical coupled-line sections. Taking into accountthe short and open circuit conditions, Sections I and II can berepresented by two scattering matrices according to [8]

(1)

(2)

where , ,and ,

, .In which, or ,

, or. c and denote the

modes of propagation for asymmetric couplers. and aremutual inductance and capacitance, respectively. and

represent the self-inductance and capacitance.Since the two sections have a common port, a complete

matrix for the balun can be derived by combining (1) and (2)together. Here, only two most important parameters, and, are given to characterize the balun’s balance performances

(3)

(4)

where . It is obvious that, which shows an unbalance, even if ,

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392 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 24, NO. 6, JUNE 2014

Fig. 2. Block diagram of an asymmetric Marchand balun with normal balancecompensation.

, , , andfor the two identical coupled-line sections. Thus, compensationsshould be made in order to balance and such that

.

B. Balun With Normal Balance Compensation

Fig. 2 shows the schematic diagram of an asymmetric balunwith a compensating (Comp.) line connecting two coupled-linesections together. represent electrical length, propaga-tion constant, and physical length of the line, respectively. The[S] matrix of the Comp. line is given by

(5)

By combining the three parts in terms of Section I, Comp.line and Section II together, we have

(6)

(7)

Significantly, holds if , which can berepresented as

(8)

Equation (8) indicates that the balance compensation can beachieved if the compensating line is introduced along with care-fully designed coupled-lines.

C. Balun With Enhanced Balance Compensation

Generally, it is difficult to design a balun which is in goodagreement with (8) when bandwidth and area efficiency are con-cerned, because the degree of design freedom is limited dueto the identical configuration for the two coupled-line sections.Fig. 3 shows the schematic diagram of a balun with a compen-sating line but non-identical coupled-line sections. In this case,(6) and (7) can be rewritten as

(9)

(10)

where . We obtain ifand , which

result in and it can be represented as

(11)

Fig. 3. Block diagram of an asymmetric Marchand balun with enhanced bal-ance compensation.

Fig. 4. Asymmetric Marchand balun with normal balance compensation. (a)Side view layout geometry. (b) Chip photograph.

It can be concluded from (11) that the structure shown inFig. 3 provides more degrees of design freedom than the pre-vious structure shown in Fig. 2 for the implementation of bal-ance-compensated asymmetric Marchand balun.

III. BALUNS IMPLEMENTATION AND MEASUREMENTS

A. Balun With Normal Balance Compensation

Fig. 4 shows the multilayer architecture and chip photographof the balun with normal balance compensation. The balun isfabricated using the aluminum copper alloy and the aluminumvias are deposited for adherence. The metal layers, layout ge-ometries and substrate parameters are also shown in detail. Thetopmost metal (M6) is used for the upper spiral coils, M5 for thecompensating line,M3 for the bottom spiral coils andM2 for theunderpasses to the output ports which are not shown in Fig. 4(a).A spiral stack structure shown in Fig. 4(b) is employed to imple-ment the balun for optimizing the area efficiency. The physicallength of the balun is 1420 including a 100- -length com-pensating line.The -parameters of the balun were simulated in ADS Mo-

mentum in order to perform full-wave electromagnetic (EM)simulations. On-wafermeasurements were performed by anAg-ilent’s N5245A 50 GHz four-port VNA and a Cascade probestation with 50 GHz probes. An open pad pattern, which is notshown here, was used for de-embedding. In Fig. 5(a), the mea-sured insertion loss is better than 5 dB from 18.5 to 50 GHz, andthe return loss is better than 10 dB from 20.4 to 50GHz. Fig. 5(b)shows that the phase imbalance is better than 2.5 and the ampli-tude difference is less than 1.3 dB within 11.7–47.7 GHz range.

B. Balun With Enhanced Balance Compensation

To further improve balun’s balance performance, the linewidth at input port (P1) was reduced to 3 , and an extraground (GND) line realized by M3 and M6 with the same widthof 10 was placed between the two coupled-line sections.The side view layout and chip photograph are shown in Fig. 6(a)and 6(b), respectively. It can be seen from Fig. 6(b) that the twocoupled-line sections are asymmetric mirrored by the GND

YANG et al.: BALANCE-COMPENSATED ASYMMETRIC MARCHAND BALUNS ON SILICON FOR MMICs 393

TABLE ICOMPARISON AND SUMMARY OF VARIOUS BALUNS IN 0.18- CMOS PROCESS

Including all testing pads.

Fig. 5. Simulation and measurement results of the balun with normal balancecompensation. (a) Insertion and return loss. (b) Amplitude and phase difference.

Fig. 6. Asymmetric Marchand balun with enhanced balance compensation. (a)Side view layout. (b) Chip photograph.

Fig. 7. Simulation andmeasurement results of the balun with enhanced balancecompensation. (a) Insertion and return loss. (b) Amplitude and phase difference.

line. Therefore, the proposed balun has a dual-asymmetricarchitecture. To the authors’ best knowledge, this kind of balunhas not been reported up to date. Following the same design,simulation and measurement procedure aforementioned, simu-lated and measured results of the balun with enhanced balancecompensation are shown in Fig. 7(a) and (b).In Fig. 7(a), the measured insertion loss is better than 5 dB

from 18.5 to 50 GHz, and the return loss is better than 10 dBfrom 19.3 to 50 GHz. Fig. 7(b) shows that the phase imbalance

is better than 2.5 within 12.5–50 GHz range and the amplitudedifference is less than 1 dB from 10 to 50 GHz.The amplitude differences between the measurements and

simulations are somewhat lager than other characteristics inFigs. 5 and 7. This is due to the fact that the amplitude differ-ence value of a balun is around 1, typically, which is smallerthan other characteristics and it is more sensitive to the layoutdifference between EM simulation and fabrication.

IV. CONCLUSION

Two silicon-based spiral-stacked asymmetric Marchandbaluns with normal and enhanced balance compensatingtechniques are demonstrated. Table I show a summary of theproposed balance-compensated baluns, along with recentlyreported state-of-the-art CMOS baluns for comparison. As canbe seen, compared with other works, the proposed dual-asym-metric Marchand balun exhibits the lowest in band phasedifference while occupies a relatively small chip area.

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