bai tap vhdl 2014

Cc BT gii sn v VHDL 2011 trang 1

HBK Tp HCMKhoa TBMT Mn hc: K thut s GVPT: H Trung M

Bi tp gii sn v VHDL (AY1112-S1) (Cc m VHDL c chy th trn Altera MaxplusII v10.2)

1. Vit m VHDL m s bit 1 ca s nh phn 3 bit A vi cc cch sau:

a) Dng m hnh hnh vi b) Dng m hnh lung d liu c) Lnh case-when d) Dng m hnh cu trc

Bi gii. Vi yu cu ca bi, ta c c bng chn tr sau:

Ng vo Ng ra A2 A1 A0 C1 C0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

Phn u dng th vin IEEE v khai bo entity th ging nhau cho cc cch: TD: Vi khai bo ca cch 1: library ieee; use ieee.std_logic_1164.all; entity ONES_CNT_EX1 is port ( A : in std_logic_vector(2 downto 0); C : out std_logic_vector(1 downto 0)); end ONES_CNT_EX1;

a) M hnh hnh vi: architecture Algorithmic of ONES_CNT_EX1 is begin Process(A) -- Sensitivity List Contains only Vector A Variable num: INTEGER range 0 to 3; begin num :=0; For i in 0 to 2


Loop IF A(i) = '1' then num := num+1; end if; end Loop; -- -- Transfer "num" Variable Value to a SIGNAL -- CASE num is WHEN 0 => C C C C


num_bits := 0; FOR i IN d'RANGE LOOP IF d(i) = '1' THEN num_bits := num_bits + 1; END IF; END LOOP; q


WHEN "111" => C C cn AND 2 ng vo v OR 3 ng vo

v C0 = A2A1A0 + A2A1A0 + A2A1A0 + A2A1A0 C0 = ((A2A1A0).( A2A1A0) .(A2A1A0).(A2A1A0))

=> Cn NAND 3 ng vo, NAND 4 ng vo v cng NOT Mch cho C1 c t tn l MAJ3 v mch cho C0 c t tn l OPAR3. T c bi gii sau: ----------------- NOT gate ----------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY notgate IS PORT( i: IN STD_LOGIC; o: OUT STD_LOGIC); END notgate; ARCHITECTURE Dataflow OF notgate IS BEGIN o


PORT( i1, i2, i3, i4: IN STD_LOGIC; o: OUT STD_LOGIC); END nand4gate; ARCHITECTURE Dataflow OF nand4gate IS BEGIN o


END COMPONENT; COMPONENT or3gate PORT(I1, I2, I3: in STD_LOGIC; O: out STD_LOGIC); END COMPONENT; -- SIGNAL A1, A2, A3: STD_LOGIC; -- Declare Maj3 Local Signals begin -- Instantiate Gates g1: and2gate PORT MAP (X(0), X(1), A1); g2: and2gate PORT MAP (X(0), X(2), A2); -- Wiring of g3: and2gate PORT MAP (X(1), X(2), A3); -- Maj3 g4: or3gate PORT MAP (A1, A2, A3, Z); -- Compts. end Structural_M; ------------------OPAR3 Circuit------------------------------ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity OPAR3 is PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); end OPAR3; architecture Structural_O of OPAR3 is COMPONENT notgate PORT( i: in STD_LOGIC; O: out STD_LOGIC); END COMPONENT; COMPONENT nand3gate PORT( I1, I2, I3: in STD_LOGIC; O: out STD_LOGIC); END COMPONENT; COMPONENT nand4gate PORT( I1, I2, I3, I4: in STD_LOGIC; O: out STD_LOGIC); END COMPONENT; -- SIGNAL A1B, A2B, A0B, Z1, Z2, Z3, Z4: STD_LOGIC; begin -- Instantiate Gates g1: notgate PORT MAP (X(0), A0B); g2: notgate PORT MAP (X(1), A1B); g3: notgate PORT MAP (X(2), A2B); g4: nand3gate PORT MAP (X(2), A1B, A0B, Z1); g5: nand3gate PORT MAP (X(0), A1B, A2B, Z2); g6: nand3gate PORT MAP (X(0), X(1), X(2), Z3); g7: nand3gate PORT MAP (X(1), A2B, A0B, Z4);


g8: nand4gate PORT MAP (Z1, Z2, Z3, Z4, Z); end Structural_O; -----------------ONES_CNT_EX4: Main Circuit------------ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity ONES_CNT_EX4 is port ( A : in STD_LOGIC_VECTOR(2 downto 0); C : out STD_LOGIC_VECTOR(1 downto 0)); end ONES_CNT_EX4; architecture Structural of ONES_CNT_EX4 is COMPONENT MAJ3 PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); END COMPONENT; COMPONENT OPAR3 PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); END COMPONENT; -- begin -- Instantiate Components -- c1: MAJ3 PORT MAP (A, C(1)); c2: OPAR3 PORT MAP (A, C(0)); end Structural; Dng sng ra m phng:

Ch : Ta c th s dng lun cc component c sn ca Altera MaxplusII. Tuy nhin lu phi khai bo component ng vi khai bo ca Altera MaxplusII! Cc cng logic ca Maxplus II c cc khai bo sau:

1) Cng NOT vi tn l A_NOT c khai bo sau: COMPONENT a_not PORT( a_in: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT;


2) Cng AND c th c n ng vo (ANDn) vi n=2, 3, 4, 6, 8 v 12. TD: Khai bo sau cho cng AND c 2 ng vo: COMPONENT and2 PORT( IN1, IN2: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT;

3) Cng OR c th c n ng vo (ORn) vi n=2, 3, 4, 6, 8 v 12. TD: Khai bo sau cho cng OR c 2 ng vo: COMPONENT or3 PORT(IN1, IN2, IN3: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT;

4) Cng NAND c th c n ng vo (NANDn) vi n=2, 3, 4, 6, 8 v 12. 5) Cng NOR c th c n ng vo (NANDn) vi n=2, 3, 4, 6, 8 v 12. 6) Cng XOR 2 ng vo c tn l a_XOR vi khai bo sau:

COMPONENT a_xor PORT(IN1, IN2: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT;

7) Cng XNOR 2 ng vo c tn l a_XNOR Nh vy ta c li gii khc ngn hn nu s dng cc component c sn ca Maxplus II:

----- Use built-in components of MaxplusII ----------------- Majority of 3 bit number---------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity MAJ3 is PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); end MAJ3; architecture Structural_M of MAJ3 is COMPONENT and2 PORT( IN1, IN2: in STD_LOGIC; -- Declare Components a_out: out STD_LOGIC); -- To Be Instantiated END COMPONENT; COMPONENT or3 PORT(IN1, IN2, IN3: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; -- SIGNAL A1,A2,A3: STD_LOGIC; -- Declare Maj3 Local Signals begin -- Instantiate Gates g1: and2 PORT MAP (X(0), X(1), A1); g2: and2 PORT MAP (X(0), X(2), A2); -- Wiring of g3: and2 PORT MAP (X(1), X(2), A3); -- Maj3


g4: or3 PORT MAP (A1, A2, A3, Z); -- Compts. end Structural_M; ------------------OPAR3 Circuit--------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity OPAR3 is PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); end OPAR3; architecture Structural_O of OPAR3 is COMPONENT a_not PORT( a_in: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; COMPONENT nand3 PORT( IN1, IN2, IN3: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; COMPONENT nand4 PORT( IN1, IN2, IN3, IN4: in STD_LOGIC; a_out: out STD_LOGIC); END COMPONENT; -- SIGNAL A1B, A2B, A0B, Z1, Z2, Z3, Z4: STD_LOGIC; begin -- Instantiate Gates g1: a_not PORT MAP (X(0), A0B); g2: a_not PORT MAP (X(1), A1B); g3: a_not PORT MAP (X(2), A2B); g4: nand3 PORT MAP (X(2), A1B, A0B, Z1); g5: nand3 PORT MAP (X(0), A1B, A2B, Z2); g6: nand3 PORT MAP (X(0), X(1), X(2), Z3); g7: nand3 PORT MAP (X(1), A2B, A0B, Z4); g8: nand4 PORT MAP (Z1, Z2, Z3, Z4, Z); end Structural_O; -----------------ONES_CNT_EX4: Main Circuit------------ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity ONES_CNT_EX4B is port ( A : in STD_LOGIC_VECTOR(2 downto 0); C : out STD_LOGIC_VECTOR(1 downto 0)); end ONES_CNT_EX4B; architecture Structural of ONES_CNT_EX4B is


COMPONENT MAJ3 PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); END COMPONENT; COMPONENT OPAR3 PORT( X: in STD_LOGIC_VECTOR(2 downto 0); Z: out STD_LOGIC); END COMPONENT; -- begin -- Instantiate Components c1: MAJ3 PORT MAP (A, C(1)); c2: OPAR3 PORT MAP (A, C(0)); end Structural;

2. Vi mch t hp sau:

Hy vit m VHDL vi cc cch sau (khng thit k ring mch gii m, m ch ci t hm F):

1) Lnh ng thi vi php gn dng cc ton t logic 2) Lnh ng thi WHEN-ELSE 3) Lnh ng thi WITH-SELECT-WHEN 4) Lnh tun t IF-THEN-ELSE 5) Lnh tun t CASE-WHEN

Bi gii. 1) Lnh ng thi vi php gn dng cc ton t logic

--- signal assignment with logic operators library ieee; use ieee.std_logic_1164.all; entity Q02_1 is port ( A, B, C: in std_logic; -- C: LSB F: out std_logic); end Q02_1; architecture a of Q02_1 is signal D1, D5, D7: std_logic; begin

D1


D5


4) Lnh tun t IF-THEN-ELSE

--- signal assignment with IF-THEN-ELSE library ieee; use ieee.std_logic_1164.all; entity Q02_4 is port( A, B, C: in std_logic; -- C: LSB F: out std_logic); end Q02_4; architecture a of Q02_4 is signal ABC: std_logic_vector(2 downto 0); begin ABC


3. Hy v mch logic tng ng (khng n gin ha hm Boole v c th s dng cc thnh phn t hp c bn nh cng logic, mux, decoder, FA, HA, ) ca m VHDL sau:

library ieee; use ieee.std_logic_1164.all; entity blackbox is port( a, b, cin: in std_logic; inst: in std_logic_vector(2 downto 0); F, cout: out std_logic); end blackbox; architecture bg of blackbox is signal s0, s1, s2, s3, s4 : std_logic; --signal command : std_logic_vector(1 downto 0); begin s0


4. Hy v mch logic tng ng (khng n gin ha hm Boole v c th s dng cc thnh phn t hp c bn nh cng logic, mux, decoder, FA, HA, ) ca m VHDL sau: library ieee; use ieee.std_logic_1164.all; entity CIRCUIT is port(A, B, C: in std_logic; S:in std_logic_vector (1 downto 0); Z: out std_logic); end CIRCUIT; architecture a of CIRCUIT is begin process(A, B, C, S) begin if (S(0)= 1) then Z


Bi gii. T m VHDL ta c th vit trc tip cc biu thc Boole cho cc bin ra vi loi lnh IF :

Lnh Biu thc Boole tng ng if (cond1) then

F


Bi gii. NX : Ng ra ch c cp nht khi c cnh ln ti CLK y l D F/F kch cnh ln vi ng vo l mch t hp nh cu trn.

6. Ta cn thit k 1 mch t hp m xut pht t thit k s thng thng, mch ny c ghp t mch m ha u tin t 10 ng vo (in_n) sang 4 (BCD): ng vo tch cc thp v u

tin bit c trng s thp nht, ng ra l s BCD 4 bit ch ng vo no c tch cc thp. o TD: Ng vo in_n = 11111100 th ng ra l BCD = 0000

Mch gii m BCD ra 7 on ni vi LED (gi s logic 1 lm cho on LED sng) : mch ny nhn gi tr ra t mch trn v chuyn sang m 7 on hin trn LED 7 on.

a) Hy vit m VHDL vi 2 mch ny c lp. b) Hy vit m VHDL ch c 1 mch duy nht.

Bi gii. Ta c th dng when-else hay with-select-when m t cc mch ny.

a) M VHDL vi 2 mch c lp library ieee; use ieee.std_logic_1164.all; entity Q06_1 is port( in_n: in std_logic_vector(9 downto 0);

-- in_n : low active and higher priority LSB LED_7seg: out std_logic_vector(6 downto 0));

-- LED_7seg(0) = segment a end Q06_1; architecture bg of Q06_1 is signal s_BCD : std_logic_vector (3 downto 0); begin -- Priority Encoder s_BCD


-- BCD to 7 segment Decoder: LED_7seg = gfedcba LED_7seg '0'); end bg; Dng sng m phng :

b) M VHDL vi 1 mch duy nht library ieee; use ieee.std_logic_1164.all; entity Q06_2 is port( in_n: in std_logic_vector(9 downto 0); LED_7seg: out std_logic_vector(6 downto 0)); end Q06_2; architecture bg of Q06_2 is begin LED_7seg


"0000111" when in_n(7) = '0' else "0000000" when in_n(8) = '0' else "1101111" when in_n(9) = '0' else (others => '0'); end bg; 7. Thit k JK flipfop nh hnh bn di (cc ng Preset PR v Clear CLR tch cc cao v bt ng b, CLR c u tin cao hn PR)

a) Dng phng trnh c tnh ca JK FF. b) Dng bng hot ng ca JK FF. c) Nu mun Preset PR ng b th phi sa li nh th no?

Bi gii. a) Dng phng trnh c tnh ca JK FF:

library ieee; use ieee.std_logic_1164.all; entity JK_FF is port( J, K, CLK, PR, CLR: in std_logic;

-- PR, CLR: Asynchronous Preset and Clear Q, Q_n: out std_logic); end JK_FF; architecture bg of JK_FF is signal Q_int: std_logic; begin process(CLK, PR, CLR) begin if (CLR = '1') then Q_int


b) Dng bng hot ng ca JK FF:

library ieee; use ieee.std_logic_1164.all; entity JK_FF is port( J, K, CLK, PR, CLR: in std_logic; Q, Q_n: out std_logic); end JK_FF; architecture bg of Q07_2 is signal Q_int: std_logic; signal JK: std_logic_vector(1 downto 0); begin JK


Dng sng m phng :

8. Thit k mch cng song song 2 s nh phn N bit (dng pht biu generic thit k tng qut, mc nhin N =4) l A v B. Tng l Sum v s nh/mn l C_out.

a) M t VHDL cho mch ny. b) Thm vo tn hiu iu khin cho php cng/tr vi tn l Add_Sub (0: cng v 1:tr)

th phi chnh sa nh th no? Bi gii.

a) Khi s dng ton t cng/tr th ta phi dng gi ieee.std_logic_unsigned.all : -- Parallel Adder library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Q08_1 is

generic (N: integer := 4); port( A, B: in std_logic_vector(N-1 downto 0); C_out: out std_logic; Sum: out std_logic_vector(N-1 downto 0)); end Q08_1; architecture bg of Q08_1 is signal Sum_int: std_logic_vector(Num downto 0); begin Sum_int


9. Thit k mch cng ni tip 2 s nh phn vi A v B c chiu di l Num_bits bit (mc nhin cho Num_bits = 4).

D liu vo c nhp ni tip vi LSB i trc. Kt qu l tng Sum c chiu di Num_bits bit v c s nh ra l C_out. Tn hiu Start =1 ch bt u thc hin cng (ch tn ti < 1 chu k xung nhp). C tn hiu Finished bo hon tt php cng. Mch hot ng theo cnh xung xung nhp CLK.

Hy vit m VHDL cho mch ny. Bi gii. library ieee; use ieee.std_logic_1164.all; entity Q09_1 is generic (Num_bits: integer := 4); port( A, B, Start, CLK: in std_logic; C_out, Finished: out std_logic; Sum: out std_logic_vector(Num_bits-1 downto 0)); end Q09_1; architecture bg of Q09_1 is begin process(CLK, Start) variable FIN: std_logic; -- Internal Finish signal variable N: integer range 0 to Num_bits; variable S, C_in: std_logic; variable Sum_int: std_logic_vector(Num_bits-1 downto 0); begin if (Start = '1') then FIN := '0'; N := Num_bits; C_in := '0'; Finished


if N = 0 then FIN := '1'; Finished


10. Cho trc h tun t ng b sau:

a) Lp bng chuyn trng thi ca mch trn. b) Vit m VHDL cho cu a) c thm tn hiu reset_n tch cc thp cho chy t trng

thi Q1Q2=00. Bi gii.

a) T s mch ta c th tm c cc phng trnh c tnh cho cc FF v ng ra Z : D1 = Q1+ = Q1 + Q2 ; D2 = Q2+ = XQ2 ; Z = Q1 + Q2

Suy ra bng chuyn trng thi sau: PS

Q1Q2 NS (Q1+Q2+) Z X = 0 X =1

00 10 01 1 01 10 10 0 11 00 10 1 10 00 01 1

b) M VHDL cho cu a): library ieee; use ieee.std_logic_1164.all; entity Q10_1 is port( X, CLK, reset_n: in std_logic; Z: out std_logic); end Q10_1; architecture bg of Q10_1 is signal state: std_logic_vector( 1 downto 0); signal state_X: std_logic_vector( 2 downto 0); begin state_X


when "010" | "011" => state state state state state null; end case; end if; end process; end bg; Dng sng m phng:

Ch : C nhiu cch vit khc m t FSM, th d sau y l 1 cch vit khc: library ieee; use ieee.std_logic_1164.all; entity Q10_2 is port( X, CLK, reset_n: in std_logic; Z: out std_logic); end Q10_2; architecture bg of Q10_2 is signal Present_state: std_logic_vector( 1 downto 0); -- PS signal Next_state: std_logic_vector( 1 downto 0); -- NS begin Z


Find_Next_state: process(Present_state) begin case Present_state is when "00" => if X = '0' then Next_state


Ta nh ngha thm kiu mi cho cc trng thi khng cn gn trng thi m CAD s t gn tr cho n.

library ieee; use ieee.std_logic_1164.all; entity Q11_1 is port( X, CLK, reset_n: in std_logic; Z: out std_logic); end Q11_1; architecture bg of Q11_1 is type state_type is (S0, S1, S2); signal state: state_type; begin Z


b) Thanh ghi dch library ieee; use ieee.std_logic_1164.all; entity Q11_2 is port( X, CLK, reset_n: in std_logic; Z: out std_logic); end Q11_2; architecture bg of Q11_2 is signal pattern: std_logic_vector(2 downto 0); begin Z


architecture bg of Q12_1 is signal CBA: std_logic_vector(0 to 2); signal CBA_int: integer range 0 to 7; begin -- Decoder 3 to 8 CBA


13. Thit k b m ln 3 bit loi ni tip (cn gi l b m gn hay bt ng b) vi xung nhp vo CLK (kch cnh). Mch c ng reset tch cc thp reset_n. Hy vit m VHDL vi

a) M hnh cu trc vi component DFF c sn. b) Cc lnh tun t.

Bi gii. a) Dng component DFF c sn ca Maxplus II

library ieee; use ieee.std_logic_1164.all; entity Q13_1 is port( CLK, reset_n: in std_logic; Q2, Q1, Q0: out std_logic); -- Q0: LSB end Q13_1; architecture bg of Q13_1 is COMPONENT DFF PORT (d : IN STD_LOGIC; clk : IN STD_LOGIC; clrn: IN STD_LOGIC; prn : IN STD_LOGIC; q : OUT STD_LOGIC ); END COMPONENT; -- Inputs | Output --prn clrn CLK D | Q -- L H X X | H -- H L X X | L -- L L X X | Illegal -- H H L | L -- H H H | H -- H H L X | Qo* -- H H H X | Qo -- * Qo = level of Q before Clock pulse -- All flipflops are positive-edge-triggered. signal D0, D1, D2, prn: std_logic; signal Q2_int, Q1_int, Q0_int: std_logic; begin U1: DFF port map(D0, CLK, reset_n, prn, Q0_int); U2: DFF port map(D1, D0, reset_n, prn, Q1_int); U3: DFF port map(D2, D1, reset_n, prn, Q2_int); prn


c) Cc lnh tun t:

library ieee; use ieee.std_logic_1164.all; entity Q13_2 is port( CLK, reset_n: in std_logic; Q2, Q1, Q0: out std_logic); -- Q0: LSB end Q13_2; architecture bg of Q13_2 is signal Q2_int, Q1_int, Q0_int: std_logic; begin process(CLK, reset_n) begin if reset_n = '0' then Q0_int


Ch : Ta c th khai bo buffer cho cc i tng ra Q2, Q1, v Q0, khi khng cn dng cc tn hiu Q2_int, Q1_int, Q0_int. 14. Thit k b m ln 3 bit loi song song (cn gi l b m ng b) vi xung nhp vo CLK (kch cnh). Mch c ng reset tch cc thp reset_n. Hy vit m VHDL vi

a) M hnh cu trc vi component JKFF c sn. b) Cc lnh tun t. c) Vi dy m 1, 3, 5, 7, 1, . .

Bi gii. a) M hnh cu trc vi component JKFF c sn:

library ieee; use ieee.std_logic_1164.all; entity Q14_1 is port( CLK, reset_n: in std_logic; Q2, Q1, Q0: buffer std_logic); -- Q0: LSB end Q14_1; architecture bg of Q14_1 is COMPONENT JKFF PORT (j : IN STD_LOGIC; k : IN STD_LOGIC; clk : IN STD_LOGIC; clrn: IN STD_LOGIC; prn : IN STD_LOGIC; q : OUT STD_LOGIC); END COMPONENT; -- Inputs | Output -- PRN CLRN CLK J K | Q -- L H X X X | H -- H L X X X | L -- L L X X X | Illegal -- H H L X X | Qo* -- H H L L | Qo* -- H H H L | H -- H H L H | L -- H H H H | Toggle -- * Qo = level of Q before Clock pulse -- All flipflops are positive-edge-triggered. signal J0, J1, J2, prn: std_logic; begin U1: JKFF port map(J0, J0, CLK, reset_n, prn, Q0); U2: JKFF port map(J1, J1, CLK, reset_n, prn, Q1); U3: JKFF port map(J2, J2, CLK, reset_n, prn, Q2); prn


b) Cc lnh tun t:

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- De tinh cong so nhi phan voi so nguyen entity Q14_2 is port( CLK, reset_n: in std_logic; Q2, Q1, Q0: out std_logic); -- Q0: LSB end Q14_2; architecture bg of Q14_2 is signal Q: std_logic_vector(2 downto 0); begin process(CLK) begin if reset_n ='0' then Q

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