automotive fully integrated h-bridge motor driver · the vnh5180a-e is a full bridge motor driver...

September 2013 Doc ID 17074 Rev 6 1/31

1

VNH5180A-E

Automotive fully integrated H-bridge motor driver

Features

• Output current: 8 A

• 3 V CMOS compatible inputs

• Undervoltage shutdown

• Overvoltage clamp

• Thermal shutdown

• Cross-conduction protection

• Current and power limitation

• Very low standby power consumption

• PWM operation up to 20 KHz

• Protection against loss of ground and loss of VCC

• Current sense output proportional to motor current

• Output protected against short to ground and short to VCC

• Package: ECOPACK®

DescriptionThe VNH5180A-E is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic high-side driver and two low-side switches. Both switches are designed using STMicroelectronics’ well known and proven

proprietary VIPower® M0 technology that allows to efficiently integrate on the same die a true Power MOSFET with an intelligent signal/protection circuitry. The three dies are assembled in PowerSSO-36 TP package on electrically isolated leadframes. This package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals INA and INB can directly interface to the microcontroller to select the motor direction and the brake condition. The DIAGA/ENA or DIAGB/ENB, when connected to an external pull-up resistor, enables one leg of the bridge. Each DIAGA/ENA provides a feedback digital diagnostic signal as well. The normal operating condition is explained in the truth table. The CS pin allows to monitor the motor current by delivering a current proportional to its value when CS_DIS pin is driven low or left open. When CS_DIS is driven high, CS pin is in high impedance condition. The PWM, up to 20 KHz, allows to control the speed of the motor in all possible conditions. In all cases, a low level state on the PWM pin turns off both the LSA and LSB switches.

Type RDS(on) Iout VCCmax

VNH5180A-E 180 mΩ max

(per leg)8 A 41 V

PowerSSO-36 TP

Table 1. Device summary

PackageOrder codes

Tube Tape and reel

PowerSSO-36 TP VNH5180A-E VNH5180ATR-E

www.st.com

http://www.st.com

Contents VNH5180A-E

2/31 Doc ID 17074 Rev 6

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.1.1 Thermal calculation in clockwise and anti-clockwise operation in steady-state mode 23

4.1.2 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2 PowerSSO-36 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3 PowerSSO-36 TP packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

VNH5180A-E List of tables

Doc ID 17074 Rev 6 3/31

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Table 2. Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Table 3. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6Table 4. Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Table 5. Pin functions description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Table 7. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 8. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Table 9. Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 10. Switching (VCC = 13 V, RLOAD = 5 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 11. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Table 12. Current sense (9 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Table 13. Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 14. Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 15. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 16. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 17. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 18. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 23Table 19. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Table 20. PowerSSO-36 TP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

List of figures VNH5180A-E

4/31 Doc ID 17074 Rev 6

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 4. Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 5. Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 6. Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 7. Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 14Figure 8. Definition of delay response time of sense current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 9. Waveforms in full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 10. Waveforms in full-bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 19Figure 12. Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 13. Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 14. Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 15. PowerSSO-36™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 16. Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 17. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 23Figure 18. Detailed chipset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 25Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 25Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 22. PowerSSO-36 TP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 23. PowerSSO-36 TP tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

VNH5180A-E Block diagram and pin description

Doc ID 17074 Rev 6 5/31

1 Block diagram and pin description

Figure 1. Block diagram

Table 2. Block description

Name Description

Logic controlAllows the turn-on and the turn-off of the high-side and the low-side switches according to the truth table.

Undervoltage Shuts down the device for battery voltage lower than 5V.

High-side and low-side clamp voltageProtect the high-side and the low-side switches from the high voltage on the battery line.

High-side and low-side driverDrive the gate of the concerned switch to allow a proper RDS(on) for the leg of the bridge.

Current limitation Limits the motor current in case of short circuit.

High-side and low-side overtemperature protection

In case of short-circuit with the increase of the junction temperature, it shuts down the concerned driver to prevent degradation and to protect the die.

Low-side overload detectorDetects when low side current exceeds shutdown current and latches off the concerned Low side.

Fault detectionSignalizes the abnormal behaviour of the switch (output shorted to ground or output shorted to battery) by pulling down the concerned ENx/DIAGx pin.

Power limitationLimits the power dissipation of the high-side driver inside safe range in case of short to ground condition.

Block diagram and pin description VNH5180A-E

6/31 Doc ID 17074 Rev 6

Figure 2. Configuration diagram (top view)

Table 3. Suggested connections for unused and not connected pins

Connection / pin Current sense N.C. SOURCE_HSx DRAIN_LSxINPUTx, PWM

DIAGx/ENxCS_DIS

Floating Not allowed X X X X

To groundThrough 1 kΩ

resistorX Not allowed X

Through 10 kΩ resistor

Table 4. Pin definitions and functions

Pin N° Symbol Function

13, 24 VCC, Heat Slug1 Drain of high-side switches and power supply voltage.

1, 5, 9, 14, 18, 23, 28, 32, 36

NC Not connected.

15 INA Clockwise input

16 ENA/DIAGAStatus of high-side and low-side switches A;

open drain output.

17 IN_PWM PWM input.

19 CS Output of current sense.

1

EN/DIAG_A

CS19

IN_A

GND_B

GND_A

IN_B

EN/DIAG_B

18

NC

SOURCE HSB

GND_B

Slug1

Slug2 Slug3

36

SOURCE HSA

GND_A

GND_AGND_A

DRAIN LSA

SOURCE HSA

SOURCE HSA

VCC

NCVCC

SOURCE HSB

SOURCE HSB

DRAIN LSB

GND_BGND_BDRAIN LSB

NC

NC

NC

IN_PWMNC

CS_DIS

NC

NC

NCDRAIN LSA

VNH5180A-E Block diagram and pin description

Doc ID 17074 Rev 6 7/31

20 CS_DISActive high CMOS compatible pin to disable current sense pin.

21 ENB/DIAGBStatus of high-side and low-side switches b;

open drain output.

22 INB Counter clockwise input.

25, 26, 27, 29, 35 OUTB, Heat Slug3 Source of high-side switch B / drain of low-side switch B.

30, 31, 33, 34 GNDB Source of low-side switch B.

2, 8, 10, 11, 12 OUTA, Heat Slug2 Source of high-side switch A / drain of low-side switch A.

3, 4, 6, 7 GNDA Source of low-side switch A.

Table 5. Pin functions description

Name Description

VCC Battery connection.

GND Power ground.

OUTA

OUTBPower connections to the motor.

INA

INB

Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to VCC, Brake to GND, clockwise and counterclockwise).

PWMVoltage controlled input pin with hysteresis, CMOS compatible. Gates of low-side FETS get modulated by the PWM signal during their ON phase allowing speed control of the motor.

ENA/DIAGA

ENB/DIAGB

Open drain bidirectional logic pins.These pins must be connected to an external pull up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a high-side FET or excessive ON-state voltage drop across a low-side FET), these pins are pulled low by the device (see Table 14: Truth table in fault conditions (detected on OUTA)).

CSAnalog current sense output. This output delivers a current proportional to the motor current if CS_DIS is low or left open. The information can be read back as an analog voltage across an external resistor.

CS_DIS Active high CMOS compatible pin to disable the current sense pin.

Table 4. Pin definitions and functions (continued)

Pin N° Symbol Function

Electrical specifications VNH5180A-E

8/31 Doc ID 17074 Rev 6

2 Electrical specifications

Figure 3. Current and voltage conventions

2.1 Absolute maximum ratingsStressing the device above the rating listed in the Table 6: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

VCCINA

IS

IOUTA

IINA

VINA

VCC

VOUTAISENSE

VOUTBDIAGA/ENA

IENA

IGND

IOUTBINB

IINB

DIAGB/ENB

IENB

VENBVENAVINB

VSENSE

OUTA

OUTB

PWM

CS

Ipw

Vpw

GND

VCSD

ICSDCS_DIS

Table 6. Absolute maximum ratings

Symbol Parameter Value Unit

VCC Supply voltage + 41 V

Imax Maximum output current (continuous) Internally limited A

IR Reverse output current (continuous) -15 A

IIN Input current (INA and INB pins) +/- 10 mA

IEN Enable input current (DIAGA/ENA and DIAGB/ENB pins) +/- 10 mA

Ipw PWM Input current +/- 10 mA

ICS_DIS CS_DIS input current +/- 10 mA

VCS Current sense maximum voltage VCC-41/+VCC V

VESDElectrostatic discharge (Human body model: R=1.5 kΩ, C=100 pF)

2 kV

Tc Junction operating temperature -40 to 150 °C

TSTG Storage temperature -55 to 150 °C

IGND DC reverse ground pin current 200 mA

VNH5180A-E Electrical specifications

Doc ID 17074 Rev 6 9/31

2.2 Thermal data

2.3 Electrical characteristicsValues specified in this section are for VCC = 9 V up to 18 V; -40 °C < TJ < 150 °C, unless otherwise specified.

Table 7. Thermal data

Symbol Parameter Max. value Unit

Rthj-case Thermal resistance junction-case (per leg)HSD 4.8 °C/W

LSD 4.6

Rthj-amb Thermal resistance junction-ambient See Figure 17 °C/W

Table 8. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC Operating supply voltage 5.5 18 V

IS Supply current

Off-state with all fault cleared andENx = 0 (standby)INA = INB = PWM = 0; Tj = 25 °C;VCC = 13 V

3 6 µA

Off-state with all fault cleared andENx = 0 (standby)INA = INB = PWM = 0; VCC = 13 V; Tj = - 40 to 150 °C

10 µA

Off-state (no standby)INA = INB = PWM = 0; ENx = 5 V; Tj = - 40 to 150 °C

5 mA

On-state:

INA or INB = 5 V; no PWM3 6 mA

On-state:

INA or INB = 5 V; PWM = 20 kHz6 mA

RONHS Static high-side resistance

IOUT = 2.5 A; Tj = -40 °C 75 mΩ

IOUT = 2.5 A; Tj = 25 °C 115 mΩ

IOUT = 2.5 A; Tj = 150 °C 230 mΩ

IOUT = 2.5 A; Tj = - 40 to 150 °C 250 mΩ

RONLS Static low-side resistanceIOUT = 2.5 A; Tj = 25 °C 53.5 mΩ

IOUT = 2.5 A; Tj = - 40 to 150 °C 110 mΩ

VfHigh-side free-wheeling diode forward voltage

IOUT = -2.5 A; Tj = 150 °C 0.7 0.9 V


10/31 Doc ID 17074 Rev 6

IL(off)High-side off-state output current (per channel)

Tj = 25 °C; VOUTX = ENX = 0 V; VCC = 13 V

0 3 µA

Tj = 125 °C; VOUTX = ENX = 0 V; VCC = 13 V

0 5 µA

IRMDynamic cross-conduction current

IOUT= 2.5A (see Figure 6) 0.6 A

Table 9. Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS)


VIL Input low level voltageNormal operation (DIAGX/ENX pin acts as an input pin)

0.9 V

VIH Input high level voltageNormal operation (DIAGX/ENX pin acts as an input pin)

2.1 V

VIHYST Input hysteresis voltageNormal operation (DIAGX/ENX pin acts as an input pin)

0.15 V

VICL Input clamp voltageIIN = 1 mA 5.5 6.3 7.5 V

IIN = -1 mA -1.0 -0.7 -0.3 V

IINL Input current VIN = 0.9 V 1 µA

IINH Input current VIN = 2.1 V 10 µA

VDIAGEnable output low

level voltage

Fault operation (DIAGX/ENX pin acts as an output pin); IEN = 1 mA

0.4 V

Table 10. Switching (VCC = 13 V, RLOAD = 5 Ω)


f PWM frequency 0 20 kHz

td(on) Turn-on delay timeInput rise time < 1µs (see Figure 6)

250 µs

td(off) Turn-off delay timeInput rise time < 1µs (see Figure 6)

250 µs

tr Rise time See Figure 5 1 2 µs

tf Fall time See Figure 5 1 2 µs

tDELDelay time during change of operating mode

See Figure 4 200 400 1600 µs

trr

High-side free wheeling diode reverse recovery time

See Figure 7 400 ns

Table 8. Power section (continued)



Doc ID 17074 Rev 6 11/31

Table 11. Protections and diagnostics


VUSD Undervoltage shutdown 3 5 V

VUSDhystUndervoltage shutdown hysteresis

0.5 V

ILIM_H High-side current limitation 8 12 16 A

ISD_LS Shutdown LS current 16 30 52 A

VCLPHHigh-side clamp voltage (VCC to OUTA = 0 or OUTB = 0)

IOUT = 2.5 A 41 46 52 V

VCLPLS

Low-side clamp voltage (OUTA = VCC or OUTB = VCC to GND)

IOUT = 2.5 A 41 46 52 V

TTSD(1)

1. TTSD is the minimum threshold temperature between HS and LS

Thermal shutdown temperature VIN = 2.1 V 150 175 200 °C

TTR(2)

2. Valid for both HSD and LSD.

Thermal reset temperature 135 °C

THYST(2) Thermal hysteresis (TSD - TR) 7 °C

TTSD_LSLow-side thermal shutdown temperature

VIN = 2.1 V 150 175 200 °C

VCLP Total clamp voltage (VCC to GND) IOUT = 2.5 A 41 46 52 V

tSD_LS Time to shutdown for the low-side 10 µs

Table 12. Current sense (9 V < VCC < 18 V)


K0 IOUT/ISENSEIOUT = 0.35 A; VSENSE = 0.32 V; VCSD = 0 V; Tj = - 40 to 150 °C

645 840 1140

K1 IOUT/ISENSEIOUT = 1 A; VSENSE = 0.98 V; VCSD = 0 V; Tj = - 40 to 150 °C

700 820 955

K2 IOUT/ISENSEIOUT = 2.5 A; VSENSE = 2.4 V; VCSD = 0 V; Tj = - 40 to 150 °C

710 810 900

K3 IOUT/ISENSEIOUT = 4 A; VSENSE = 4 V; VCSD = 0 V; Tj = - 40 to 150 °C

690 790 900

dK0/K0(1)

Analog sense current drift

IOUT = 0.35A; VSENSE = 0.32V; VCSD = 0 V; Tj = - 40 to 150 °C

-18 18 %

dK1/K1(1) Analog sense

current driftIOUT = 1 A; VSENSE = 0.98 V; VCSD = 0 V; Tj = - 40 to 150 °C

-13 13 %

dK2/K2(1)

Analog sense current drift

IOUT = 2.5A; VSENSE = 2.4V; VCSD = 0 V; Tj = - 40 to 150 °C

-13 13 %

dK3/K3(1) Analog sense

current driftIOUT = 4A; VSENSE = 4V; VCSD = 0 V; Tj = - 40 to 150 °C

-13 13 %

VSENSEMax analog sense output voltage

IOUT = 2.5A; VCSD = 0 V; RSENSE = 2 KΩ 5 V


12/31 Doc ID 17074 Rev 6

Figure 4. Definition of the delay times measurement

ISENSE0Analog sense leakage current

IOUT = 0 A; VSENSE = 0 V; VCSD = 5 V; VIN = 0 V; Tj = - 40 to 150 °C

0 5 µA

VCSD = 0 V; VIN = 5 V; Tj = - 40 to.150 °C

0 180 µA

VCSD = 5 V; VIN = 5 V; IOUT = 2.5 A; Tj = - 40 to.150 °C

0 5 µA

tDSENSEH

Delay response time from falling edge of CS_DIS pin

VIN = 5 V; VSENSE < 4 V, IOUT = 2.5 A, ISENSE = 90 % of ISENSEmax (see Figure 8)

50 µs

tDSENSEL

Delay response time from rising edge of CS_DIS pin

VIN = 5 V; VSENSE < 4 V; IOUT = 2.5 A;ISENSE = 10 % of ISENSEmax(see Figure 8)

20 µs

1. Analog sense current drift is deviation of factor K for a given device over (-40 °C to 150 °C and9 V < VCC < 18 V) with respect to its value measured at TJ = 25 °C, VCC = 13 V.

Table 12. Current sense (9 V < VCC < 18 V) (continued)


t

t

VINB

VINA

t

PWM

t

ILOAD

tDELtDEL


Doc ID 17074 Rev 6 13/31

Figure 5. Definition of the low-side switching times

Figure 6. Definition of the high-side switching times

tf

PWM

t

t

VOUTA, B

20%

90% 80%

10% tr

t

t

VOUTA

VINA

90%

10%

tD(on) tD(off)


14/31 Doc ID 17074 Rev 6

Figure 7. Definition of dynamic cross conduction current during a PWM operation

Figure 8. Definition of delay response time of sense current

t

t

IMOTOR

PWM

t

VOUTB

t

ICC

trr

IRM

INA = 1, INB = 0

SENSE CURRENT

INPUT

LOAD CURRENT

CS_DIS

tDSENSEH tDSENSEL


Doc ID 17074 Rev 6 15/31

Note: In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high.

Table 13. Truth table in normal operating conditions

INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB CS Operating mode

11

1 1

HH High Imp. Brake to VCC

0 LISENSE = IOUT/K

Clockwise (CW)

01

LH Counterclockwise (CCW)

0 L High Imp. Brake to GND

Table 14. Truth table in fault conditions (detected on OUTA)

INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB CS (VCSD=0V)

11

01

OPEN

HHigh Imp.

0 L

01 H IOUTB/K

0 LHigh Imp.

X X 0 OPEN

Fault Information Protection Action


16/31 Doc ID 17074 Rev 6

Table 15. Electrical transient requirements (part 1)

ISO 7637-2: 2004(E)

Test pulse

Test levels(1)

1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b.

Number of pulses or test times

Burst cycle/pulse repetition time Delays and

ImpedanceIII IV Min. Max.

1 -75V -100V 5000 pulses 0.5s 5s 2 ms, 10Ω

2a +37V +50V 5000 pulses 0.2s 5s 50µs, 2Ω

3a -100V -150V 1h 90ms 100ms 0.1µs, 50Ω

3b +75V +100V 1h 90ms 100ms 0.1µs, 50Ω

4 -6V -7V 1 pulse 100ms, 0.01Ω

5b(2)

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

+65V +87V 1 pulse 400ms, 2Ω


ISO 7637-2: 2004(E)

Test pulse

Test level results(1)

1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b.

III IV

1 C C

2a C C

3a C C

3b C C

4 C C

5b(2)

2. Valid in case of external load dump clamp: 40V maximum referred to ground.

C C


Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

EOne or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.


Doc ID 17074 Rev 6 17/31

2.4 Waveforms

Figure 9. Waveforms in full-bridge operation

NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)

INA

INB

PWM

OUTA

OUTB

IOUTA->OUTB

DIAGA/ENADIAGB/ENB

DIAGB/ENB

INA

INB

PWM

OUTA

OUTB

DIAGA/ENA

NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)

CS (*)

CS

IOUTA->OUTB

tDEL tDEL

LOAD CONNECTED BETWEEN OUTA, OUTB

LOAD CONNECTED BETWEEN OUTA, OUTB

(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE

CS_DIS

CS_DIS

INA

INB

TjHSA

DIAGA/ENA

DIAGB/ENB

ILIM

TTSD_HSA

TTR_HSA

Tj > TTR

CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND

CS

IOUTA->OUTB

normal operation OUTA shorted to ground normal operation

CS_DIS

Tj < TTSD

Tj =TTSD

power limitation

limitationcurrent


18/31 Doc ID 17074 Rev 6

Figure 10. Waveforms in full-bridge operation (continued)

normal operation OUTA softly shorted to VCC normal operation undervoltage shutdown

INA

INB

OUTAOUTB

DIAGB/ENB

DIAGA/ENA

OUTA shorted to VCC (resistive short) and undervoltage shutdown

CS V<nominal

IOUTA->OUTB

CS_DIS

Tj_LSA

TTSD_LS

normal operation OUTA hardly shorted to VCC normal operation undervoltage shutdown

INA

INB

OUTAOUTB

DIAGB/ENB

DIAGA/ENA

OUTA shorted to VCC (pure short) and undervoltage shutdown

CS V<nominal

IOUTA->OUTB

CS_DIS

ILSA

ISD_LS

ILSA

ISD_LS

Tj_LSA

TTSD_LS

VNH5180A-E Application information

Doc ID 17074 Rev 6 19/31

3 Application information

In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high.

PWM pin usage: In all cases, a “0” on the PWM pin turns off both LSA and LSB switches. When PWM rises back to “1”, LSA or LSB turn on again depending on the input pin state.

Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit protection

Note: The value of the blocking capacitor (C) depends on the application conditions and defines voltage and current ripple on supply line at PWM operation. Stored energy of the motor inductance may fly back into the blocking capacitor, if the bridge driver goes into 3-state. This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation, 500 µF per 10 A load current is recommended.

In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.

The fault conditions are:

– Overtemperature on one or both high-sides

– Short to battery condition on the output (overcurrent detection on the low-side Power MOSFET)

Possible origins of fault conditions may be:

OUTA is shorted to ground → overtemperature detection on high-side A

OUTA is shorted to VCC → low-side Power MOSFET overcurrent detection

When a fault condition is detected, the user can identify which power element is in fault by monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.

M

μC

Reg 5V+ 5V

HSA HSB

LSA LSB

VCC

DIAGA/ENA

DIAGA/ENA

CS

INA

PWM

OUTA OUTB

D

SG

b) N MOSFET

3.3K

1K

1K

1K

10K

33nF 1.5K

VCC

DIAGB/ENB

+5V

1K

3.3K

INB

1K

GND GND

Vcc

CS_DIS

1k

100K

Application information VNH5180A-E

20/31 Doc ID 17074 Rev 6

In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the respective output (OUTX) again, the input signal must rise from low to high level.

Figure 12. Behavior in fault condition (how a fault can be cleared)

Note: In case of the fault condition is not removed, the procedure for unlatching and sending the device in Stby mode is:

- Clear the fault in the device (toggle: INA if ENA = 0 or INB if ENB = 0)

- Pull low all inputs, PWM and Diag/EN pins within tDEL.

If the Diag/En pins are already low, PWM = 0, the fault can be cleared simply toggling the input. The device enters in stby mode as soon as the fault is cleared.

3.1 Reverse battery protectionThree possible solutions can be considered:

– A Schottky diode D connected to VCC pin

– An N-channel MOSFET connected to the GND pin (see Figure 11: Typical application circuit for DC to 20 kHz PWM operation short circuit protection)

– A P-channel MOSFET connected to the VCC pin

The device sustains no more than -15 A in reverse battery conditions because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of VNH5180A-E is pulled down to the VCC line (approximately -1.5 V).

VNH5180A-E Application information

Doc ID 17074 Rev 6 21/31

Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum target reverse current through microcontroller I/Os, series resistor is:

Figure 13. Half-bridge configuration

Note: The VNH5180A-E can be used as a high power half-bridge driver achieving an On resistance per leg of 90 mΩ.

Figure 14. Multi-motors configuration

Note: The VNH5180A-E can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow to put unused half-bridges in high impedance.

RVIOs VCC–

IRmax---------------------------------=

MOUTA OUTAOUTB OUTB

VCC

PWM

DIAGA/ENA

INA

DIAGB/ENB

INB

GND GND

PWM

DIAGA/ENA

INA

DIAGB/ENB

INB

M2OUTA OUTAOUTB OUTB

VCC

PWM

DIAGA/ENA

INA

DIAGB/ENB

INB

GND GND

PWM

DIAGA/ENA

INA

DIAGB/ENB

INB

M1 M3

Package and PCB thermal data VNH5180A-E

22/31 Doc ID 17074 Rev 6

4 Package and PCB thermal data

4.1 PowerSSO-36 thermal data

Figure 15. PowerSSO-36™ PC board

Double layers: footprint

Double layers: 2cm2 of Cu

Double layers: 8cm2 of Cu

Note:Board finish thickness 1.6 mm +/- 10 %, Board double layers, Board dimension 129 mm x 60 mm, Board Material FR4, Cu thickness 0.070 mm (front and back side), Thermal vias spaced on a 1.2 mm x 1.2 mm grid, Vias pad clearance thickness 0.2 mm, Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm.

VNH5180A-E Package and PCB thermal data

Doc ID 17074 Rev 6 23/31

Figure 16. Chipset configuration

Figure 17. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition

4.1.1 Thermal calculation in clockwise and anti-clockwise operation in steady-state mode

CHIP 1RthA

CHIP 2 CHIP 3

RthB RthC

RthAB RthAC

RthBC

0

10

20

30

40

50

60

70

80

0 1 2 3 4 5 6 7 8 9cm 2 of Cu Area (refer to PCB layout)

°C/W

RthARthB = RthCRthAB = RthACRthBC

Table 18. Thermal calculation in clockwise and anti-clockwise operation in steady-state mode

HSA HSB LSA LSB TjHSAB TjLSA TjLSB

ON OFF OFF ONPdHSA x RthHS + PdLSB x RthHSLS + Tamb

PdHSA x RthHSLS + PdLSB x RthLSLS + Tamb

PdHSA x RthHSLS + PdLSB x RthLS + Tamb

OFF ON ON OFFPdHSB x RthHS + PdLSA x RthHSLS + Tamb

PdHSB x RthHSLS + PdLSA x RthLS + Tamb

PdHSB x RthHSLS + PdLSA x RthLSLS + Tamb


24/31 Doc ID 17074 Rev 6

4.1.2 Thermal calculation in transient mode

Ths = Pdhs • Zhs + Zhsls • (PdlsA + PdlsB) + Tamb

TlsA = PdlsA • Zls + Pdhs • Zhsls + PdlsB • Zhsls + Tamb

TlsB = PdlsB • Zls + Pdhs • Zhsls + PdlsA • Zhsls + Tamb

Figure 18. Detailed chipset configuration

Equation 1: pulse calculation formula

where

CHIP 1Zts

CHIP 2 CHIP 3

Zls Zls

Zhsls Zhsls

Zlsls

ZTHδ RTH δ ZTHtp 1 δ–( )+⋅=

δ tp T⁄=

VNH5180A-E Package and PCB thermal data

Doc ID 17074 Rev 6 25/31

Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse

Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse

ZTH -HSD @ cu area

0.1

1

10

100

0.001 0.01 0.1 1 10 100 1000time (sec)

°C/W

HSD-8 cm^2 CuHSD-2 cm^2 CuHSD-footprintHsLsD-8 cm^2 CuHsLsD-2 cm^2 CuHsLsD-footprint

ZTH -LSD @ cu area

0.1

1

10

100

0.001 0.01 0.1 1 10 100 1000time (sec)

°C/W

LSD-8 cm^2 CuLSD-2 cm^2 CuLSD-footprintLsLsD-8 cm^2 CuLsLsD-2 cm^2 CuLsLsD-footprint

Z ls

Z lsls


26/31 Doc ID 17074 Rev 6

Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36

Table 19. Thermal parameters(1)

1. The blank space means that the value is the same as the previous one.

Area/island (cm2) Footprint 2 8

R1 = R7 (°C/W) 0.4

R2 = R8 (°C/W) 3.5

R3 (°C/W) 8

R4 (°C/W) 30 16 11

R5 (°C/W) 40 30 14

R6 (°C/W) 36 34 21

R9 = R15 (°C/W) 0.1

R10 = R16 (°C/W) 5.2

R11 = R17 (°C/W) 32 14 14

R12 = R18 (°C/W) 49 21 21

R13 = R19 (°C/W) 52 36 24

R14 = R20 (°C/W) 50 40 33

R21 = R22 = R23 (°C/W) 80 77 75

C1 = C7 = C9 = C15 (W.s/°C) 0.0005

C2 = C8 (W.s/°C) 0.008

C3 (W.s/°C) 0.09

C4 (W.s/°C) 0.5 0.8 0.8

C5 (W.s/°C) 0.8 1.4 2

C6 (W.s/°C) 7 8 10

C10 = C16 (W.s/°C) 0.009

C11 = C17 (W.s/°C) 0.09 0.07 0.07

C12 = C18 (W.s/°C) 0.45 0.45 0.45

C13 = C19 (W.s/°C) 0.8 1.2 1.4

C14 = C20 (W.s/°C) 4 5 8

C21 = C22 = C23 (W.s/°C) 0.005 0.003 0.003

VNH5180A-E Package and packing information

Doc ID 17074 Rev 6 27/31

5 Package and packing information

5.1 ECOPACK®

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

5.2 PowerSSO-36 TP package information

Figure 22. PowerSSO-36 TP package dimensions

Package and packing information VNH5180A-E

28/31 Doc ID 17074 Rev 6

Table 20. PowerSSO-36 TP mechanical data

SymbolMillimeters

Min. Typ. Max.

A 2.15 - 2.47

A2 2.15 - 2.40

a1 0 - 0.1

b 0.18 - 0.36

c 0.23 - 0.32

D 10.10 - 10.50

E 7.4 - 7.6

e - 0.5 -

e3 - 8.5 -

F 2.3

G - - 0.1

H 10.1 - 10.5

h - - 0.4

k 0 deg 8 deg

L 0.6 - 1

M 4.3

N - - 10 deg

O 1.2

Q 0.8

S 2.9

T 3.65

U 1.0

X1 1.85 2.35

Y1 3 3.5

X2 1.85 2.35

Y2 3 3.5

X3 4.7 - 5.2

Y3 3 - 3.5

Z1 0.4

Z2 0.4

VNH5180A-E Package and packing information

Doc ID 17074 Rev 6 29/31

5.3 PowerSSO-36 TP packing information

Figure 23. PowerSSO-36 TP tube shipment (no suffix)

Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”)

All dimensions are in mm.

Base Qty 49

Bulk Qty 1225Tube length (±0.5) 532A 3.5

B 13.8C (±0.1) 0.6

A

CB

Base Qty 1000Bulk Qty 1000A (max) 330

B (min) 1.5C (±0.2) 13F 20.2

G (+2 / -0) 24.4N (min) 100T (max) 30.4

Reel dimensions

Tape dimensionsAccording to Electronic Industries Association(EIA) Standard 481 rev. A, Feb. 1986

All dimensions are in mm.

Tape width W 24

Tape Hole Spacing P0 (±0.1) 4Component Spacing P 12Hole Diameter D (±0.05) 1.55

Hole Diameter D1 (min) 1.5Hole Position F (±0.1) 11.5Compartment Depth K (max) 2.85

Hole Spacing P1 (±0.1) 2

Topcovertape

End

Start

No componentsNo components Components

500mm min 500mm minEmpty components pocketssealed with cover tape.

User direction of feed

Revision history VNH5180A-E

30/31 Doc ID 17074 Rev 6

6 Revision history

Table 21. Document revision history

Date Revision Changes

11-Feb-2010 1 Initial release.

28-Sep-2010 2

Updated following tables:– Table 7: Thermal data– Table 8: Power section

– Table 12: Current sense (9 V < VCC < 18 V)

13-Oct-2010 3

Updated Chapter 3: Application information

Updated following tables:– Table 18: Thermal calculation in clockwise and anti-clockwise

operation in steady-state mode– Table 19: Thermal parameters

20-Oct-2010 4Changed document status from target specification to definitive datasheet

22-Dec-2011 5

Updated Figure 1: Block diagramAdded Table 3: Suggested connections for unused and not connected pinsTable 11: Protections and diagnostics:

– TTSD, TTR, THYST: added noteUpdated Figure 9: Waveforms in full-bridge operation and Figure 10: Waveforms in full-bridge operation (continued)

19-Sep-2013 6 Updated Disclaimer.

VNH5180A-E

Doc ID 17074 Rev 6 31/31

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