Asynchronous 8051 Microcontroller Presentation

By:

Ryan Mabry

April 18, 2005

Agenda

• 8051 Background• Motivation• Architecture• Design Flow• Design Implementation• Results• Challenges• Conclusion

8051 Background

• Developed by Intel in 1980• Widely used in embedded systems• Very popular after 25 years on the market• Official 8051 family designation is MCS 51• Based on Harvard Architecture –

Separate memory for instructions and dataROM stores program instructionsRAM stores program data

8051 Background Continued

• 8051 Predecessor was the 8048Used in IBM’s first PC keyboard

• Enhanced version of 8051 is 8052Increased Internal Memory CapacityAdditional TimerMore Registers

Motivation

• Project is based off VHDL synthesizable 8051 model developed by University of California’s Dalton Project (http://www.cs.ucr.edu/~dalton/8051)• Two Goals

A) Develop asynchronous 8051B) Use synchronous design tools in the process

• Asynchronous AdvantagesA) Lower Power ConsumptionB) No clock skew

Motivation Continued

• Asynchronous DisadvantagesA) No complete design solution toolsB) No global clock: communication must be done through handshaking or other methodsC) Must ensure timing and data integrity when using asynchronous communication methods

Synchronous Architecture

I8051_CTR

I8051_DEC

I8051_ALU

I8051_ROM

I8051_RAM

Op-code

ip

Src-1Src-2Src-3

Carry-in 1 & 2

desCarry-out 1 & 2

Overflow

ALU-Op-code

td

addr

data

tdwr

addrIs-bit-addr

dataData-bit

Ports

rst

(Rd, wr, addr, data_out, data_in)

Clock

Asynchronous Architecture

I8051_CTR

I8051_DEC

I8051_ALU

ALUWrapper

CTRWrapper

I8051_ROM

I8051_RAM

Op-code

ip

Src-1Src-2Src-3

Carry-in 1 & 2

desCarry-out 1 & 2

Overflow

ALU-Op-code

ClockingElement

req

ack

td

addr

data

tdwr

addrIs-bit-addr

dataData-bit

PortsClock

rst

(Rd, wr, addr, data_out, data_in)

Architecture Differences

• Clock is generated onboard asynchronous 8051• Clock is stopped while controller waits for ALU to complete an operation

- Implemented through handshaking signals generated by ALU and Controller Wrappers

• No excess cycles in asynchronous controller- Defined in synchronous version as clock cycles where controller is doing nothing and waiting for ALU to complete an operation

Asynchronous Design Flow

Functional Simulation

Synthesis ofSynchronous Blocks

TimingAnalysis

Asynchronous WrapperDesign

Timing Simulation

Asynchronous Design Flow Continued

• Functional Simulation – Verify Functionality Of Design

A) Standard VHDL Compilers cannot synthesizeVHDL code that implements asynchronous logicB) This project used ModelsimC) Compare controller registers, memory contentsand instructions executed in asynchronous and synchronous versions – verify to be the same

• Synchronous Block Synthesis – Synthesize synchronous parts of both 8051 microcontrollers. This project used Ambit Buildgates.

Behavioral Code -> Verilog Netlist

Asynchronous Design Flow Continued

• Timing Analysis – Generate Delay Numbers

A) Cadence Encounter generates parasitics for circuitsB) Use Synopsys Primetime for critical path analysisC) Import parasitics and verilog netlist into PrimetimeD) Remove successive ALU Operations to get delay numbers

IE: Remove division case from ALU to obtaincritical path delay for multiplication

E) Also generate critical path numbers for RAM, ROM,decoder, and controller modules

Asynchronous Design Flow Continued

• Asynchronous Wrapper Design

A) Implement delay elements for wrappers in Cadence Composer schematic editorB) Combinational logic elements in wrapperscan be designed in VHDL code and then importedC) Wire two parts together in schematic

• Timing Simulation Unable to test implementation of asynchronous designsince university does not have post-synthesis timingsimulator installed.

Design Implementation - Handshaking

Ack-

Req+Stop Clock

Ack+Start Clock

Req-

• Controller needs ALU Operation to be performed:A) Assert request line B) Stop Clock

• Once ALU Operation is finished:A) Assert acknowledge lineB) Start Clock

• Deassert request Line• Deassert acknowledge line

Design Implementation – ALU Wrapper

SelectLogic

ALUOpcode

2to1Mux

LogicalOperations

2to1Mux

AddSubtract

2to1Mux

Multiply Divide

S0S1S20 0 0

S0

11 1

S1 S2

Req

Ack

Design Implementation – ALU Wrapper Continued

• Remove operations from ALU to obtain delay numbers• Buffers used as building block for each delay element

- Delay of 114ps (Used 100ps to simplify design)• Primetime was used for critical path analysis• Apply 50% safety margin to initial numbers to account for operating conditions – temperature changes and voltage fluctuations

Delay(ps)Division 37000

15800128009000

ALU Ops

MultiplicationAdd & SubtractLogical Operations

BuffersDivision 163

303890

ALU Ops

MultiplicationAdd & SubtractLogical Operations

Design Implementation – Controller Wrapper

CTRWrapper

ALU Op-code

Ack

Req

• Asserts request signal while controller is waiting for ALU to complete operation• Deasserts request signal once acknowledge signal from ALU wrapper is received• Implemented in VHDL code

Design Implementation – Controller Modifications

• Excess Cycles EliminatedExample: ADDC_1 instruction takes 8 clock cyclesin synchronous controller and 6 clock cycles in asynchronous controller

when OP C_ADDC_1 =>

case exe_st at e is

…

end case;

when ES_5 =>

exe_st at e <= ES_6;

when ES_6 =>

exe_st at e <= ES_0;

exe_st at e <= ES_7;

when ES_7 =>

SHUT _DOW N_ALU;

cpu_st at e <= CS_1;

Cycles ES_5 and ES_6 are excess cyclesEliminated in asynchronous version

Design Implementation – Clocking Unit

. . .Inverter Chain

reqack

Clock

• When req=‘1’ and ack=‘0’ clock is stopped. Otherwise behaves as a synchronous clock• Length of inverter chain is longer than critical path in RAM to avoid timing violations• Critical path in RAM module is 30.9ns• Since inverter has delay of 50ps, inverter chain must be 682 inverters long

Results

• Targeted VTVT standard cell library developed by Virginia Tech VLSI for Telecommunications. • Asynchronous 8051 consumes more area due to onboard clock and wrappers. RAM dominates both chip areas

Asynchronous Cell Area: 72400Synchronous Cell Area: 65662

• Divmul program on Dalton website used to roughly benchmark designs in Modelsim

Asynchronous Simulation Time: 172,030nsSynchronous Simulation Time: 221,390ns

• Asynchronous 8051 is roughly 28.7% faster while using 10% more area than synchronous version

Challenges

• Had to learn all of the different toolsA) Technical assistance was available for Ambit

Buildgates and Cadence EncounterB) Resorted to user manuals and the Internet

for Synopsys Primetime• Learned other tools not necessary to design flow

- Time spent learning Synopsys Design Analyzer and Timemill could have been better spent in later stages of design flow

Conclusion

• A lot of work to change existing synchronous design to asynchronous design• Use of synchronous design tools in asynchronous design flow made process much easier• Since no post-synthesis timing simulators are installed, it is impossible to verify the correctness of the asynchronous design• I would like to thank Narender Hanchate for his time in helping me learn most of the tools used in this project