ASIC Design and Test Methodologies

Prof. MacDonald EE5375

Course Overview l  Lecture

–  First third of class – Verilog, FPGAs, synthesis, timing –  Rest of class (Testability and Design for Test concepts)

l  Logic Modeling, simulation l  Fault Modeling, Test Pattern Generation, ECC l  Design for Testability, Built-In Self Test l  Diagnosis l  Memory Testing l  JTAG

l  Lab –  Five FPGA based labs ending with a term project. –  Term project is sent through ASIC methodology and sent to fab.

l  Pre-requisites: basic logic design l  Will learn and use Verilog extensively in lab by completing an ASIC l  Course website www.ece.utep.edu/courses/web5375

Grading

l  Three exams - 10% each l  Final Exam - 20% (can replace one exam) l  Homework – worth 10% l  Labs - 40% total (20% FPGA, 20% ASIC) l  Lab / homework are generally full credit

Where does this class fit in? logic design

circuit design

synthesis

logic verification

test synthesis

place and route

timing and checks

tape-out and mask gen

fabrication

Standard Cells: Flip-Flop

Chip with circuit rows

ASIC projects

ASIC projects

CMOS – Historical Perspective

l  the 70’s: NMOS primary technology –  CMOS becomes usable in late 70’s

l  CMOS doesn’t consume power when idle – battery applications l  calculators – slide rules disappear l  digital wrist watches

l  the 80’s: CMOS dominates and the PC is born l  1985: accusations of Japanese chip-dumping

–  Japanese extend existing photolithographic technology –  US migrates to next generation tools and can’t get it working

l  the 90’s: CMOS gets smaller, faster, more integrated l  the 00’s: CMOS scaling continues but leakage

emerges

CMOS – Moore’s Law – channel length

0.01

0.1

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Year

Leffective(microns) Japanese DRAM crisis

CMOS comes on-lineDEC Alpha 500 MHz processor

First MOS 4 bit processor - Intel's 4044

my career startedworking on 0.8u DSPsat Motorola

CMOS – Moore’s Law - transistors

1,000

10,000

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1965 1970 1975 1980 1985 1990 1995 2000 2005

CMOS – Moore’s Law - speed

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CMOS – Moore’s Law – DRAMs

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DR

AM

Mbi

ts

16 Mbit DRAM

256 Mbit DRAM

1 Gbit DRAM

PPC405LP

Full Custom CMOS design

l  Only done when performance is king l  Unit cost is medium - $50 a chip l  Performance is best – 3 GHz processor l  Development cost (one time cost) is very high

–  1000 engineers working for 2 years and costed at $200k/year

–  $400 million dollar development cost – wow! –  turn around and sell 100 million chips for $150 each –  $15 billion income – wow! development cost insignificant –  moral of the story:

l  get a lot of engineers to hand tweak design for max performance

l  but you better sell a lot of them…

ASIC Chips (AKA Semi-custom)

l  Mostly logic design in Verilog and VHDL l  Little transistor-level work l  Synthesis/Place/Route cells from logic library -

tools l  Library includes

–  standard cells (i.e. ANDs, OR’s, Flip Flops) –  memories –  IO blocks (input and output of chip) –  Phase-Lock Loops –  probably developed in another company (i.e. ARM-Artisan)

l  Fabricate in a foundry (i.e. TSMC, IBM, AMI, TI) l  10 to 50 engineers in one year to design chip

ASIC Chips

l  Good trade-off between performance / price l  Unit Cost low - $5 to $10 l  Performance medium – 400 MHz l  Development cost medium

–  50 engineers for one year at $200k/year = $10 million –  sell 10 million graphics cards - chip adds $10 of value –  $100 million income (minus cost of fabrication)

l  Good approach for system level manufacturers –  Cisco, NVidia, Nokia –  Let someone else fabricate it – Fab is $5B capital expense –  need chip to differentiate product

l  router, cell phone, graphics card

FPGA Chips

l  Greatest Flexibility – update chips in customer’s hands

l  Performance low – 100 MHz l  Unit cost High - $50 to $200 per chip

–  good for low volumes only – say less than 10,000 –  can start with FPGAs and migrate to ASIC later

l  Development cost low –  2 engineers for 6 months at $200k/year = $200,000 –  no mask charges which are now approaching $1M for

ASICs l  Unit cost are getting better

–  some say FPGAs will soon take over the world

BASYS2 - $50

FPGA projects

FPGA projects

FPGA projects