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Proceedings of the
ASP-DAC '98 Asia and South Pacific Design Automation Conference 1998
February 10 - 13, 1998 Pacific0 Yokohama Yokohama, Japan
Sponsored by:
IEICE (Institute of Electronics, Information and Communication Engineers)
IPSJ (Information Processing Society of Japan) ACM SIGDA
IEEE Circuits and Systems Society
Supported by:
EIAJ (Electronics Industries Association of Japan) STARC (Semiconductor Technology Academic
Research Center)
Additional copies may be ordered from:
IEEE Order Dept. Hoes Lane P.O. Box 1331 Piscataway, NJ 08854, U.S.A.
Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, IWA 01 923. For other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Service Center, 445 Hoes Lane, P.O.Box 133 1, Piscataway, NJ 08855- 133 1. All rights reserved. Copyright 01 998 by the Instituie of Electrical and Electronics Engineers, Inc.
ASP-DAC '98 Organizing Committee General Chair:
Tokinori Kozawa STARC (Semiconductor Technology Academic Research Center) Onarimon BN Build. 5F 16-10 Shimbashi 6-chome, Minato-ku, Tokyo 105 Japan Phone: +8 1-3-3436- 1250
E-mail: [email protected]
Secretaries:
FAX: +8 1-3-3436- 1295
Toshihiro Hattori Hitachi, Ltd., hattori @crl. hi tachi .co.j p
Osamu Karatsu Advanced Telecommunications Research Institute International E-mail: [email protected]
Past Chair:
Isao Shirakawa Osaka University
Steering Committee Chair:
Tatsuo Ohtsuki Waseda University
Assistant Secretary:
Nobuyuki Hayashi Hitachi, Ltd.
Technical Program Co-chairs:
Shuji Tsukiyama Chuo University
Philip Chan The Hong Kong University of Science and Technology
Technical Program Vice Chair:
Hiroaki Kunieda Tokyo Institute of Technology
Tutorial Co-chairs:
Hidetoshi Onodera Kyoto University.
Jack Poon
Tutorial Vice Chair:
Takashi Kambe SHARP Corporation
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Design Contest Co-chairs:
Akihiko Morino NEC Corp.,
Design Contest Vice Chair:
Akinori Nishihara Tokyo Institute of Technology
EDA Techno Fair Chair:
Yoshitada Fujinami NEC Corp.
Publicity Chair:
Takashi Mitsuhashi Toshiba Corporation
Publication Chair:
Masaharu Imai Osaka University
Audio Visual Chair:
Chak-Kuen Wong Tsuneo Nakata The Chinese University of Hong Kong Fujitsu Laboratories Ltd.
Local Arrangement Chair:
Katsuhiko Seo Mitsubishi Electric Corporation
Registration Chair:
Masahiro Koyama Sony Corporation
Finance Chair: Promotion Chair:
Michiaki Muraoka Nagisa Ishiura Matsushita Electric Industry Co.,Ltd. Osaka University
IEICENLD Chair:
Hitoshi Kitazawa NTT Corp.
iv
IEICE/TGCAS Chair: ASP-DAC ‘98 SECRETARIAT:
Akinori Nishihara Tokyo Institute of Technology
IEICEIICD Chair:
Gensuke Goto Fujitsu Laboratories Ltd.
IPS J/SIGDA Chair:
Kenji Yoshida Toshiba Corporation
EIAJLEDA TC Chair:
Sagoro Hazama Fujitsu LTD.
JIPC Representative:
Akinori Kanasugi Saitama University
DAC Representative:
Fumiyasu Hirose Fujitsu Laboratories Ltd.
c/o CONVEX Inc., lchijoji Bldg., 2-3-22 Azabudai, Minato-ku, Tokyo 106 Japan Tel: +81-3-3589-3355 Fax: +8 1-3-3589-3974 E-mail: [email protected]
V
Takeo Hashimoto Senior General Manager, System LSI Division Executive Vice President, Semiconductor Company Sony Corporation
Tatsuo lzawa Senior Vice President, NTT
Susumu Kohyama Corporate Director and Vice President, Deputy Group Executive, Semiconductor Group, Toshiba Corp.
Susumu Koike Director, Corporate Semiconductor Development Division, Matsushita Electric Industrial Co. Ltd.
Heihachi Matsumoto General Manager, System LSI Development Center Mitsubishi Electric Corp.
Shigeo Misaka Corporate Senior Executive Director, Electronic Components and Device business, Sharp Corp.
Hisakazu Mukai Fellow, Oki Electric Industry Co., Ltd.
Hajime Sasaki Senior Executive Vice President, NEC Corp.
Shigeru Sat0 President, Fujitsu Labs., Ltd.
Yasutsugu Takeda Senior Executive Managing Director, Member of the Board, Hitachi Ltd.
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ASP-DAC Steering Committee Chairperson:
Tatsuo Ohtsuki Department of Electronics, Information & Communication Engineering Waseda University 3-4-1 Okubo, Shinjuku Tokyo 169, Japan Tel: +8 1-3-5286-3387 Fax: +8 1-3-3203-91 84 E-mail: [email protected]
Vice Chairperson:
Fumiyasu Hirose Fujitsu Laboratories Ltd. E-mail: [email protected]
Secretary:
Tsuneo Nakata Fujitsu Laboratories Ltd. E-mail: [email protected]
ASP-DAC '98 General Chair:
Tokinori Kozawa Semiconductor Technology Academic Research Center (STARC)
ASP-DAC '98 Secretary:
Toshihiro Hattori Hitachi, Ltd.
ASP-DAC '98 Technical Program Co-chairs:
Shuji Tsukiyama Chuo University
Philip Chan The Hong Kong University of Science and Technology
IEICE TGCAS Chair:
Akinori Nishihara Tokyo Institute of Technology
IEICE TGVLD Chair:
Hitoshi Kitazawa NTT Corporation
IEICE TGICD Chair:
Gensuke Goto Fujitsu Laboratories Ltd.
IPS J SIGDA Chair:
Kenji Yoshida Toshiba Corporation
JIPC Representative:
Kunihiro Asada- University of Tokyo
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ACM SIGDA Representative:
Nikil Dutt Chong-Min Kyung University of California at Irvine Korea Advanced Institute of Science and
Technology
IEEE CAS Representative:
Graham R. Hellestrand University of New South Wales
Hon-Wai Leong National University of Singapore
DAC Representative:
Basant R. Chawla Lucent Technologies
EDA Techno Fair Chair:
Yoshitada Fujinami NEC Corporation
International Members:
Xian-Long Hong Tsinghua University, Beijing
Youn-Long Steve Lin Tsing Hua University, Hsin-Chu
Sunil D. Sherlekar Silicon Automation Systems (India) Pvt. Ltd.
EIAJ EDA TC Representative:
Sagoro Hazama David Skellern Fujttsu Limited Macquarie University
Omar Wing The Chinese University of Hong Kong
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Ellen J. Yoffa IBM Corporation
Qianling Zhang Fudan University, Shanghai
Advisory Members (Industries):
Kazuyuki Hirakawa Oki Electric Industry Co., Ltd.
Eisaburo lwamoto Sony Corporation
Takashi Kambe Sharp Corporation
Nobuaki Kawato Fujitsu Laboratories of America
Shigeo Kuninobu Matsushita Electric Industrial Co., Ltd.
Masami Masuyama Seiko Instruments Inc.
Shin'ichi Murai Mitsubishi Electric Corporation
Fusao Wada Zuken Inc.
Osamu Karatsu Kenji Yoshida Advanced Telecommunication Research Toshiba Corporation Institute International
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Takeshi Yoshimura NEC Corporation
Masaharu Imai Osaka University
Michitaka Kameyama Tohoku University
Hiroaki Kunieda Tokyo Institute of Technology
Yoshikazu Miyanaga Hokkaido University
Advisory Members (Academia):
Toshiro Akino Yukihiro Nakamura Kinki University Kyoto University
Hideo Fujiwara Hidetoshi Onodera Nara Institute of Science and Technology Kyoto University
Tsutomu Sasao Kyushu Institute of Technology
lsao Shirakawa Osaka University
Kazuhiro Ueda Shibaura Institute of Technology
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Shin'ichi Wakabayashi Hiroshima University
Masao Yanagisawa (formerly Sato) Waseda University
Hiroto Yasuura Kyushu University
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Welcome to ASP-DAC '98
This is the third meeting of the Asia and South Pacific Design Automation Conference (ASP-DAC '98) with EDA Techno Fair '98 to be held in the Pacifico Yokohama, Japan. This conference provides an international forum for researchers and engineers worldwide in electronic systems, VLSI design, and CADEDA. ASP-DAC is regarded as a sister conference of DAC in the U.S.
A recent topic in design technology has been the Design Productivity Crisis in the deep submicron era. In order to overcome this difficulty it will be essential to have interaction between different communities, that is, academia, industry, electronic system and circuit design engineers, and EDA (Electronic Design Automation) developers.
ASP-DAC '98 will facilitate technical interchanges among people in these various communities and thereby advances the state of the art in VLSI design and design automation.
Keynote speakers will present topics and strategies for VLSI design in the deep submicron era. Gady Singer, general manager of design technology at Intel, will talk about the strategy for breaking through the design difficulties that will be encountered in developing general-purpose microprocessors, including the Pentium series, in future. Hisashi Yamada, Chief Fellow of Technology of Toshiba, will talk about his group's experience in developing a DVD multimedia system. Anantha Chandrakasan will talk about design methodologies for low power LSI such as dynamically variable supply, multiple and variable threshold CMOS, self-powered systems, custom vs. programmable implementations, etc.
The program, decided by the Technical Program Committee (TPC), consists of technical sessions, special sessions, and panel sessions. The university design contest is the second trial to encourage academics to enter VLSI implementation.Prof. Onodera has selected five one-day tutorials on Tuesday. Topics are design for merging logic and DRAM, high-performance system LSI design, deep submicron design, co-design with IP core, and low-power design.
EDA Techno Fair '98 (the fifth of these annual premier Japanese EDA shows) is collocated with ASP-DAC '98. Exhibitors are companies including EDA vendors, EDA developers, and ASIC vendors.
I would like to thank all the members of the steering committee, organizing committee, technical program committee, and university design contest committee for their voluntary services.
I hope you enjoy the conference and the various events to be held in conjunction with it.
General Chair, ASP-DAG '98
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ASP-DAC '98 Technical Program Committee
Co-chairs:
Shuji Tsukiyama Chuo University Dept. ISC, Chuo University 1-1 3-27 Kasuga, Bunkyo-ku, Tokyo 1 12, Japan Phone: +8 1-3-38 17- 187 1
Email: tsuki @elect.chuo-u.ac.jp
Philip Chan Hong Kong University of Science and Technology Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology Clear Water Bay, Hong Kong Phone: +852-2358-704 1
Email: eepchan @ee.ust.hk
Vice-Chair:
Hiroaki Kunieda Tokyo Institute of Technology Dept. of Electrical and Electronic Engineering Tokyo Institute of Technology 2-12-1 Ookayama, Meguro-ku, Tokyo 152, Japan Phone: +8 1-3-5734-2574
Email: [email protected]
Secretaries:
Kazutoshi Wakabayashi C & C Research Labs. NEC Corporation 4-1-1 Miyazaki, Miyamae-ku, Kawasaki, Kanagawa 216, Japan Phone: +8 1-44-856-2 134
Email: [email protected]
Kazuhito Ito Department of Electrical and Electronic Systems Saitama University 255 Shimookubo, Urawa, Saitama 338, Japan Phone: +8 1-48-858-373 1
Email: [email protected]
TPC Members:
Hideharu Amano Keio Univ.
FAX: +8 1-3-3817-1 847
FAX: +852-2358-1485
FAX: +81-3-5734-2842
FAX: +8 1-44-856-2235
FAX: +8 1-48-855-0940
Kunitoshi Aono Matsushita Electric Industrial Co., Ltd.
Hideki Asai Shizuoka Univ.
M. Balakrishnan Indian Inst. of Technology, Delhi
Neil W. Bergmann
Jinian Bian
Queensland Univ. of Technology
Tsinghua Univ.
Tapan J. Chakraborty
Kwang-Ting (Tim) Cheng
Bell Labs
Univ. of California. Santa Barbara
Ying S. Cheung Univ. of Hong Kong
Mely Chen Chi CCL/ITRI
Shih-Chieh Chang
Henk Corporaal
Zdzislaw Czarnul Toshiba Corp.
Inst. of Systems & Information Technologies /Kyushu
Masato Edahiro NEC Corp.
Kunihiro Fujiyoshi Tokyo Univ. of Agriculture & Technology
Masahiro Fukui Matsushita Electric Industrial Co., Ltd.
National Chung-Cheng Univ.
Delft Univ. of Technology
Hiroshi Date
Tetsuya Fujimoto Sharp Corp.
Hisanori Fujisawa
Raanan D. Gewirtzman
Fujitsu Labs. Ltd.
IBM Corp.
Sandeep K. Gupta Univ. of Southern California
Soonhoi Ha Seoul National Univ.
Kiyoharu Hamaguchi Osaka Univ.
Reiner W. Hartenstein Universitaet Kaiserslautern
Kazumi Hatayama Hitachi Ltd.
Ikuo Harada NTT Corp.
Terumine Hayashi Mie Univ.
Graham R. Hellestrand Univ. of New South Wales
John Hillawi DA Solutions Ltd.
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Hiromi Hiraishi Kyoto Sangyo Univ.
Xianlong Hong
Tomoo Inoue
Tsinghua Univ.
Nara Inst. of Science and Technology
Nagisa lshiura Osaka Univ.
Kazuhiko Iwasaki Tokyo Metropolitan Univ.
Fujitsu Labs. of America
Canon Information Systems Research Australia
Jawahar Jain
David M. Johnstone
Wen-Ben Jone National Chung-Cheng Univ.
Kyushu Inst. of Technology
Fujitsu Labs. Ltd.
Korea Advanced Inst. of Science and Technology
Seiji Kajihara
Kaoru Kawamura
Beomsup Kim
Seok-Yoon Kim Soong Si1 Univ.
Hitoshi Kitazawa NTT Corp.
Shinji Kimura Nara Inst. of Science and Technology
Hideaki Kobayashi
Tetsushi Koide
Knowledge Based Silicon Corp.
Hiroshima Univ
Sharad Malik Princeton Univ.
Yossi Malka IBM Corp., Israel
Univ. of Dortmund Peter Marwedel
Hiroshi Matsumoto NEC Corp.
Yusuke Matsunaga Fujitsu Labs. Ltd.
Eiji Masuda Toshiba Corp.
Kazuhiko Matsumoto Hitachi Ltd.
Yinghua Min Chinese Academy of Sciences
Hisao Koizumi Mitsubishi Electric Corp.
Stanley J . Krolikoski Cadence
Yuji Kukimoto
Wolfgang Kunz
Hajime Kubosawa
Univ. of California, Berkeley
Univ. of Potsdam
Fujitsu Labolatories
Feipei Lai National Taiwan Univ.
Tak-Kwan Lee Chinese Univ. of Hong Kong
Cueesang Lee Chonnam National Univ
K. J . Lee National Cheng-Kung Univ.
Howard Luong Hong Kong Univ. of Science and Technology
Shin-ichi Minato NTT Corp.
Yukiya Miura Tokyo Metropolitan Univ
Toshiaki Miyazaki NTT Corp.
Mitiko Miura-Mattausch Hiroshima Univ.
Mutsumi Mitarashi Oki Electric Industry Co.,Ltd.
Seijiro Moriyama Toshiba Corp.
Vasily G. Moshnyaga Kyoto Univ.
Akira Nagoya NTT Corp.
Tsuneo Nakata Fujitsu Labs. Ltd.
Takashi Nanya
Kenji Numata
Hiroyuki Ochi
Univ. of Tokyo
Toshiba Corp.
Hiroshima City Univ.
Kiyoshi Oguri NTT Corp.
Naohisa Ohta NTT Corp.
Hidetoshi Onodera Kyoto Univ.
Osaka Univ. Takao Onoye
Sandeep Pagey Cadence Design Systems India
Texas Instruments, India Rubin A. Parekhji
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Manish Pandey
Keshab K. Parhi
Carnegie Mellon Univ.
Univ. of Minnesota
Miodrag Potkonjak
Changge Qiao
Jan M. Rabaey
Tsutomu Sasao
Univ. of California, Los Angels
Tsinghua Univ.
Univ. of California, Berkeley
Kyushu Inst. of Technology
NTT Corp.
Hyunchul Shin HanYang Univ.
Yoichi Shiraishi Gunma Univ.
Hiroshi Sawada
Toru Shonai Hitachi Ltd.
Toshiyuki Shibuya
Naoyuki Shigyo
Fumio Suzuki
Fujitsu Labs. Ltd.
Toshiba Corp.
Mitsubishi Electric Corp.
Atsushi Takahara NTT Corp.
Fudan Univ. Pusan Tang
Shigetaka Takagi Tokyo Inst. of Technology
Koichiro Takayama Fujitsu Labs. Ltd.
Yoshinori Takeuchi Osaka Univ.
Nozomu Togawa Waseda Univ.
Masahiko Toyonaga
Jiarong Tong
Matsushita Electric Industrial Co., Ltd.
Fudan Univ.
Toru Toyabe Toyo Univ.
Chi-ying Tsui Hong Kong Univ. of Science and Technology
Akihiro Tsutsui NTT Corp.
Tsuneo Tsukahara NTT Corp.
Kazuhiro Ueda Shibaura Inst. of Technology
Nachiket Urdhwareshe Silicon Automation Systems
Ad J . van de Goor Delft Univ. of Technology
G. Venkatesh Silicon Automation Systems
Shin'ichi Wakabayashi Hiroshima Univ.
Takahiro Watanabe Yamaguchi Univ.
Cadence European Labs.
National Chung-Cheng Univ.
Akita Univ.
Yosinori Watanabe
Jinn-Shyan Wang
Xiaoqing Wen
C.-K. Wong Chinese Univ. of Hong Kong
Hei Wong
Allen C.-W. Wu
City Univ. of Hong Kong
Tsing Hua Univ.
City Univ. of Hong Kong Angus Wu
Cheng-Wen Wu Tsing Hua Univ.
Yu-Liang Wu Chinese Univ. of Hong Kong
Hans-Joachim Wunderlich Univ. of Stuttgart
Tsinghua Univ.
Hangzhou Inst. of Electronics Engineering
Osaka City Univ.
Masayuki Yamaguchi Sharp Corp.
Chingwei Yeh National Chung-Cheng Univ.
Tokumi Yokohira Okayama Univ.
Hitachi Ltd.
Hongxi Xue
Xiaolang Yan
Shoichiro Yamada
Goichi Yokomizo
Tomohiro Yoneda Tokyo Inst. of Technology
Takeshi Yoshimura NEC Corp.
Michio Yotsuyanagi NEC Corp.
Kyoji Yuyama Hitachi Ltd.
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C
On behalf of the Technical Program Committee, we would like to welcome you to ASP-DAC '98, which is the third, but the second after changing biennial to annual, in a series of international conferences to be held in Asia and South Pacific regions concerning the fields of design automation and design methodology of electronic systems. This year, we received more than 120 good papers from around 12 countries. The high technical standard of the submitted papers reflects that researchers and engineers in the fields have begun to recognize shuji Tsukiyama this annual conference as an important forum for interchanging their ideas and opinions.
Philip Chan
In order to further stimulate the discussion between system/circuit designers and design automation researchers, we have tried to emphasize design methodology more than the last year, and hence the "Area of Interest" in the Call for Papers were divided into two big categories; "Design Technology" and "Design Automation Technology."
The Technical Program Committee consisting of experts from industry and academia around the world was organized into 9 groups according to the categories of the Area of Interest. Each group conducted the peer review and discussion for evaluating and selecting the submitted papers. Thanks to their great efforts, 74 regular and short papers were accepted and arranged in the three regular tracks of the technical program.
Similarly to the last ASP-DAC, the technical program is structured under four parallel tracks; three regular tracks and one special track. Special sessions composed of invited talks and panel sessions are incorporated into the special track, together with University LSI Design Contest presentation and poster. These invited talks and panels are selected carefully by the Technical Program Committee from the hot topics in Design Technology and Design Automation Technology, and features the conference. Since the embedded tutorials were well received and attended last year, seven embedded tutorials are put into the regular tracks in order to introduce the state of the art. Please attend the sessions you are interested in and enjoy stimulating discussions about Design Technology and Design Automation Technology.
Finally, we would like to take this opportunity to thank all individuals, in particular, all authors, members of the Technical Program Committee, and session co-chairs. Without their contributions and dedications, the conference could not maintain the high level of quality. We believe that due to their efforts, ASP-DAC is establishing its position in the fastest developing area of the high-technology world.
Y
uji Tsukiyama hilip Chan
Technical Program Co-chairs, ASP-DAC '98
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Best Paper Award Candidates Asia and South Pacific Design Automation Conference 1998 (ASP-DAC '98)
1A.2 Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R- MMIC Front-End for 1.9-GHz Personal Communications
Kazuya Yamamoto, Takao Moriwaki, Yutaka Yoshii, Takayuki Fujii, Jun Otsuji, Yoshinobu Sasaki, Yukio Miyazaki, Kazuo Nishitani
2C.3 Concurrent Technology, Device, and Circuit Development for EEPROMs
U. Feldmann, R. Kakoschke, M. Miura-Mattausch, G. Schraud
3C. 1 On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design
Mohit Sahni, Takashi Nanya
3C.2 Practical Synthesis of Speed-Independent Circuits Using Unfoldings
Uisok Kim, Dong-Ik Lee
5A. 1 Software Licensing Models in the EDA Industry
Dinesh R. Bettadapur
5A.2 Pre-layout Delay Calculation Specification for CMOS ASIC Libraries
Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, k n y a Tabuchi
5B. 1 A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs
Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki
8B .3 Automatic Test Generation for Linear Analog Circuits under Parameter Variations
C.-J. Richard Shi, Michael W. Tian
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Contest Co-chairs' e
On behalf of the University LSI Design Contest Committee, we would like to welcome you to the University LSI Design Contest. The aim of this Contest is to encourage the education and research on LSI design and its implementation into chips, at universities and other educational organizations, by providing the opportunities to present and discuss those designs at the conference. And also, a certain number of awards will be given to the designs selected from those presented at the conference.
Akihiko Morino Chak-Kuen Wong Akinori Nishihara
Application areas, or types of circuits include, Microprocessors, Digital Signal processing, Custom Application Specific Circuits, and Analog and Mixed-Signal Circuits. Methods, or technologies employed in the implementation include, full custom and cell-based LSIs, gate arrays,and field programmable devices, including FPGA/PLDs.
This year, thirteen selected designs from three countries will be disclosed in Session 5D, with a short aural presentations, followed by Q & A, using posters. Demonstrations on the achievements will also be made for some designs. Opportunities for demonstrations at EDA TechnoFair'98 will be provided for the above designs.
Submitted designs were reviewed by the members of the University LSI Design Contest Committee, based on the following criteria: ( 1) Reliability of design and implementation, (2) Quality of implementation, (3) Performance of the design, (4) Originality, and ( 5 ) Additional factors. In the selection process, emphasis were placed more on the above criteria (1) and (2). As a result, thirteen designs were selected for the presentation at the conference.
It is our great pleasure if the design contest will contribute to the promotion of LSI design and its implementation at universities and other educational organizations. It is also our hope that many people in the industry will be interested in the contest.
Akihi orino
Co-chairs, University LSI Design Contest
Akinori Nishihara
Vice Chiar, University LSI Design Contest
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University LSI Design Contest Committee
Co-chairs:
Akihiko Morino NEC Corp.
Chak-Kuen Wong The Chinese University of Hong Kong
Vice Chair:
Akinori Nishihara Tokyo Institute of Technology
Secretaries:
Mineo Kaneko Japan Advanced Institute of Science and Technology
Hiroaki Hirata Kyoto Institute of Technology
Members:
Yukio Akazawa N I T Electronics Corp.
Hideharu Amano Keio Univ.
Liang-Gee Chen National Taiwan Univ.
Howard Chen IBM
Tadayoshi (Tad) Enomoto Chuo Univ.
Graham Hellestrand The Univ. of New South Wales
Akihiro Higashi Fujitsu Labs. Ltd.
Nagisa Ishiura Osaka Univ.
Beomsup Kim Korea Advanced Inst. of Science and Technology
Hitoshi Kitazawa N'IT System Electronics Labs.
Noboru Kubo Sharp Corp.
Chong-Min Kyung Korea Advanced Inst. of Science and Technology
S. Madhusudhanan Silicon Automation Systems Ltd.
Eiji Masuda Toshiba Corp.
Yoshikazu Miyanaga Hokkaido Univ.
Yasuhiro Nakakura Matsushita Electric Industrial Co., Ltd.
Yasunobu Nakase Mitsubishi Electric Corp.
Keisuke Okada Mitsubishi Electric Corp.
Jan M. Rabaey Univ. of California, Berkeley
Keitaro Sekine Science Univ. of Tokyo
Chandra Shekhar Central Electronics Engineering Research Inst. (CEERI)
Chi-ying Tsui Hong Kong Univ. of Science and Technology
Toshirou Tsukada Hitachi, Ltd.
Yoshiaki Umezawa Oki Electric Industry Co., Ltd.
Neil Weste Macquarie Univ.
Futao Yamaguchi SONY Corp.
Kaichi Yamamoto SONY Corp.
Hironori Yamauchi Ritsumeikan Univ.
Yoichi Yano NEC Corp.
Jun Yu Fudan Univ
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ontest Summary
Country
Japan
Korea
China
Australia
Submission
Number of Submission
8
4
1
1
Fourteen designs were submitted from four countries, Japan, Korea, China, and Australia. Statistics in terms of the application areas, and design methodologies are as follows:
A: Analog, A/D Mixed, D: Digital, M: Microprocessor, and C: Custom/Appl F/C: Full Custom, G/A: Gate Array, and F/P: FPGNPLD
Selection Process 1. Submitted designs were subjected to the reviewing by all of the committee members.
Each committee member was requested to fill in the review sheet, including the recommendation points and comments.
2. Design selection was carried out at the committee meeting held on Wednesday, October 8. Discussion on the selectiordrejection of each design was carried out, based on the recommendation points and comments.
3. As a result, 13 designs were selected, and one design (#09) was rejected. 4. A candidate for the Outstanding Design Award, and two candidates for Special Feature
Awards were selected.
Session Assignment 1. The session has 2 hours time slot, for easier presentation of the designs. 2. Presentations will be made in a sequence of microprocessors, digital, custom, and
3. For each design, an aural presentation for 7 minutes, and Q&A by the use of the analog.
posters are planned.
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University LSI Design Contest Award
Recipient for Outstanding Award
"TITAC-2: An Asynchronous 32-bit Microprocessor"
Akihiro Takamura", Masashi Imai+, Motokazu Ozawa*, Izumi Fukasaku", Taro Fujii*, Masashi Kuwako+, Yoichiro Ueno*, and Takashi Nanya*+
* Graduate School of Information Science and Engineering Tokyo Institute of Technology, Tokyo, Japan
+ Research Center for Advanced Science and Technology University of Tokyo, Tokyo, Japan
(Microprocessor, Cell-based LSI)
This paper describes an asynchronous microprocessor design, based on MIPS R2000 microprocessor, but targeted to asynchronous circuitry for 0.5 pm CMOS Standard Cell. Its achievements include not only the world-first working. large scale real microprocessor design by asynchronous circuits, but also wide range of device behavior testing to guarantee the correctness of the design. These design features, testing method, complexity of the development, and well-written paper clearly distinguish itself from other submitted designs. Thus, this design is worthy of the Outstanding Design Award.
Recipient for Special Feature Award
"MetaCore: A Configurable & Instruction-Level Extensible DSP Core"
Jin-Hyuk Yang, Byung-Woon Kim, Sung-Won Seo, Sang-Jun Wam, Chang-Ho Ryu, Jang-Ho Cho, and Chong-Min Kyung
Department of Electrical Engineering Korea Advanced Institute of Science and Technology, Taejon, Korea
(Digital Signal Processing, Cell-based LSI)
In order to pursue cost-effective solutions for diversified applications, a configurable and instruction-level extensible DSP will be useful and viable. This design proposes such a DSP core named MetaCore, and a platform for its developmeint. The MetaCore has an architecture to facilitate tuning itself to specific applications by changing a set of parameters. The development platform provides retargetability to support configurability and instruction-level extensibility. The first version of MetaCore, which is a 16-bit fixed point DSP core, is realized by using 0.6 pm three level metal CMOS process, has a core size of 4.5" x 5mm, and 50 MIPS performance. Judging from the design rule, and standard cell design methodology employed, the above data are considered to be excellent. Above achievements demonstrate the excellent feature of the design as compared with other submitted designs. Thus, this design deserves a Special Feature Award.
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Recipient for Special Feature Award
"A CMOS Smart Image Sensor LSI for Focal-Plane Compression"
Shoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata", Shiro Doushou" and Akira Matsuzawa"
Department of Information and Computer Sciences Toyohashi University of Technology
*Matsushita Electric Industrial Co. Ltd.
(Analog and Mixed-Signal Circuits, Full-Custom LSI)
A CMOS imaging array with block access function and an analog two-dimensional discrete cosine transform (DCT) processor using switched capacitor circuits are implemented in one chip. Two-dimensional 8x8-point DCT is computed by repeated 1-D 8-point DCTs. SC circuits perform 32 multiplications and 32 additions in 8-point DCT in parallel. This chip is combined with an adaptive A-D converter and an entropy coder to produce motion JPEG signals. Analog approach makes it possible to reduce the power dissipation. The chip consisting of 128 x 128- pixel imager and a DCT processor is fabricated with 0.35 pm CMOS. The chip size is 4.95 mm x 4.95 mm and it consumes less than 20 mW. Although there are some contribution from a company, the original idea, circuit design and layout design come from university side. The design shows the performance feasibility of analog approach, and deserves a Special Feature Award.
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Keynote Address I EDA beyond 2000 - Evolution or Revolution?
Gadi Singer General Manager, Design Technology, Microprocessor Group, Intel
The keynote address will analyze future semiconductor design trends and characterize the EDA capabilities that can help meet some of the critical design and test challenges for the year 2000 and beyond. Further, the address will offer an analysis of the current state and the future direction of the EDA industry from four perspectives. In each area, the potential inflection points will be sought, identifying where the EDA world is likely to experience radical changes compared to the evolutionary trends of the past decade. The four perspectives are -
1.
2.
3.
4.
Technology: Chip designs of the future will have to address ever-increasing complexity (>50M transistors), high frequencies (>2 GHz), low voltages (<lV), and surging currents (>100A). After a look at current trends, the address will examine the implications for the tools and methods needed to design and test the new generations of chips. In addition, ways to enhance the alignment between the semiconductor and EDA roadmaps will be explored.
Computing: Today's computing paradigms are based on decade-old concepts and may not be able to meet future design complexity and design productivity needs. The address will outline the opportunities created by the new computing/software era, including multiple CPUs, tightly integrated high horsepower workstation farms, seamless integration of office and engineering applications, use of the Internet, and similar phenomena.
Business: The continuing consolidation of the EDA industry and new business trends, such as the push into design services, is leading to a new set of business dynamics in the industry. The address will examine these and other market forces (system on chip, the new age IP market) and assess the implications for the EDA industry.
Standards and Interoperability: The address will draw comparisons between the EDA industry and other industries in terms of their use of standards and resulting interoperability. A demonstration of how standards and interoperability will be one of the keys to growing the industry and staying aligned with future design needs will be presented. The address will also provide a brief overview of the EDA industry council's efforts in trying to bring about greater standardization in the industry.
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and Role of LSI in Multi-Source Multimedia
isashi Yamada Toshiba Corp.
LSI has been the key technology to construct electronic systems for past 30 years. Any information technology or signal processing technology has been depending on the LSI technology at real implementation stage. Although the basic theory was established long before the real application of the theory, actual introduction can be predicted by estimating the hardware size of the system required for the real implementation. Since LSI progress has been measured by the DRAM capacity and microprocessor computational power, we can estimate the logic LSI through put by those LSI progress power. DVD has been proposed considering the LSI progress and it's introduction timing was estimated from the cost estimation of the key LSI such as MPEG decompression LSI.
DVD is proposed as a unified media for multi-source multimedia era that provides unified environment for multi-source handling. Any software or application of information processing technology is depending on the LSI technology and system integration is key issue for cost reduction and compact system realization.
ainly there is two major area for role of LSI, one is performance improvement and cost reduction by increasing system integration scale namely system on chip, and the other one is miniaturization and power consumption reduction by integration to realize mobile equipment. There are always trade-off between power consumption and system complexity. Usually, in digital system, system designer want to integrate more sophisticated feature into the LSI, but always there is a definite limit for power consumption for mobile equipment. So the key issue to win the competition is how fast you can achieve system integration and low power consumption. Since life of a LSI is very short until that becomes mature, then continuous evolution of the integration is always required. From the environment stated above, CAD technology becomes key issue for competition in multi-source multimedia era. More accurate and user friendly design tool is the most important for competition today.
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Keynote Address I11 Trends in Energy Efficient Computing
Anantha Chandrakasan Massachusetts Institute of Technology, Cambridge
Energy efficient system design requires systematic optimization at all levels of the design abstraction ranging from process technology and logic design to architectures and algorithms. Significant advances have been made in reducing the energy consumption of digital processors over the past few years and this presentation will highlight some the recent directions in energy efficient computing.
The energy expended per operation is continually improving as the power supply voltages are scaled. Reduced device thresholds and electronic tuning techniques have enabled the aggressive scaling of power supply voltages, but the increased leakaige is not acceptable for "event-driven" computation that have long idle periods. Several emerging process technologies such as Multiple and Variable threshold CMOS (bulk and SOI) have addressed the idle mode leakage problem by providing a "knob" to dynamically adjust leakage currents; this enables high- performance during active periods and low-standby lealkage. These technologies pose several new challenges in fabrication technology, design methodologies, and CAD tools.
In many applications, it is desirable to design digital processors that allow a trade-off between the quality of service provided and the average energy consumption (e.g., trading the level of encryption/security for energy). For such applications, there is significant energy advantage in using an embedded power supply scheme where the voltage can be adapted based on computational demand. Rather than designing a system with a static supply to meet a specific timing constraint under worst case conditions (i.e., establishing the feedback around the power converter to fix the output voltage), it is more energy efficient to allow the voltage to vary such that the timing constraints are just met at any given temperature and operating conditions; this is accomplished by establishing the feedback around a fixed processing rate or delay. This approach requires the design of high-efficiency switching regulators that have a fast transient response. Embedded power supply systems can minimize energy consumption under varying temperature, process parameters and computational workload.
Voltage scaling alone is not enough as the complexity increases and as applications that use the portable energy source require further energy reductions. The switched capacitance must be minimized by avoiding unnecessary transitions beyond what is required to implement a given logic function and by minimizing node capacitances. While several interesting techniques have been proposed and used (e.g., clock gating, transistor sizing, compilation techniques, etc.), many opportunities exist to reduce the switched capacitance by exploiting properties of specific systems. For example, in some video applications, exploiting knowledge about signal distributions during architecture development can save more than order of magnitude in energy at a fixed power supply voltage. Similarly, restructuring algorithms to exploit communications capabilities of emerging wireless systems can save orders of magnitude in power consumption of the energy constrained portable unit.
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le of Contents
... Organizing Committee ..................................................................................................... 111
Advisory Board Members ................................................................................................ vi
Steering Committee .......................................................................................................... vii
General Chair's Message .................................................................................................. xii
... Technical Program Committee ......................................................................................... xi11
Technical Program Co-chairs' Message ........................................................................... xvi
Best Paper Award Candidates ........................................................................................... xvii
University LSI Design Contest Co-chairs' Message ........................................................ xviii
University LSI Design Contest Committee ...................................................................... xix
University LSI Design Contest Summary ........................................................................ xx
University LSI Design Contest Award ............................................................................. xxi
Keynotes Address ............................................................................................................. xxiii
Conference Author Index ................................................................................................. 601
ASP-DAC '99 Call for Papers ........................................................................................... 605
Call for Designs ASP-DAC '99 University Design Contest ............................................. 606
Session 1A High-speed Design Techniques
Chair: Naohisa Ohta Co-chair: Atsushi Kameyama High-speed GaAs MESFET Digital IC Design for Optical Communication Systems 1A.1 Kimikazu Sano, Koichi Narahara, Koichi Murata, Taiichi Otsuji, Kiyomitsu Onodera ............... 1
1A.2 Design and Experimental Results of a 2V-Operation Single-Chip GaAs T/R-MMIC Front-End for 1.9-GHz Personal Communications Kazuya Yamamoto, Takao Moriwaki, Yutaka Yoshii, Takayuki Fujii, Jun Otsuji, Yoshinobu Sasaki, Yukio Miyazaki, Kazuo Nishitani.. ................................................................... I
1A.3 A Simple Architecture of Low Voltage GHz BiCMOS Four-Quadrant Analogue Multiplier using Complementary Voltage Follower Simion Cimin Li, Reggie Chien, Jerry Chien, Kaung-Long Lin .................................................... 13
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Session 1B Hardware/Software Codesiign I
lB. l
Chair: Graham R. Hellestrand Co-chair: Kei Suzuki (Embedded Tutorial) HW-SW Co-Synthesis: The Present and The Future Sri Parameswaran .........................................................................................................................
1B.3 Parallelization in Co-Compilation for Configurable Accelerators Reiner W Hartenstein, Jiirgen Beckel; Michael Herz, U1,rich Nageldinger ..................................
Session 1C Technology CAD for Interconnections and Environments
Chair: Naoyuki Shigyo Co-chair: Uwe Feldmann Delay and Noise Formulas for Capacitively Coupled ]Distributed RC Lines IC.1 Hiroshi Kawaguchi, Takayasu Sakurai ................................................................. ... ... ... .., ,.. ... .., ... ...
1 c.2 Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs Davide Pandini, Primo Scandolara, Carlo Guardiani .................................................................
1C.3 A New LSI Performance Prediction Model for Interconnection Analysis of Future LSIs Shuji Takahashi, Masato Edahiro, Yoshihiro Hayashi ..................................................................
Session 1D (Design General Manager Panel) Design Technology Challenges in the Design Productivity Crisis
Organizer: Tokinori Kozawa Moderator: A. Richard Newton Panelists: lchiro Fujitaka, Tetsuya lizuka, Gadi Singer, Dave Shepard ...................................
Session 2A Combinational Logic Synthesis
Chair: Yoshinori Watanabe CO-C hai r: New Methods to Find Optimal Non-Disjoint Bi-Decoinpositions
Da vide Pandini 2A. I
Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya .....................................................................
2A.2 A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks Debatosh Debnath. Tsutomu Sasao ...............................................................................................
2A.3 ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions Gueesang Lee, Rolf Drechsler .......................................................................................................
2A.4 Function Decomposition and Synthesis Using Linear Sifting Christoph Meinel, Fabio Somenzi, Thorsten Theobald .................................................................
19
23
35
45
51
57
59
69
75
81
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Session 2B Compiler for Embedded Processors
Chair: Rainer Leupers Co-chair: Nagisa Ishiura Optimized Array Index Computation in DSP Programs 2B.1 Rainer Leupers, Anupam Basu, Peter Marwedel ..........................................................................
2B.2 Binding and Scheduling Algorithms for Highly Retargetable Compilation Masayuki Yamaguchi, Nagisa Ishiura, Takashi Kambe ................................................................
2B.3 Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines Hui Guo, Sri Parameswaran .........................................................................................................
2B .4 Quantitative Selection of Media Benchmarks Chunho Lee, Miodrag M. Potkonjak .............................................................................................
Session 2C Technology CAD for Lowest Level Design
Chair: Hiroshi Matsumoto Co-chair: Carlo Guardiani Reliable Threshold Voltage Determination for Sub-O.lpm Gate Length MOSFET's Morikazu Tsuno, Masato Suga, Masayasu Tanaka, Kentaro Shibahara, Michiko Miura-Mattausch, Masataka Hirose ...............................................................................
2c. 1
2c.2 Inverse Modeling - A Promising Approach to Know What is Made and What should be Made S. Yamaguchi, H. Goto ...................................................................................................................
2C.3 Concurrent Technology, Device, and Circuit Development for EEPROMs U. Feldmann, R. Kakoschke, M. Miura-Mattausch, G. Schraud ...................................................
2C.4 TCAD/DA for MPU and ASIC Development Hiroo Masuda, Katsumi Tsuneno, Hisako Sato, Kazutaka Mori ..................................................
2D. 1
Session 2D (Panel & Embedded Tutorial) Coupling of Synthesis and Layout: Challenges and Solutions
Organizer: Jason Cong Moderator: Jason Cong Embedded Tutorial: Logical-Physical Co-design for Deep Submicron Circuits: Challenges and Solutions Massoud Pedram ...........................................................................................................................
Panel Discussion: Panelists: Edward Hsieh, Joe Hutt, George Janac, Takashi Mitsuhashi,
Massoud Pedram, Malgorzata Marek-Sadowska .....................................................
87
93
99
105
111
117
123
129
137
143
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Session 3A DSP System Design
3A. 1
3A.2
3A.3
3B. 1
3B.2
3B.3
3C. 1
3C.2
3c.3
Chair: Georgi Stoyanov Co-chair: Yoshinori Takeuchi A Low Power 2-D DCT Chip Design Using Direct 2-1) Algorithm Liang-Gee Chen, Juing-Eng Jiu, Hao-Chieh Chang, Yung-Pin Lee, Chung- Wei Ku ...................
Low Power Realization of FIR Filters Implemented using Distributed Arithmetic Mahesh Mehendale, Amit Sinha, S. D. Sherlekar .........................................................................
An Efficient Variable-Length Tap FIR Filter Chip Sung Hyun Yoon, Myung H. Sunwoo .............................................................................................
Session 3B System Simulation
Chair: Alec Stanculescu Co-chair: Masahiro Fujita Effective Simulation for the Giga-scale Massively Parallel Supercomputer SR2201 Kaoru Suzuki, Shunsuke Miyamoto, Masato Kurosaki, Junji Nakagoshi ......................................
A Top-down Hardware/Software Co-Simulation Method for Embedded Systems Based Upon a Component Logical Bus Architecture Mitsuhiro Yasuda, Katsuhiko Seo, Hisao Koizumi, Barry Shackleford, Fumio Suzuki .................
A Hardware Software Cosimulation Backplane with .Automatic Interface Generation Wonyong Sung, Soonhoi Ha ..........................................................................................................
Session 3C Asynchronous Logic Synthresis
Chair: Chiu-sing Oliver Choy Co-chair: Yusuke Matsunaga On the CSC Property of Signal Transition Graph Spt:cifications for Asynchronous Circuit Design Mohit Sahni, Takashi Nanya ..........................................................................................................
Practical Synthesis of Speed-Independent Circuits Using Unfoldings Uisok Kim, Dong-Ik Lee ................................................................................................................
Automated Design of Wave Pipelined Multiport Register Files Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura ................
Session 3D (Invited Talks) Design and EDA Road Map
Organizer: Steve Grout Moderators: Greg Ledenbach, Steve Grout Speakers: Steve Schulz, Don Cottrell, Jean Mermet, Tumotsu Hiwatashi ................................
145
151
157
163
169
177
183
191
197
203
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Session 4A Design for Testability
Chair: Kazumi Hatayama Co-chair: Hiroshi Date
Considering Testability during High-level Design Sujit Dey, Anand Raghunathan, Rabindra K. Roy ........................................................................ 205
4A. 1 (Embedded Tutorial)
4A.3 Partial Scan Design Methods Based on Internally Balanced Structure Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara ......................................................................... 21 1
Session 4B Model Checking: Its Basics and Reality
Chair: Kiyoharu Hamaguchi Co-chair: Koichiro Takayama
Model Checking: Its Basics and Reality Masahiro Fujita ............................................................................................................................. 217
4B. 1 (Embedded Tutorial)
Session 4C Pass Transister Logic
Chair: Massoud Pedram Co-chair: Takayasu Sakurai
A Survey for Pass-Transistor Logic Technologies -Recent Researches and Developments and Future Prospects- Kazuo Taki ..................................................................................................................................... 223
4c. 1 (Embedded Tutorial)
4c.3 ALPS: An Automatic Layouter for Pass-Transistor Cell Synthesis Yasuhiko Sasaki, Kunihito Rikino, Kazuo Yano ............................................................................. 227
Session 4D (Panel Discussion) Upcoming Deep Sub Micron EDA Tool Problem
Organizer: Greg Ledenbach Moderator: Greg Ledenbach Panelists: Richard Newton, Steve Schulz, Ray Ambershambi, Kurt Keutzer ............................ 233
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Session SA Towards New EDA Standards
5A. 1
5A.2
5A.3
5A.4S
5ASS
5B.1
5B.2
5B.3
5B.4
5C. 1
5C.2
5c.3
5c.4
Chair: Stanley J. Krolikoski Co-chair: Masatoshi Sekine Software Licensing Models in the EDA Industry Dinesh R. Bettadapur .................................................................................................................... 235
Pre-layout Delay Calculation Specification for CMOS ASIC Libraries Hisakazu Edumatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi ........... 241
CHDStd - A Standard Model for Deep Submicron Design Tools Donald Cottrell, David Mallis, Joseph Morrell ............................................................................ 249
Hierarchy - A CHDStd Tool for the Coming Deep Submicron Complex Design Crisis S. Grout, G. Ledenbach, R. G. Bushroe, R Fishel; D. Cocttrell, D. Mallis, S. DasGupta, J. Morrell, J. Sayah, R. Gupta, PT Patel, R Adams ........................................................................ 257
ATM Cell Modelling using Objective VHDL A. Allara, Massimo Bombana, P Cavulloro, W Nebel, M! Putzke, M. Radetzki ........................... 261
Session 5B High-Level and System-Level Synthesis
Chair: Rajesh Gupta Co-chair: Vasily G. Moshnyaga A High-Level Synthesis System for Digital Signal Processing Based on Enumerating Data-Flow Graphs Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki ..................................... 265
Module Selection Using Manufacturing Information Hiroyuki Tomiyama, Hiroto Yasuura ............................................................................................. 275
Techniques for Functional Test Pattern Execution lnki Hong, Miodrag M . Potkonjak ................................................................................................. 283
Heterogeneous BISR-approach using System Level Synthesis Flexibility lnki Hong, Miodrag M. Potkonjak, Ramesh Kurri ........................................................................ 289
Session 5C Performance Driven Layout
Chair: Yu-Liang Wu Co-chair: Shin'ichi Wakabayashi An Integrated Flow for Technology Remapping and :Placement of Sub-half-micron Circuits Jinan Lou, Amir H. Salek, Mussoud Pedram ................................................................................. 295
Scan-chain Optimization Algorithms for Multiple Scan-paths Susumu Kobayashi, Masato Edahiro, Mikio Kubo ........................................................................ 301
A Clock-Gating Method for Low-Power LSI Design Tukeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kiiniyoshi Usami, Seiichi Nishio, Musami Murakata, Takashi Mitsuhushi ........................................................................................ 307
Power Reduction in Microprocessor Chips by Gated Clock Routing Jaewon Oh, Massoud Pedrum ....................................................................................................... 31 3
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Session 5D (Special Session) University LSI Design Contest
5D. 1 P
5D.2P
5D.3P
5D.4P
5D.5P
5D.6P
5D.7P
5D.8P
5D.9P
5D.
5D.
5D.
5D.
OP
1P
2P
3P
Chair: Akinori Nishihara Co-chair: Chi-ying Tsui TITAC-2: An asynchronous 32-bit microprocessor Akihiro Takumura, Motokazu Ozawa, lzumi Fukasaku, Taro Fujii, Yoichiro Ueizo, Masashi Imai, Masashi Uuwako, Takashi Nanya .......................................................................... 3 19
Power-Pro: Programmable Power Management Architecture Tohru Ishihara, Hiroto Yasuuru ..................................................................................................... 321
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada ......................................................................... 323
Metacore: A Configurable and Instruction Level Extensible DSP Core Jin-Hyuk Yang, Byung- Woon Kim, Sung- Won Seo, Sang-Jun Num, Chang-No Ryu, Jang-Ho Cho, Chong-Min Uyung .................................................................................................. 325
A Design of Sound Synthesis IC Ho Keun Jang ................................................................................................................................ 327
An Effcient 2-D Convolver Chip for Real Time Image Processing Se Young Eun, Myung H. Sunwoo ................................................................................................. 329
FPGA for High-Performance Bit-Serial Pipeline Datapath Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, lmanuddin Amril, Hiroaki Uunieda ............................................................................................................................ 33 1
A New Multiport Memory for High Performance Parallel Processor System with Shared Memory K. Hirano, 7: Ono, H. Kurino, M. Koyanagi ................................................................................. 333
Low Power 50MHz FFT Processor with Cyclic Extension and Shaping Filter M. Bickersta3 T Arivoli, R. J. Ryan, Neil Weste, D. Skellern ...................................................... 335
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip Takashi Midorikawa, Takayuki Uamei, Toshihiro Hanawa, Hideharu A m m o ............................. 337
A CMOS Smart Image Sensor LSI for Focal-Plane Compression Shoji Uawahito, Makoto Yoshida, Masaaki Sasaki, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata, Shiro Doushou, Akira Matsuzawa ......................................................... 339
A +1SV 4MHz Low-Pass Gm-C Filter in CMOS Changsik Yoo, Wonchan Kim ......................................................................................................... 341
Motion Adaptive Image Sensor Takayuki Hamamoto, Kiyoharu Aizawa, Mitsutoshi Hatori ......................................................... 343
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Session 6A Digital PLL & Timing Design
6A. 1
6A. 3
6B.1
6B.2
6B.3
6C. 1
6C.2
6C.3
Chair: Vasily G. Moshnyaga CO-@hair: Graham R. Hellestrand (Embedded Tutorial) Timing Analysis and Optimization: From Devices to Systems Anirudh Devgan, Sandip Kundu .................................................................................................... 345
Dual-loop Digital PLL Design for Adaptive Clock R.ecovery Tae Hun Kim, Beomsup Kim ......................................................................................................... 347
Session 6B HardwareKoftware Codesign I1
Chair: Reiner U! Hartenstein Co-chair: Shinji Kimura High-Level Estimation Techniques for Usage in Hardware/Software Co-Design Jorg Henkel, Rolf Ernst .................................................................................................................. 353
Loop Pipelining in Hardware-Software Partitioning, Jinhwan Jeon, Kiyoung Choi .......................................................................................................... 361
A Performance Maximization Algorithm to Design ,4SIPs under the Constraint of Chip Area Including RAM and ROM Sizes Nguyen-Ngoc Binh, Masaharu Imai, Yoshinori Takeuchli ............................................................. 367
Session 6C Layout Optimization and Veirification
Chair: C. -M. Kyung Co-chair: Takashi Mitsuhashi Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization Jiang-An He, Hideaki Kobayashi .................................................................................................. 373
Hierarchical LVS Based on Hierarchy Rebuilding Wonjong Kim, Hyunchul Shin ........................................................................................................ 379
Curvilinear Detailed Routing Algorithm and Its Extension to Wire-Spreading and Wire-Fattening Toshiyuki Hama, Hiroaki Etoh ...................................................................................................... 385
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6D. 1
6D.2
6D.3
7A. I
7A.2
7A.3
7B. 1
7B.2
7B.3
7c . 1
7c.3
Session 6D (Invited Talk & Embedded Tutorial) Interconnections and Packaging for High Speed and High Frequency
PCB/MCM
Organizer: Akinori Kanasugi Chair: Akinori Kanasugi Tool Capabilities Needed for Designing 100 MHz Interconnects Tim A. Schreyer .............................................................................................................................. 391
Development of a Support Tool for PCB Design with EMC Constraint Yuji Tarui, Takehiro Takahashi, Noboru Schibuya ........................................................................ 397
An Analysis on VLSI Interconnection Considering Skin Effect Tetsuhisa Mido, Kunihiro Asada ................................................................................................... 403
Session 7A High-Performance CMOS Circuits
Chair: Philip C. H. Chan Co-chair: Eiji Masuda Design of Nonlinear Switched-Current Circuits Using Building Block Approach X . Zeng, I? S. Tang, C. K. Tse ........................................................................................................ 409
A High-Performance CMOS Redundant Binary 16 X 16-bit Multiplication Tae-Min Kim, Gun Sun Shin .......................................................................................................... 41 5
A New Design for Double Edge Triggered Flip-flops Massoud Pedram, Qing Wu, Xunwei Wu ....................................................................................... 417
Session 7B Decision Diagrams
Chair: Jawahar Jain Co-chair: Kiyoharu Hamaguchi Space- and Time-Efficient BDD Construction via Working Set Control Bwolen Yang, Yirng-An Chen, Randal E. Bryant, David R. O'Hallaron ....................................... 423
Manipulation of *BMDs Rolf Drechsler; Stefan Horeth ........................................................................................................ 433
Decision Diagrams for Discrete Functions: Classification and Unified Interpretation Radomir S. Stankovic. Tsutomu Sasao .......................................................................................... 439
Session 7C Reconfigurable Systems
Chair: Reiner W Hartenstein Co-chair: Akira Nagoya (Embedded Tutorial) Reconfigurable Systems: A Survey Toshiaki Miyazaki .......................................................................................................................... 447
(Embedded Tu to rial) Reconfigurable Systems: Activities in Asia and South Pacific Hideharu Amano, Yuichiro Shibata ............................................................................................... 453
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Session 7D (Panel Discussion) Asian-Pacific LSI Business in the 21st Century
Moderator: Osamu Karatsu Panelists: Mely Chen Chi, Chong-Min Kyung, Zhong l! Xu, David Skellern,
Takamasa Kishimoto ................................................................................................. 459
Session 8A Testing
Chair: Sunil D. Sherlekar Co-chair: Seiji Kajihara A Redundant Fault Identification Algorithm with Exclusive-OR Circuit Reduction Miyako Tandai, Takao Shinsha ...................................................................................................... 463
8A. 1
8A.2 Interchangeable Boolean Functions and Their Effecls on Redundancy in Logic Circuits Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhauacharya ................................................ 469
8A.3 Real Time Fault Injection Using Logic Emulators Reza Sedaghat-Maman, Erich Barke ............................................................................................ 475
8A.4 Integer Programming Models for Optimization Problems in Test Generation Joao F1 Marques Silva ................................................................................................................... 481
Session 8B Analog CAD
Chair: Hideki Asai Co-chair: Seijiro Moriyama A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling Seiji Funaba, Akihiro Kitagawa, Toshiro Tsukada, Goichi Yokomizo ........................................... 489
8B. 1
8B.2 A Novel Design Assistant for Analog Circuits Markus Wolf; Ulrich Kleine, Frederic Schafer .............................................................................. 495
8B.3 Automatic Test Generation for Linear Analog Circuits under Parameter Variations C.-J. Richard Shi. Michael W Tian ............................................................................................... 501
86.4 The Ensparsed LU Decomposition Method for Large Scale Circuit Transient Analysis Reyi Suda, Yoshio Oyanagi ........................................................................................................... 507 ...
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Session 8C Physical Design for FPGA
Chair: Wayne Wei-Ming Dui Co-chair: Kengo Azegami FPART A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm Rongzheng Zhou, Jiarong Tong, Pushan Tang .............................................................................. 51 3
8C. 1
8C.2 An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays Nozomu Togawu, Kayoko Hagi, Masao Yunagisawa, Tatsuo Ohtsuki .......................................... 519
8C.3 An Architecture-oriented Routing Method for FPGAs Having Rich Hierarchical Routing Resources Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki, Akihiro Tsutsui ....... I .......................... 527
8C.4 On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing Architectures Jiaofeng Pan, Yu-Liang Wu, C. K. Wong ....................................................................................... 535
Session 8D (Panel & Embedded Tutorial) The Next-Generation System Level Design Language
Organiser: Steven E. Schulz Moderator: Steven E. Schulz Panelists: Richard Newton, Grant Martin, Masaharu imai, Greg Peterson, Takahide inoue .. 54 1
Session 9A Analog HDL
Chair: Hidetoshi Onodera Co-chair: Goichi Yokomizo
M~xe~-S igna~ Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities C.4. Richard Shi ............................................................................................................................ 543
9A.I
Session 9B System-Level Power Minimization
Chair: Rob Roy Co-chair: Tetsuya Fujimoto
9B.1 eduction in Pipelines Sri Parameswaran, Hui Guo ......................................................................................................... 545
9B.2 A Hybrid Power Model for RTL Power Estimation Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho ................... 551
9B.3 cient Systems-on-Silicon Darko Kirovski, Chunho Lee, Miodrug Potkonjak, William Mangione-Smith ..................... ......... 557
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Session 9C Floorplannning
Chair: Massoud Pedram Co-chair: Ikuo Harada Air-Pressure-Model-Based Fast Algorithms for General Floorplan 9c. 1 Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani ........................................................................ 563
9C.2 Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani .................................................................. 57 1
9c.3 A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout Tetsushi Koide, Shin 'ichi Wakabayashi .......................................................................................... 577
Session 9D (Invited Talks) LSI Designs in Multimedia1 Era
Chair: Hiroaki Kunieda
9D. 1 VLSI for Multimedia U-NI1 WLANs Neil Weste, David Skellern, 7: Percival ......................................................................................... 585
9D.2 Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing Takao Onoye, Gen Fujita, Hiroyuki Okuhata, Morgan H. Miki, Isao Shirakawa ......................... 589
9D.3 CMOS Image Sensors with Video Compression Shoji Kawahito, Yoshiaki Tadokoro, Akira Matsuzawa ................................................................. 595
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