Architecture optimization and design verification of the Timepix3 and the

Velopix pixel ASICs

14.11.2013Tuomas Poikela (TUCS/CERN)

SV/UVM Mini workshop

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Outline Introduction (Pixel chip & TLM)

Architecture optimizationTransaction level model (TLM)Integration with verification environment

Design verificationReusing modeling frameworkTestbench architectureAssertions

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Introduction

Techniques presented here used in two pixel ASIC projects: Timepix3 and Velopix

256x256 pixel ASICs with 55um x 55um pitch, designed using 130nm CMOS

Timepix3 has been manufactured and tested to work (characterization not fully done yet)

Velopix is still a work in progress, but the design is very well advanced

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Pixel readout chip interfaces

Slowcontrol

Input interface(sensor/discriminators)

Pixel matrix(active area)

Dataoutputs

TFC (reset, sync, etc.)

Periphery

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TLM notation

Get-interface

Put-interfaceBit-levelinterface

Analysis-interface

Components(agents,scoreboards,BFMs…)

Initiator port

Target port/export

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ARCHITECTURE OPTIMIZATION

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Testbench for optimization

Inputagent

Pixel ASICTLM DUT

(ovm_component)

Output agent

TLM Scoreboard

Test class (ovm_test)

Sequencelibrary

Configurationobject

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Discriminatorinterface

Output data interface

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Pixel ASIC TLMPixel ASIC TLM DUT (ovm_component)

Virtualrouter

Column 0

Column1

Column N

Periphery

Bus

Arbiter

Not all TLM ports/components shown inside the periphery.

FIFO

FIFO

FIFO

Out

put b

lock

Each portspecializedfor packettransaction

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All componentsmodelled as ovm_components.

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Transaction definition

Each TLM port in TLM model specialized with TPX2PacketTransaction

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TLM Framework

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Sequence & test library Component library

Arbiter base

TokenArbiter

ColumnBase

SuperPixelColumn

PixelColumn

PeripheryBase

EoCBase

EoCArbitrated

ColumnBus

PeripheryBus

ChipBase

Chip0 Chip1

extends

BaseSeq class TestBase;ChipBase chip;BaseSeq seq;

RandomSeq

MonteCarloSeq

Class Test0extends TestBase;

Class Test1extends TestBase;

set_type_override( ChipBase, Chip0)

set_type_override( ChipBase, Chip1)

set_type_override( BaseSeq, RandomSeq)

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Different modeling approach (non-TLM/OVM)

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class TopLevelSim;

Pixel Matrix

Periphery

module TopLevel_tb;

Packet creatorMonte Carlo data

ConstrainedRandomData generator

(Ideally one objectat top-level)

PacketPool

Scoreboard

Result extraction

TopLevelSim simulation = new;initial simulation.run();

Chip modelList of packets

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Simulation main loop

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Completely untimedstyle Can use C++ as well Seems to be 4-8 x fasterthan TLM model

Can add timingby using #25ns;No performance loss.

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DESIGN VERIFICATION

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RTL Verification Environment

Inputagent

Pixel Trans-actor

Output agentSl

owCo

ntro

lAg

ent

TFC

Agem

t

RTL Scoreboard (hierarchical)

Configuration

registers

Registerupdater

OutputTrans-actor

Pixel ASIC RTL DUT

Converter

Test class (ovm_test) Configuration

VirtualSequencer

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Test base class

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Test base class

Actual, derived test

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Scoreboard block diagram

RTL Scoreboard (hierarchical)

Datapath scoreboard

Packetgenerator

WriteImplem.

Control packetscoreboard

Slow control ScoreboardConfigura

tion registers

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Black box view

White box view

ErrorDB PacketDB Checker

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Configuration registers

Created in test class Passed to components

inside a config object Each register is an ovm_object, has a coverage model

Only handful of registers but > 800 LOCs of SV (excluding drivers, macros etc.)

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Configuration registers,ovm_object

Pixels

PLL

General Outputblock

Test pulse

Power pulsingAnalog

config

Register package

+ register typedefsTypedef struct {……} PixelReg_t;

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Assertions – using macros

Source: C. E. Cummings. SystemVerilog Assertions Design Tricks and SVA Bind Files. 2009.14.11.2013

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Assertions cont’d

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No error. Datastable 1 clock beforeand after.

ERROR. Data changed1 clock before req.

ERROR. Data changed 1 clockafter req.

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Scripting flowTest library +verif. environment

Top-levelmodules

IUS simulation scripts-one per module

IUS compilationscripts

SystemVerilogcode

Simulator

Shell

PERL script

Test list 0

Test list N

regress.pl

work_dir0

work_dir1

work_dirN

./regress.pl-f ius_script.f-t test_list_N.t

Sequencelibrary

Coverage

Master log file

Run 0 log file

Run N log file

Simulations logs

Results14.11.2013

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Concluding remarks

Few use cases of SV + OVM have been presentedModeling of a pixel chipRTL verification: Testbench structure using OVM

Plan is to move to UVM for Velopix (and maybe change the high-level model from TLM/OVM to pure SV)

Use assertions!

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THANK YOU FOR THE ATTENTION!

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