architecture for smart grid based consumer end solution
TRANSCRIPT
Generation
Transmission and Distribution
Consumers
- To design low profile, versatile nodes capable of communication between the system designer and the appliances.
Problem Definition
- To design a generic entity to play administrator over a group of control nodes.
- To make available the desired data at the administrator node, and to maintain a database for the specified duration.
- We call the control nodes as “SLAVES”, and the administrator nodes as “POWER HUB”.
- The POWER HUB listens to the system designer, and implements the required control over the network through SLAVES.
- To design a low profile, versatile nodes to communicate between the system designer and the appliances.
Problem Definition
- To design a generic entity to play administrator over a group of control nodes.
- To make available the desired data at the administrator node, and to maintain a database for the specified duration.
- We call the control nodes as “SLAVES”, and the administrator nodes as “POWER HUB”.
- The POWER HUB listens to the system designer, and implements the required control over the network through SLAVES.
Power Hub
Slaves
Power Lines
Power Hub
Slaves
Power Lines
Architecture Overview
Power Hub
Slave
Architecture Overview
Power Hub
Slave
User Interface
Network Interface
CardEthernet Interface
Power Line Modem
Display Control Panel
Interface Controller
Database Manager
Intelligent Kernel
AdministratorInterface
Com
man
d In
terfa
ce
Legend: - Power Lines - 10/100 Ethernet Interface
Architecture - Power Hub
User Interface
Network Interface
CardEthernet Interface
Power Line Modem
Display Control Panel
Interface Controller
Database Manager
Intelligent Kernel
AdministratorInterface
Com
man
d In
terfa
ce
Legend: - Power Lines - 10/100 Ethernet Interface
Architecture - Power Hub
User Interface
Network Interface
CardEthernet Interface
Power Line Modem
Display Control Panel
Interface Controller
Database Manager
Intelligent Kernel
AdministratorInterface
Com
man
d In
terfa
ce
Legend: - Power Lines - 10/100 Ethernet Interface
Architecture - Power Hub
Architecture Overview
Power Hub
Slave
Architecture Overview
Slave
Metrology Sensors
Real Time Clock
Segment LCDDisplay
Power Line Modem
ADC Switching Control
Control, Logic,
Display & Keypad Control
Keypad, User Interface
SwitchAppliance
UART
RTCFP
GA
Prio
rity
Cont
rol
Architecture - Slave
Metrology Sensors
Real Time Clock
Segment LCDDisplay
Power Line Modem
ADC Switching Control
Control, Logic,
Display & Keypad Control
Keypad, User Interface
SwitchAppliance
UART
RTCFP
GA
Prio
rity
Cont
rol
Architecture - Slave
Metrology Sensors
Real Time Clock
Segment LCDDisplay
Power Line Modem
ADC Switching Control
Control, Logic,
Display & Keypad Control
Keypad, User Interface
SwitchAppliance
UART
RTCFP
GA
Prio
rity
Cont
rol
Architecture - Slave
Metrology Sensors
Real Time Clock
Segment LCDDisplay
Power Line Modem
ADC Switching Control
Control, Logic,
Display & Keypad Control
Keypad, User Interface
SwitchAppliance
UART
RTCFP
GA
Prio
rity
Cont
rol
Architecture - Slave
Metrology Sensors
Real Time Clock
Segment LCDDisplay
Power Line Modem
ADC Switching Control
Control, Logic,
Display & Keypad Control
Keypad, User Interface
SwitchAppliance
UART
RTCFP
GA
Prio
rity
Cont
rol
Architecture - Slave
Metrology Sensors
Real Time Clock
Segment LCDDisplay
Power Line Modem
ADC Switching Control
Control, Logic,
Display & Keypad Control
Keypad, User Interface
SwitchAppliance
UART
RTCFP
GA
Prio
rity
Cont
rol
Architecture - Slave
Metrology Sensors
Real Time Clock
Segment LCDDisplay
Power Line Modem
ADC Switching Control
Control, Logic,
Display & Keypad Control
Keypad, User Interface
SwitchAppliance
UART
RTCFP
GA
Prio
rity
Cont
rol
Architecture - Slave
Communication Schema
Communication Schema
ADDSLOT
8MARKER
Hub
Communication SchemaHub feeds the MARKER on network
ADDSLOT
8MARKER
Hub
PREFIX
then, it feeds PREFIX on the network
Hub
These basic elements are sent on the network, even when there is no SLAVE connected
ADDSLOTPREFIX
8MARKER
Hub
Slave 1
SLAV
E 1
When a SLAVE is introduced in the network, it searches for MARKER, and catches the PREFIX that follows.
PREFIX
8
ADD
SLOT
MAR
KER
Hub
Slave 1SLAVE 1
The SLAVE registers itself into the network, by sending its unique address to HUB during this slot.
SLAVE 1
PREFIX
8M
ARKE
R
Hub
Slave 1
The HUB registers the new SLAVE into the network, when it receives an address during this slot.
MARKER
SLAVE 1 TO HUBHUB TO SLAVE 1
SLAVE 1
ADD SLOT
PREFIX
Hub
SLAVE 1
When a SLAVE is successfully registered in the network, the HUB assigns it an address slot – SLAVE 1.
The HUB and SLAVE are now connected, and communication can take place.
SLAVE 1
HubMSG
SLAVE 1
Hub
MSG
SLAVE 1
HubM
SG
MSG
SLAVE 1
Hub
MSG
SLAVE 1
Hub
MSG
Applications
Applications
- Smart Grid Technologies.
Applications
- Other Applications.
- Smart Grid Technologies.
Applications
- Other Applications.
- Device Management.- Prepaid Power.- Energy Market Transaction.
- Breakdown Management.- Power Factor Correction- Data Acquisition systems
Current Status
Current Status
- The design of Power Line modem and SLAVE as mentioned in the proposed architecture has been completed with appreciable results.
Current Status
- Pspice simulation models of the Oscillator, BPSK modulator & demodulator, and the notch filter have been displayed in the mentioned order.
Current Status - Oscillator• 1.02 MHz Oscillator to transmit Pilot Carrier on network.
Current Status - BPSK Modulator• The carrier is phase shifted by 180⁰ for level shifts of Data.
Current Status - BPSK DemodulatorDemodulated Data
Original Data• XOR operation based demodulator
Current Status - Notch Filter• Twin – Tee Symmetrical Notch Filter with notch at 50Hz.
THANK YOU
Oscillator I
Oscillator II
Switching Network Modulated Output
Modulator
Schematics – Oscillator I
Schematics – Oscillator II
Schematics – Switching Network
Amplifier Amplifier Amplifier
XOR
Clipper
Amplifier
Amplifier Amplifier AmplifierClipper
Output Data
Input Data – 10 MHz
Carrier Input– 1 MHz
Stage IIStage I
Output Stage
Front End
Demodulator
Schematics – Amplifier
Schematics – Buffer
Schematics – Clipper
Schematics – XOR