application note msan-131 - microsemi

A-149

Table of Contents

• 1.0 Introduction

• 2.0 MT8960-67 Voice Codec GeneralApplication Information

• 3.0 MT8960-67 Functional Descriptionand Application Details

3.1 Channel Timeslot Assignment3.2 Switching and Control Using the

MT8980 Digital Crosspoint Switch

• 4.0 Subscriber Line Interface CircuitApplications

• 5.0 MH88610 Application Details

5.1 Battery Feed5.2 Off-Hook Detection and Dial Pulse

Signalling5.3 Application of Ringing and Automatic

Ring Trip Implementation5.4 Transmit and Receive Signal Levels

• 6.0 Consideration of Loss and LevelPlans in SLIC Design

• 7.0 Line Card Power Supply Filteringand Codec Circuit Protection

• 8.0 Line Card Layout Guidelines

• 9.0 Conclusions

• 10.0 References

1.0 Introduction

In digital telephone switching systems, the two wireanalog loops interface to the switch through aSubscriber Line Interface Circuit (SLIC). The basicfunctions of the SLIC are frequently summarizedusing the acronym BORSCHT - which stands forBattery, Overvoltage, Ringing, Signalling, Coding,Hybrid and Test. Zarlink’s MH88610 Subscriber LineInterface Circuit (SLIC) and the MT8960-67 series ofVoice Codecs can be used together to implementthese functions.

The MT8960-67 series of Voice Codecs integrate allthe functionality necessary to encode analog signalsin the voice band into a digital format using PulseCode Modulation (PCM). The encoded signal can bereadily handled by digital time-space crosspointswitches and digital transmission interfaces. Thecodecs also perform the converse function ofdecoding PCM back into an analog format. TheMH88610 is a thick film hybrid circuit which can beused to implement the remaining BORSCHTfunctions mentioned previously.

This application note provides details on how theZarlink MT8960-67 series of Voice Codecs can beused in conjunction with the MH88610 to implementa complete subscriber line interface for a digital PBX.A general discussion on loss and level plans hasbeen included to highlight how some of the featuresincorporated in the codecs facilitate design ofswitching systems. Guidelines on low noise line carddesign and codec protection have also beenpresented.

2.0 MT8960-67 Voice Codec GeneralApplication Information

The MT8960-67 (MT896X) series of voice codecsintegrate all the functions necessary to convertanalog voice signals to PCM and PCM back toanalog. The devices meet CCITT and AT&T codecstandards for primary rate interface. The MT8960-67series of codecs are optimized for use in line cardtype applications and therefore incorporate severalfeatures not generally seen in other devices withsimilar functionality including software program-mable gain pads, uncommitted drive outputs and anumber of loopback and test modes.

ISSUE 3 June 1995

MSAN-131Subscriber Line Interface for

Digital Switching Systems

Application Note

MSAN-131 Application Note

A-150

Table 1. Voice Codec Variants Manufactured by Zarlink* Alternate Digit Inversion

Device Type Part Number Number of SD Outputs Code

A-LawDevices

MT8961MT8963MT8965MT8967

4646

True Sign/True Mag.True Sign/True Mag.

ADI*ADI*

µ-LawDevices

MT8960MT8962MT8964MT8966

4646

True Sign/True Mag.True Sign/True Mag.True Sign/Inv. Mag.True Sign/Inv. Mag.

The basic differences in the codec variants aredescribed in Table 1. The even numbered devices -MT8960, MT8962, MT8964 and MT8966 all use theµ-companding law. The MT8960 and MT8962conform to the sign and true magnitude data format.The MT8964 and MT8966 conform to the sign andinverted magnitude format. In the latter, the sevenmagnitude bits are inverted. To ensure a higher onesdensity, AT&T requires the line code output by aninterface on to a T1 line to conform to the sign andinverted magnitude format. However, thisrequirement does not necessarily restrict the user tothe MT8964 and MT8966 because most T1interfaces perform the inversion of the data bitsbefore the signal is transmitted on the line side.Zarlink’s MT8976 T1 interface device offers a userselectable option to enable or disable inversion of themagnitude bits. Therefore any of the µ-law codecscan be used with it.

The odd numbered devices - MT8961, MT8963,MT8965 and MT8967 use the A-companding law.

The MT8961 and MT8963 conform to sign and truemagnitude data format. The MT8965 and theMT8967 generate a code in which the evennumbered bits of the octet are inverted (AlternateDigit Inversion) - a requirement specified by CCITTfor PCM code transmitted on the primary multiplexline. Zarlink's European primary rate interface devices,the MT8978 and MT8979, provide user selectableoptions which permits either type of codec to beused.

The MT8960, MT8964, MT8961 and the MT8965have only four uncommitted drive outputs, while theMT8962, MT8966, MT8963 and the MT8967 have sixsuch outputs.

3.0 MT8960-67 Functional Descriptionand Application Details

A detailed codec functional and pin description isavailable in the MT8960-67 data sheet. A brief

Figure 1 - MT896X Functional Block Diagram

ANUL

VX

SD0

SD1

SD2

SD3

SD4

SD5

VR

VRef GNDA GNDD VDD VEE

DSTo

CSTiCA

F1i

C2i

DSTi

TransmitFilter

OutputRegister

ReceiveFilter

Analog toDigital PCM

Encoder

PCM Digitalto AnalogDecoder

OutputRegister

InputRegister

A Register8-Bits

B-Register8-Bits

ControlLogic

Application Note MSAN-131

A-151

summary is presented below to highlight some of thefeatures of the device as they pertain to digitalcontrol and data I/O.

The analog signal input to the device at the Vx pin(see Figure 1) is filtered using switched capacitorfilters. It is sampled by the analog to digital converterwhich generates the appropriate PCM byte accord-ing to the applicable encoding law (µ-law or A-law).The 8 bit digital byte is held in a serial register. It isclocked out at DSTo with the 2.048 MHz signalapplied at C2i when the digital interface is enabledby asserting the appropriate level on F1i and CA.The PCM byte from the far end is also clocked intothe device through the DSTi input at this time. Thedevice performs the D/A conversation and makesavailable the filtered analog signal on VR. The codecuses the signal applied at C2i for all internal timingand clocking of switched capacitor filters. In order forthe device to meet the stringent CCITT and AT&Tstandards, the frequency of the C2i clock should beaccurate to within ± 0.1%.

As mentioned earlier in the introduction, theMT8960-67 series of voice codecs have a number ofextra features which facilitate line card design.Features such as gain control, activation/deactivation of uncommitted drive outputs, loopbackand test modes, and, the powerdown mode are allaccessed through the serial control input pin CSTi.

This pin accepts data in a serial format for twointernal registers, A and B.

The A register is loaded when F1i and CA are bothlow (GND). When F1i is low (GND) and CA is high(+5V), register B is loaded. The A register controlsthe gain pads, loopback modes and the powerdownfunction. The B register controls the state of theexternal uncommitted drive points (SD0-SD5) andthe various test modes. Note that the data input atCSTi must be continually made available to thedevice once per frame. This is illustrated in thetiming diagram shown in Fig. 2. It is possible to usethe codecs in a default mode. If CA is tied to -5V andCSTi is tied to ground, the encoder and decoder willfunction normally. However the gain pads will be setto the default state of 0dB, the uncommitted controloutputs will all be disabled, and the various testmodes will not be accessible. In the second defaultmode, CA is tied to GND and serial data clocked intoCSTi may be used to control the receive and transmitgain by loading the A register.

3.1 Channel Timeslot Assignment

The F1i and CA inputs are used to assign a device toa specific 8 bit channel within a time divisionmultiplexed serial stream such as the ST-BUS. TheST-BUS is a time division multiplexed serial bus witha bit rate of 2048 kbit/s. In a telecommunications

Figure 2 - MT896X Timing Diagram - 125 µs Frame Period

HIGH IMPEDANCE

Load A Register Load B Register

C2iINPUT

F1i

CA

DSToOUTPUT

DSTiINPUT

CSTiINPUT

5V

0V

125µs

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 7 6

7 6

7


A-152

environment, the serial stream is divided into thirtytwo 8 bit channels. Each channel has a bandwidth of64 kbit/s. The voice codec uses one ST-BUS channelfor PCM data and two channels for control. Thedigital word is clocked out (most significant bit first)with the first rising edge of C2i after F1i is taken low.When F1i is high, the device does not accept anyinput at the DSTi or CSTi pin and the DSTo outputgoes into a high impedance state.

The timing relationship of the C2i clock signal withrespect to the input and output digital word and F1i isillustrated in Figure 2. The F1i set-up time of 50nsand hold time of 25ns with respect to the risingedge of C2i must be adhered to in order for thedevice to operate properly (see MT8960-67 datasheet for more information). The MT896X isenabled on the first rising edge. F1i mustsubsequently be taken high after eight periods ofC2i, as shown in Figure 2.

The timeslot assignment circuit shown in Figure 3generates the Framing type 1 (F1o) and the ControlAddress (CA) signal in a manner which allows thecodec to be assigned to any one of 32 channels. TheF1oX (where X = 0, 1, 2,... 31) output from the

circuit is connected to a codec’s F1i input. The CAoutput from the circuit is connected to the CA inputon the first 16 codecs.

The codec connected to F1o0 will be enabled duringtimeslot 0 on the ST-BUS serial stream. Similarly acodec connected to F1o1 will be enabled duringchannel 1. For codec 0, the F1i and CA signals areboth low during timeslot zero. During channel 16,only F1i is taken low. CA is kept high. Thus registerA will be loaded during timeslot zero and register Bwill be loaded during timeslot 16. The CA inputs onthe first 16 codecs are connected directly to the CAoutput of the timeslot assignment circuit. The CAinputs of the next 16 are connected to an invertedCA. Thus codec number 16 will accept its PCM inputand load the A register during timeslot 16 when bothCA and F1i are low. The B register will be loadedduring timeslot 0 when CA is high and F1i is low.

Figure 3 - Timeslot Assignment Circuit for Voice Codecs

C2

F02

13

12

+5V

14

VCC1A

1CLR

2A

2CLR

1QA1QB1QC1QD2QA2QB2QC2QD

GND

7

3456111098

+5v

16

123

645

ABC

G1G2A

G2B

Y0Y1Y2Y3

Y4Y5Y6Y7

F1o0F1o1F1o2F1o3

F1o4F1o5F1o6F1o7

F1o8F1o9F1o10F1o11

F1o12F1o13F1o14F1o15

CA

CA

1

15141312

111097

8

GND

+5v

16

123

645

ABC

G1G2A

G2B

Y0Y1Y2Y3

Y4Y5Y6Y7

15141312

111097

8

GND

138

138

393

VCC

VCC


A-153

3.2 Switching and Control Using the MT8980Digital Crosspoint Switch

Zarlink's ST-BUS devices are designed to complementeach other in terms of functionality and ease ofinterface. The MT8980 digital crosspoint switch canbe used both for switching and control function. Ithas eight serial input ports and eight serial outputports. Each of these I/O ports support a 32 channelST-BUS stream. Any channel on the ST-BUS inputscan be switched to any output channel timeslot. Anoutput channel can also be programmed to sourcedata from internal memory. This mode, referred to asmessage mode, can be used for controllingperipheral devices. In message mode, the 8 bitscorresponding to the specific memory location in theconnection memory are transmitted out during theappropriate timeslot on the ST-BUS stream. Aperipheral device such as a codec connected to thisstream and assigned this specific channel timeslot,will accept the byte. In this manner the controlregisters of the various devices are effectivelymapped into memory locations in the MT8980. Themicroprocessor interfaced to the MT8980 writes theappropriate word to the connection memorycorresponding to the selected output channel. Thecontents of the memory are continually output, onceper frame, until the MPU changes the mode ofoperation. This feature can be used to control theMT896X codecs by placing the appropriate channelson the ST-BUS stream connecting the MT8980digital switch to the CSTi inputs of the MT896Xs inmessage mode (refer to the MT8980 data sheet andMSAN-123 Application Note “The MT8980 andMT8981 Digital Crosspoint Switches” for moredetails).

A simplified configuration of a switching systemusing the MT8980 and the voice codecs is illustratedin Figure 4. The MT8980 provides both the switchingand control function.

The configuration illustrated in Figure 4 shows only32 codecs. The MT8980 has the capability to support256 voice channels. In applications utilizing the fullcapability of the codec, three ST-BUS channels perdevice are required. One for the PCM data and twofor controlling the device via the A and B registers.Therefore to support 256 codecs fully for switchingand control, three MT8980s would be required.However, as mentioned earlier, the MT896X series ofvoice codecs can be operated in a default modewhereby only the encoding and decoding function isutilized. The A and B registers are not loaded. In thiscase, only one MT8980 would be required to functionin a switching capacity for 256 voice codecs.

The ST-BUS I/O streams chosen for illustration inFigure 4 were selected arbitrarily. The STi0 inputstream on the MT8980 accepts PCM data from thecodecs for switching. The output stream STo0transmits PCM data to the codecs. All 32 codecsshare a single input stream and a single outputstream. STo1 and STo2 are used for controlling thedevices. The timeslot assignment circuit providesthe F1i and CA signals which enable theappropriate codec at a specific time during which itaccepts data from the TDM stream. For example, theF1i and CA signals input to codec #0 go low duringchannel timeslot 0. This codec will clock in PCM dataoriginating from the MT8980 STo0 during thistimeslot. The device will also clock out PCM data fortransmission to the MT8980 over the STi0 at thistime. Each codec requires two ST-BUS channels forcontrol. Since each ST-BUS stream is capable ofsupporting only 32 channels, only 16 codecs can behandled by each stream. In the configurationillustrated in Figure 4, CSTi inputs of the first 16codecs are connected to STo1, while the remaining16 are connected to STo2. Also note that the firstsixteen devices (0 to 15) receive CA from thetimeslot assignment circuit where as the last 16receive CA. Thus codec number 16 will accept PCMinput and data for register A during timeslot 16.Register B will be loaded during timeslot "0" viaCSTi. As an example, in Figure 4, codec # 0 has itsCSTi pin connected to STo1. This codec has alsobeen assigned channel 0 for its A register andchannel 16 for its B register. In the MT8980,channels 0 and 16 on this stream are put in"message mode”. The appropriate control bytedesired for the A register is placed in the Connectionmemory location corresponding to channel 0, outputstream 1 (STo1). The control byte for the B register iswritten into the connection memory lowcorresponding to channel 16, stream 0. The controlbytes are accepted by this codec during channeltimeslot 0 and 16. The timeslot assignment circuitgenerates the F1 signal and the CA signal.

Note that if the channel assignment circuit illustratedin Figure 3 is used, the voice codec expects the Aand B registers to be updated once per frame.

The MPU interface to the MT8980 can place thecodecs into the different modes and control externaldevices or circuits connected to the SD outputs. Thetransmit and receive gains of each codec can becontrolled digitally through the A register.

Supervisory information originating from the linecard, such as an off-hook indication, can bemultiplexed onto a ST-BUS channel using the circuitillustrated in Figure 5. The circuit can be assigned anST-BUS channel using the timeslot assignment


A-154

Figure 4 - Simplified Switching System Architecture

ST-BUSCONTROL STREAM

DATA STREAM

DIGITALCROSSPOINT

SWITCHMT8980

MPUSTi0

STo0STo1STo2

F0iF0iC4i4.096 MHz

2.048

-5V

CSTiDSTiC2iDSToVDDF1iCASD3SD2

GNDDVREFGNDA

VRANUL

VXVEESD0SD1

GND2.5V

-5V

LINELine

Interface

FROM TIMESLOTASSIGNMENT CIRCUIT

CODEC #1MT896X

CODEC #15MT896X

CODEC #16MT896X

CODEC #31MT896X

CSTiDSTiDSTo

CSTiDSTiDSTo

CSTiDSTiDSTo

CSTiDSTiDSTo

TIMESLOT ASSIGNMENTCIRCUIT (see Fig. 3)

To # 0 & 16To # 1 & 17To # 2 & 18

To # 15 & 31

To # 0 to 15To # 16 to 31

F1o0F1o1F1o2

F1o15

••••

CACA

C2i

F0i

CODEC #0MT896X


A-155

circuit shown in Figure 3. The status from eightinterfaces can be multiplexed on to a single ST-BUSchannel and transmitted to the MT8980. The MPUinterfaced to the MT8980 can monitor this channel byreading the appropriate "Data Memory" location inthe MT8980. When an off-hook condition on any ofthe lines occurs, the appropriate bit in the receivedchannel is set (or reset as the case may be). This isdetected by the mpu which then takes appropriateaction i.e. connects an incoming call to thesubscriber or conversely, if the subscriber isrequesting service, connects a dial tone source to it.

This type of serial control and switching busarchitecture minimizes PCB tracking density andbackplane wiring. This in turn permits more lineinterfaces to be supported per card. Consequentlythe overall size of the system can be reduced. Thelower power consumption and reduced physical sizerequirements can offer an important marketingadvantage. The physical wiring and driverequirements of a parallel bus for similar contolcapability adds extra cost penalties which are notoffset by advantages inherent in the simpler parallelbus architecture.

4.0 Subscriber Line Interface CircuitApplications

Voice codecs are four wire devices, i.e., the encodedvoice is transmitted and received on different paths.Connection of a codec to the balanced analog two

wire subscriber loops requires a 2 to 4 wire convertercircuit referred to as a "Hybrid". The hybrid functionis an integral part of the Subscriber Line InterfaceCircuit. The Subscriber Line Interface Circuit (SLIC)also provides battery feed for operation of thesubscriber telephone. It asserts ringing voltage onthe loop to alert the subscriber of an incoming call,and, detects when the subscriber set goes off-hook.The hybrid and battery feed function has traditionallybeen performed using transformers. However, withthe continuing trend in the industry towards smallerand more compact systems, transformerless SLICsare rapidly becoming more common. Trans-formerless SLIC’s have size advantages and can bedesigned with switchable options to permit use of thesame line card in different applications.

The basic principle of operation of a hybrid isillustrated schematically in Fig. 6. If the impedancereflected to the primary side of the transformerequals ZB, then the transmit signal component willbe cancelled from the composite signal on thereceive output - thus isolating the receiver from thetransmitter. In order to maximize the cancellation, ZBshould be matched to ZL (the two wire loopimpedance) as closely as possible. In the practicalloop environment, there is significant variability inlength and wire size. Matching impedance on a lineto line basis is not practical. In PBX applications twostandard balance networks are chosen - one forshort loops (generally 600 ohms) and a second forlong loops (350 ohms in series with Ik ohm shuntedwith 0.21 µF). The degree of cancellation for a

Figure 5 - Multiplexing Status Information from 8 Scan Points on to a ST-BUS Channel

F1i

CA

C2i

CSTo

Scan Points

74LS166

74LS74

74LS04

74LS74

1 2

+5

12

3

4

5

6

DCLR

Q

PRQ

DCLR

Q

PRQ

+5

13

12

11

10

8

+5+5

159

7

133

1

2

6

74LS126

A

B

C

D

E

F

G

H

2

3

4

5

10

11

12

14

CL S/L

Cl

Q H


A-156

Figure 6 - Operation of Hybrid Circuit in a SLIC

Transmit

Receive

ZS = Source ImpedanceZB = Balance ImpedanceZL = 2 Wire Loop Impedance

VTX

ZS

ZB

ZS

ZL

_ ++Tip

Ring

Transhybrid Loss = 20 logVTXVRX

= 20 log(ZL + ZS) (ZB + ZS)

ZS ZB - ZSZL

1 : 1

VRX

particular line interface circuit is specified as theTranshybrid loss. SLIC’s can be designed so that thebalance network is selected using an externallyaccessible node in the hybrid circuit. By tying thisnode to ground or permitting it to float, effectivelymodifies the balance impedance. The SD outputs onthe Zarlink codecs may be used to switch the node toground or leave it floating. For example, the outputsSD3 to SD5 are open drain outputs which are pulledto ground when the appropriate bit in ControlRegister B is set. Therefore, if the external nodewhich selects the balance network in the hybrid istied to one of these drive points, the correct balancenetwork could be selected by merely writing to thecodec's control register. This would allow theswitching system to be reconfigured for different looptypes through software control at time of installationor when changing requirements make it necessary.Other filters and gain pads may also be switched inor out of the circuit to suit specific applications in asimilar manner.

5.0 MH88610 Application Details

The Zarlink MH88610 is a Subscriber Line InterfaceCircuit (SLIC) designed specifically for on-premiseapplications. The application circuit shown in Figure7 shows how the MT896X codecs can be used withthis device to interface to a two wire subscriber loop.

The MH88610 provides an interface between the twowire subscriber loop and the four wire codec. It doesall of the SLIC functions described in the precedingsection.

5.1 Battery Feed

The MH88610 provides the loop with constant DCcurrent to power the telephone set. The voltageapplied at the VRef pin determines the actualmagnitude of the loop current.

ILoop = VRef /0.423 mA (± 2 mA)

where VRef is in volts and is negative with respectto ground.

For typical applications, the DC subscriber loopcurrent required is 26mA. This requires VRef to be-11V which can be generated from the 2.5Vreference used by the voice codec (see Fig. 7). Theloop is connected to the Tip and Ring pins on thehybrid. Varistors RV1 and RV2 provide primaryprotection against overvoltage to the MH88610.Diodes D1, D2, D3 and D4 provide secondaryprotection.


A-157

Fig

ure

7 -

Inte

rfac

ing

the

MT

896X

to

the

MH

8861

0

-28V

D1

D2

RV

1

RV

2

To

Tel

epho

neS

et

-28V

D3

D4

K1

R2

RIN

GIN

GS

OU

RC

E

1 9 10 15 R1

11 18-2

8V

C1

MH

8861

0

TF

Tip

Rin

g

RV

RF

VB

at

VX

VR

CA

P

SH

K

Loop

VR

ef

VD

D

GN

DA

VE

E

8 3 19 D5

20 7N

C4

C3

12 6 5

C2

C4

C8

R6

+12

V K1

-5V

R5

R4

R3

Q1

2.5V

Fro

mA

D14

03A

C7

+5V

-5V

MT

896X

VX

VR

SD

3

SD

0

VR

ef

CS

Ti

DS

To

DS

Ti

CA

VD

D

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GN

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F1i

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ec2.

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uits

CO

MP

ON

EN

TS

LIS

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R1

=w

, 5%

, 30.

0 k

R2

=w

, 5%

, 750

k

R3

=w

, 5%

, 3.9

k

R4

=w

, 5%

, 4.7

k

R5

=w

, 5%

, 43

k

R6

=w

, 5%

, 470

k

R7

=w

, 5%

, 43.

2 k

R8

=w

, 5%

, 9.7

6 k

1 4 1 41 4 1 4 1 41 4 1 41 4

AR

I = M

C14

58 O

p-A

mp

*RV

1, R

V2

= V

ar. 1

60 V

RM

S, 2

50V

, 10J

*D1,

D2,

D3,

D4

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iode

, 200

V, 1

A, I

N40

03

D5

= D

iode

, 75V

, 0.2

A, 0

.5W

, IN

4148

Q1

= N

PN

, 2N

2222

K1

= R

elay

E/M

, 12V

, 1 F

orm

C

C1,

C2,

C3,

C4,

C5,

C6,

C7

= C

er. 0

.1µF

, 50V

, 20%

C8

= E

lec.

1.0

µF, 1

6V, 1

0%

*Not

e: C

ompo

nent

s w

ith a

n as

teris

k ar

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ing


A-158

5.2 Off-Hook Detection and Dial PulseSignalling

When a subscriber set goes off-hook, the local loopis closed and a DC current flows. The MH88610monitors the loop current flow and indicates an off-hook condition when a specific threshold has beenexceeded. The current flow is a function of the loopimpedance. An off-hook will be detected by theMH88610 when the loop impedance falls below1200 ohms. The SHK output on the MH88610 canbe monitored by the system processor to detectwhen the subscriber set goes off hook.

Dial pulses are generated by the subscriber set byopening and closing the loop and therefore can bedetected on the SHK output. The processormonitoring the output would have to time and countthe pulses.

5.3 Application of Ringing and Automatic RingTrip Implementation

Ringing is applied to the line by disconnecting RFfrom RV and connecting a ringing generator to theRF pin. Relay K1 is activated by the SD0 pin on theMT896X. Resistor R1 serves to provide battery feedto the subscriber loop during the transitionary state.R2 is necessary to limit the surge of DC currentwhen the subscriber set goes off-hook.

The ringing signal must be DC biased at the batteryvoltage in order for the MH88610 to detect an off-

hook condition while the ringing signal has beenapplied. The operation of the ringer at the telephoneend of the loop causes AC current to flow in the loop.This current may cause the device to indicate a falseoff-hook. In order to prevent this from happening, acapacitor is connected between ground and the CAPpin while the ringing signal is connected to the loop.The capacitor is disconnected for normal operationwhen the ringing signal is removed. In the applicationcircuit one of the SD outputs of the codec is used toground one end of the capacitor when the ringing isapplied. The SD3 output is an open drain outputwhich is in high impedance state when it isdeactivated and connected to GND when activated.For normal operation SD3 is deactivated and theground is removed. C8 is left grounded through a470 kΩ resistor. The resistance is large enough thatC8 is effectively out of the circuit. Resistors R3 andR4 are used in order to disconnect the ringing signalfrom the two wire loop when the subscriber set goesoff-hook during ringing. When the set goes off-hook,the SHK output will go low to-5V. This will turn offtransistor T1 which in turn will disable relay K1, thusdisconnecting the ringing signal from the loop.

5.4 Transmit and Receive Signal Levels

The transmit and receive levels for the Codec-SLICcircuit depend upon the gain through the SLIC andthe programmable gain through the codec.

0dBm0 for a Codec

Codecs from different manufacturers operate at voltage levels best suited to the semiconductortechnology used. However, all PCM codecs designed to meet CCITT standards are calibrated to a definedfull scale standard. The maximum peak analog voltage which the device can accept is referred to as theoverload decision level and corresponds to 3.172 dBm0 for µ-law devices and 3.14 dBm0 for A-lawdevices. The 3.172 dBm0 level is defined by CCITT as being a sinusoid whose peak voltage is equal to±8159 normalized voltage units for µ-law codecs. The normalized voltage units have been chosen so thatall quantization levels are expressed as integers. For A-law devices the comparable value is ±4096 units.In this manner the CCITT standard indirectly defines the power at the 0 transmission level point. All gainsand losses in a digital system are specified with respect to this power level.

The overload decision level for Zarlink µ-law codecs at the analog input corresponds to a voltage of 4.829volts peak-to-peak. This voltage level has been selected purely due to the technology used for the A/D orD/A conversion in the device. By definition, according to CCITT recommendations, this corresponds to apower level equal to 3.172 dBm0.

3.172 dBm0 = 4.829 Vpp

0 dBm0 = 3.352 Vpp or 1.185VRMS.

External gain or loss has to be added for specific requirements. The gain pads built into Zarlink Codecs canbe used to change the gain or attenuation.


A-159

The 0 dBm0 level for Zarlink µ-law codec's is 1.185VRMS. This is the amplitude of the analog signalgenerated at the VR output when a digital milliwattbyte sequence is input at the PCM port of the codec.The digital milliwatt corresponds to 0 dBm (seewindow on 0 dBm0)

1.185 VRMS = 3.69 dBm (referred to 600 ohms)

Therefore there is a net gain of 3.69 dB when adigital signal is converted to analog by the codec.

The MH88610 attenuates the signal applied at theVR pin by 6.69 dB (typical) before transmitting it outon Tip and Ring. When the voice codec is interfacedto the MH88610, there will be a net attenuation of 3dB from the digital side to the analog two wire side.Conversely, when a 3.69 dBm signal is applied at theVX input of the codec, the PCM signal generatedcorresponds to a digital milliwatt which by definitionis the digital equivalent of 0 dBm. Therefore there isa net loss of 3.69 dB when an analog signal isconverted to PCM. The MH88610 applies a gain of0.69 dB in from the two wire tip and ring port to theVX pin. Therefore there is a net loss of 3 dB from thetwo wire port to the digital port.

The losses and gains for a typical connection areillustrated in Figure 8.

The gain and losses through the voice codec can bechanged by the user through Control Register A. Thegain in the transmit direction can be increased by 7dB in 1 dB steps. When the codec is used incombination with the MH88610, the maximum gainthat can be added from the Tip/Ring port to thedigital side is 13 dB. In the digital to analog direction,the attenuation can be varied from 0 to -7 dB in 1 dBsteps. Incorporating the loss introduced by theMH88610 and the inherent loss in the D to Aconversion (due to the codecs designed 0 dBm0level), the net attenuation from the digital side to theTip and Ring port can be varied from -3 to -10 dB.

The facility to modify the gain or loss on aconnection-by-connection basis is necessary tomeet loss and level plans imposed by differenttelephone administrative authorities (see nextsection). The software control of the gain pads in theZarlink voice codecs makes it very easy to meetdifferent loss and level plans. For example, in theconnection illustrated in Fig. 7, if the end-to-end lossrequired was 3 dB, the codecs transmit gain pads inboth ends could be set to provide 3 dB gain. Thiswould counter the fixed losses of the variouscomponents. For 0 dB net loss through the system,

the gain in the receive direction (A to D) would haveto be set to +6 dB.

6.0 Consideration of Loss and LevelPlans in SLIC Design

Introduction of digital switching and transmission canbe expected to improve the overall transmissionquality. However, this will occur only when thepenetration of both digital transmission and switchingbecomes high. In the interim, where a mixture ofanalog/digital transmission and switchingpredominates, a certain degree of degradation of thesignal occurs due to the A/D and D/A conversions,and, due to loss introduced to maintain stability inspecific connections. In an all digital network,transmission and switching systems will not add anyappreciable degradation to the end-to-end quality ofthe voice signal. Unlike transmission of an analogvoice signal, PCM encoded signals do not notundergo any attenuation during transmission. Therewill be no requirement for 2/4 wire hybrid circuitssince digital transmission requires separate receiveand transmit channels. On standard telephone loopsthis can be achieved using elaborate echocancellation or time compression multiplexngschemes.

Digital switching and transmission systems areinherently four wire. The encoded voice istransmitted and received on different paths - makingup a four wire circuit. Connection to a two wireanalog loop, requires a hybrid circuit (described inthe previous section). The four wire circuit forms aclosed loop feedback system. If the impedance of thehybrid balance network does not match theimpedance of the subscriber loop, energy willcirculate within the closed four wire path. Theconnection will start to oscillate if the closed loop hasunity voltage gain at a frequency at which the phaseshift is a multiple of 360 degrees. In telephony, thetendency of a system to oscillate is described usingthe parameter referred to as Sing Margin. If the SingMargin is low, the connection tends to sound hollow(the rain barrell effect) or distorted. The rain barreleffect can also be due to the presence of listenerecho. Listener echo is the result of the talker’s signalgoing through two reflections and adding, with somedelay, to the transmitted signal. The listenerperceives the received sound to be hollow. Thephenomenon is illustrated in Fig 9. On longconnections talker echo is more dominant.

One other factor which is also of significantimportance in network design is contrastminimization. Contrast minimization generally entailslimiting the loudness in connections which do not


A-160

have sufficient inherent loss in the level of the signaltransmitted. This ensures that the difference in typeof connections made is not perceptible to the callerand the loudness level is maintained within a specifictolerance level.

In order to control singing, near singing, talker echoand minimize contrast, loss is introduced in theconnection. A compromise loss value is selected sothat the extra added signal attenuation providesadequate echo control while providing satisfactoryvolume level for the primary speech path. The actual

loss added depends upon the type of connection, thetype and length of trunk involved, etc. Loss and levelplans implemented by telephone administrations arebased on large amounts of statistical data and takeinto account the various factors discussed above.The North American VIA Net Loss Plan wasintroduced in the 50’s for loss allocation in the largelyanalog network. The more recent North AmericanSwitched Digital Network Loss Plan was introducedin the 70’s to accommodate the emerging digitalswitching technology in the class 5 end office. Underthis plan digital trunks are operated at zero loss. The

Figure 8 - Loss and Gains through a Typical Connection

Figure 9 - Echo Path in Typical Telephone Connection

Digital Switchor

Transmission Medium

MH88610MT896XCodec

MT896XCodec MH88610

VR

VX

DSTi

DSTo

STo1

STi0

STi1

STo0

DSTo

DSTi

+0.69dB -3.69dB 0dB +3.69dB -6.69dB

+0.69dB -3.00dBm0 -3.00dBm0 +0.69dBm

-6.00dBm

VX

VR

VX

VR

VR

VX

0dBm

Codec gain pads are set to provide 0dB loss

Talker

HYBRID HYBRID

Listener

Talker’s Primary Speech Path

Talker’s Echo Path

Listener’s Echo Path

G

G


A-161

switch adds extra loss to realize the required line totrunk loss. For example, 6 dB loss is added inconnections to digital tandem office trunks, whileonly 3 dB loss is added for digital intraoffice trunks ina metropolitan area. Intraoffice calls have a nominal0 dB loss through the switch.

Loss and level plans can differ significantly from onecountry to another.

Digital PBXs have to accommodate a number ofdifferent line types and can, therefore, have similarconstraints as the public switched network. Differentline types include digital on-premise lines, off-premise lines, analog central office trunks, digitalcentral office trunks and digital toll office trunks. On-Premise Subscriber Line Interface Circuits (ONS)interface directly to the subscriber two wire loopswhich service standard telephone set for basic POTSfunction. Off-Premise Subscriber Line InterfaceCircuits (OPS) interface to loops which traverseoutside the protective environment of a building. Theloop length is generally longer here also. OPScircuits may also be employed in Direct InwardDialing Trunk interfaces (connecting to a centraloffice). Central Offices are generally interfaced to thePBX through either Loop Start or Ground Starttrunks. Digital Central Office Trunks such as AT&T’sT1, are also becoming more common especially inlarger PBX’s. Digital transmission over standardloops is also increasingly being employed behind thePBX. This has been greatly helped by the wide scaleavailability of integrated circuits such as Zarlink'sMT8972 which permit full duplex transmission of highspeed digital signals over standard twisted pair. Thecapacity of a single loop can effectively be doubledby using a device such as the MT8972. This makes itcost effective for PBX manufacturers to offer fullfeature phones which permit simultaneous voice anddata transmission over existing telephone wiring in abuilding.

In order to make private networks compatible withthe public network, the Electronic IndustriesAssociation has developed a loss and level plan fordigital PBXs. This plan stipulates the recommendedinsertion loss for different connections. A shortsummary of the plan has been presented in Table 2in matrix form. Note that all the possible connectiontypes have not been included in the diagram.

As an example note that when an ONS line isconnected to another ONS line, 6 dB of attenuationis inserted in both directions. In ONS-OPS typeconnections, the inserted loss is only 3 dB. No loss isinserted when an ONS line is connected to a C.O.trunk.

Table 2. µ-Law Digital PBX Loss Plan (Ref. 1)ONS : On Premise SubscriberOPS: Off Premise SubscriberA/CO: Analog Central Office TrunkD/CO: Digital Central Office TrunkA/TT: Analog Tie Trunk (interconnecting two PBX’s)D/TT: Digital Tie Trunk

The programmable gain pads in Zarlink’s Voice Codecssimplify the circuitry required to accommodate lossand level plans in different countries.

7.0 Line Card Power Supply Filteringand Codec Circuit Protection

Zarlink CMOS filter/codecs are extremely reliabledevices. Significant measures have beenincorporated into the design of the device to preventlatchup caused by external factors. However, inapplications where the circuit cards are inserted intolive sockets, adhering to the following guidelines willhelp to further reduce the probability of latchup (seeFig. 10).

- Ensure that ground is always connected toeach device before any of the other supplies orsignals. An extended ground pin should beused on the card edge connectors.

- Transient protection must be provided againsteven momentary transitions outside the supplyvoltages. Schottky diodes fitted between +5Vand GND and between GND and −5V to clamptransient power supply reversals during power-up are recommended. Voltage excursionsexceeding the absolute maximum ratingsshould be limited by connecting transorbs (withbreakdown voltages not exceeding 6V) acrossVDD and GND, and, across GND and VEE.

- All supplies must be decoupled close to thecard edge connector. Decoupling with a 25µFelectrolytic capacitor in parallel with a 0.1µF

ONS≠ ↓

OPS≠ ↓

A/TT≠ ↓

D/TT≠ ↓

ONS→

←

6

6

3

3

3

3

3

9

OPS→

←

3

3

0

0

2

2

0

6

A/CO→

←

0

0

0

0

0/2

0/2

-3/0

3/6

D/CO→

←

3

3

0

0

2

2

0/-3

6/3


A-162

ceramic capacitor is recommended. Thiscombination provides adequate filtering forboth high and low frequencies, andaccommodates large current spikes due toswitching. The trace length from the edgeconnector to the decoupling capacitors shouldbe kept short. Further high frequency filteringmay be provided by placing 50 µH inductors inseries with the supplies.

- The ±5V supplies must be decoupled at eachcodec with 0.1 µF capacitors from +5 to GND,and _5V to GND connected as close to thedevice as possible.

- If the codec is connected directly to atransformer type SLIC, back-to-back 5V zenerdiodes from the analog input and output pins ofthe codec are recommended to prevent spikesinduced on the line side of the transformer fromaffecting the codecs analog I/O pins. Zenerswith low leakage should be used.

- The +5V supply for the digital control circuitryon the line card should be derived from theedge 5V - GND decoupling point. This supply

rail should be kept separate from the codecsupply rail.

- Each logic device should have a decouplingcapacitor from +5V to GND close to the device.

Ground connections for low voltage relaysshould use the digital ground.

8.0 Line Card Layout Guidelines

Line card designs using voice codecs incorporate asignificant amount of digital and analog circuitry. Oneof the most important steps in designing a low noiseline card is to ensure that the layout of the circuitcomponents and the PCB tracking result in minimumof cross coupling between analog and digital signals.The following general guidelines can serve tooptimize performance (see Figure 11):

- Separate analog and digital grounds should bemaintained on the circuit card. However, inorder to minimize ground loops, separategrounds going all the way to the power supplyare not recommended. The optimum groundingconfiguration is to have a single ground source

Figure 10 - Power Supply Decoupling and Protection Circuitry for Line Cards

EDGE Connector Side Component Side

+12

+5

DigitalGND

AnalogGND

-5

-12

C1 C2 T1 D1 C2

C1 C2 T1 D1

L1

+5VA

+5VD

C2

L1

C1

+12V

DigitalGND

AnalogGND

C1

-12V

C1

L1

C1

C1C2D1T1L1(Individual power supply decoupling capacitors at each device are not shown)

22 µF (electrolytic 25V)0.1µ F (Ceramic 25V)Schottky Diode (IN5817)Transorb (Motorola P6KE6.8 or Unitrode TVS505, min. breakdown voltage = 6V)55 µH Optional components to filter high

frequency signals in power supply

L1

-5VA


A-163

from the power supply. If separate analog anddigital ground rails are available from the powersupply, they should be interconnected togethernear the edge connector into a central groundpoint for the entire card. Distinct analog anddigital grounds should be derived from thiscommon point and maintained separately onthe circuit board.

- Voice codecs contain both analog and digitalcircuits. The Zarlink MT8960-67 series of voicecodecs have two ground pins: GNDA andGNDD. As indicated in the codec data sheetsthe potential difference between the GNDDand GNDA pins should not exceed 0.1V.Optimum performance is achieved byconnecting the two pins together close to thecodec. The interconnected pair should then betied to the analog ground rail.

- The +5V and -5V supply tracking to the codecsshould be routed adjacent to the ground rails toensure that any high frequency noise picked upby the trace is common mode.

- Digital control signals from the logic devicesshould not be routed near the 2.5V referencevoltage input or the ANUL pin on the codec. Ingeneral, circuit traces carrying digital signalsshould not be run close to or in parallel withtraces carrying analog signals.

- The reference voltage input is a highimpedance input. The PCB trace carrying the2.5V reference voltage must not be positionedparallel to digital signal tracking. Ideally itshould be placed between analog supply orground rails.

- The capacitor attached to the ANUL pin on thecodec should have minimal lead length andtrack between the analog ground and thedevice pin.

- Edge connector pins carrying analog signalsshould not be assigned adjacent to pinscarrying digital signals.

- All circuit tracking which carries signalscapable of inducing large emf’s into the audiochannel should be routed around the edge ofthe card. This includes ringing signals, 2-wiresubscriber circuits, battery feeds and relaycontrol circuits. These tracks must not runclose to or in parallel with the tracking carryingthe unbalanced signals from the voice input/output pins on the codec. The tracking for the

balanced two wire subscriber lines from theSLICs should run in parallel with each other toensure that any noise picked up is commonmode.

- The diodes and varistors for primary andsecondary protection for the Tip and Ring linesshould be connected as close to the card edgeconnector as possible. A separate energydumping ground should be used forovervoltage and lightning protection. An energydumping ground is a heavy ground originatingfrom the power supply.

9.0 Conclusions

The Zarlink MT896X series of voice codecs togetherwith Zarlink’s MH88610 offer telephone systemdesigners most of the functions necessary toconstruct analog line interface cards for digitalswitching systems. Features such as programmablegain pads and uncommitted drive points in Zarlinkcodecs contribute to substantial savings in hardware.In addition the solutions provided by Zarlink’s extensivefamily of compatible ST-BUS products simplifyoverall system design. For more information on theseand other telephony components, refer to theappropriate data sheet

10.0 References

1. PN-1378 Private Branch Exchange SwitchingEquipment for Voiceband Applications.Proposed Rev. to RS-464-1, EIA.

2 TR-TS7-000507 LATA Switching SystemGeneric Requirements (Section 7), Issue 2,Bell Communications Research, July 1987.


A-164

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www.zarlink.com

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively

“

Zarlink

”

)is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application oruse of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result fromsuch application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents orother intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the useof product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights ownedby Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form partof any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and otherinformation appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability,performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guaranteethat such methods of use will be satisfactory in a specific piece of equipment. It is the user

’

s responsibility to fully determine the performance and suitability of anyequipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarilyinclude testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injuryor death to the user. All products and materials are sold and services provided subject to Zarlink

’

s conditions of sale which are available on request.

Purchase of Zarlink s I

2

C components conveys a licence under the Philips I

2

C Patent rights to use these components in and I

2

C System, providedthat the system conforms to the I

2

C Standard Specification as defined by Philips.

Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved.

TECHNICAL DOCUMENTATION - NOT FOR RESALE

For more information about all Zarlink productsvisit our Web Site at

www.zarlink.com

Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any suchinformation, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application oruse. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectualproperty rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product incertain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.

This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form partof any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and otherinformation appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding thecapability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constituteany guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance andsuitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing doesnot necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result insignificant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.

Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the systemconforms to the I2C Standard Specification as defined by Philips.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright Zarlink Semiconductor Inc. All Rights Reserved.

TECHNICAL DOCUMENTATION - NOT FOR RESALE

For more information about all Zarlink productsvisit our Web Site at

application note msan-131 - microsemi

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