I. INTRODUCTION

In conjunction with the SSC20 Liaison Standards Subcommittee

of the Institute of Electrical, Electronic Engineers (IEEE) Stan-

dards Organization [1], a new multidimensional ATE “Open Sys-

tem Platform” packaging standard has been initiated under IEEE-

P1552 Structured Architecture for Test Systems (SATS). An ar-

chitecture that will have profound impact on current test com-

puter-busboard systems in reducing costs and size, while improv-

ing performance and supportability.

The key to ATS Integration and Test Program Set (TPS) cost re-

duction/avoidance requires us to reduce variations of the soft-

ware /hardware interfaces between ATS. Standardization func-

tionally defines and provides guidelines for developing the inter-

faces within a ATS. Applying these standards with Commercial

Off The Shelf (COTS) modular compatible pluggable modules,

the ATS structure becomes more homogenous in its integration

and supportability. This open architecture approach avoids unique

government requirements and associated nonrecurring costs, en-

hances product availability/performance, and benefits from in-

dustry investment/technology.

SATS replaces/extends the current two dimensional plug and play

computer-based architecture of VMEbus [2], VXIbus [3], PCI-

bus [4], PXIbus [5], and several other standards into a multidi-

mensional integrated hardware architecture, as conveyed by Fig-

ure 1. Under the SATS Frameworks, Instrument/Power Mezza-

nine (IPM) Carrier Modules and Serial/Test Bus Integration, the

current 2-D backplane is reconfigured into 3-D matrix wiring

panels supporting control, power, and signal interconnectivity.

Legacy VMEbus, VXIbus, PCIbus, PXIbus Standards are sup-

ported through a hybrid process that integrates respective back-

plane standard characteristics with SATS wiring panel specifica-

tions. Legacy standards can choose to integrate current front

connectors to SATS wiring panels, or convert to the SATS com-

mon CompactPCI [6] connector family. SATS reduces dissimi-

lar front panel connector proliferation and eliminates wire be-

tween chassis systems. This has the potential of reducing Auto-

matic Test Systems (ATS) material costs, labor, test time, and

support by 40%.

A preliminary set of specifications has been developed and is

undergoing refinement under the IEEE Standards Organization

process. Meetings are planned for IEEE, NEPCON, and AS-

SEMBLY TECHNOLOGY trade shows to broaden participation.

II. TECHNICAL PROBLEM

The technical problem of this Standard was first addressed by

Department of Defense memorandum OSD (A&T) - 29Apr94,

DOD Policy for Automatic Test Systems, by direction of Noel

Longuemare. The following memo caption reflects on the in-

tent of Mr. Longuemare’s directive and serves to lead our ef-

forts; “ATS capabilities shall be defined through control of criti-

cal hardware and software elements and interfaces to ensure DOD

family tester and COTS tester and component interoperability,

and to meet future DOD test needs”.

A joint government/industry Critical Interface Working Group

(CIWG) effort furthered this ATS interface standardization pro-

cess. It was conducted under the auspices of the military Joint

Service Automatic Test Systems Research and Development Inte-

grated Product Team (ARI), by a combined government and in-

“ATE Open System Platform” IEEE-P1552

Structured Architecture for Test Systems (SATS)Working Group Cochairmen

Michael J. Stora ; Modular Integration Technologies, Boonton, NJ; mjs@modintec.com

David Droste; PEI Electronics Inc., Huntsville, AL; DDroste@PEI-IDT.com

Abstract- The IEEE-P1552 Structured Architecture for Test Systems (SATS) Standards effort, is a multidimensional ATE “Open System Platform”

packaging specification. The Standard defines data/signal/power interconnect mechanical/electrical mating connector requirements and common

hardware packaging form factors. Addressed are plug&play wiring panels, switchable instrument/power mezzanine (IPM) modules, high speed

serial bus control, and test bus matrix functionality, that permit subelement interchangeability and interoperability. The standard’s functional

performance requirements are limited to mechanical engagement, connector styles/footprints, electrical pin characteristics, and pin mapping defi-

nitions. As a higher order plug&play architecture SATS supports legacy VXIbus and PXIbus architectures as hybrid subsystem integrations.

Figure 1. SATS Multi-Dimensional Plug&Play Interconnectivity

dustry Critical Interfaces Working Group[7]. The CIWG objec-

tives were to identify the critical ATS interfaces that impacted

interoperability/interchangeability of system hardware and test

program set transportability. Although the results established

clear definitions of the critical interfaces, very few could relate

to commercial interface standards, beyond existing VXI, com-

puter data interfaces and government specifications.

The remaining issues of the technical problem are those critical

packaging and interconnect hardware interfaces not addressed

by current industry standards. Hardware interfaces relate pri-

marily to packaging and data/signal/power interconnect standards.

These standards typically define mainframe and subelement (mod-

ule) mechanical/electrical mating specifications, that should per-

mit subelements to be interchanged without impact to subele-

ment interoperability. The functional performance of the stan-

dard is normally limited to mechanical engagement, connector

styles/footprints, electrical pin characteristics, and pin mapping

definitions. This permits various vendor products (subelement/

module) to interoperate (plug & play) with no or minimum modi-

fication by the integrator or user. Functional performance speci-

fications of unique subelement capabilities, that exceed interop-

erability requirements are typically relegated to the integrator/

user to define.

III. OBJECTIVES OF THE SATS STANDARD EFFORT

The mission of this Standard effort are threefold: (first) to estab-

lish ballot ready specifications for the Structured Architecture

for Test Systems (SATS) Standards; and (second) validate those

specifications through fabrication of multivendor/multifunction

prototype modules that would be integrated into working SATS

architecture. The (third) objective is achieving Users and Inte-

grators recognition and acceptance of the Standard(s), that in turn

will drive vendor/supplier requirements. This represents a de-

parture from previous Test Standards that were established by

supplier/vendor motives, and therein reasons for their respective

limitations.

Success will be measured by SATS ability to: (a) align with COTS

- Commercial Off The Shelf products, that are designed to exist-

ing commercial standards, i.e. IEEE, Eurocard, VXI, VME; (b)

reduce costs by exploiting commercial investment, limited non-

recurring integration development, and competitive pressures; (c)

improve availability and interoperability through common archi-

tectures and multivendor product offerings; (d) improve test pro-

gram set transportability; (e) increase ATS supportability through

standard acceptance, available technical/spares third-party sup-

port tools and resources; and (f) assure longer product life by

structuring the architecture for future commercial subelement pre-

planned product improvements and ATS technical insertion.

IV. SATS GENERIC INTERFACE ARCHITECTURE

The following diagram, Figure 2, illustrates the traditional VXI

based ATS hardware/electrical connector interface elements em-

ployed: (a) Rack/Chassis Mechanical Integration Structure; (b)

Computer Control Interface; (c) VXI/IEEE-488 Instruments;

(d) Power Distribution; (e) Cabling/Signal Interconnects; and

(f) Receiver Fixture Interface Subsystem.

Figure 2. Traditional VXI/IEEE based ATS hardware/electrical generic interfaces

V. RELATED STANDARDS ACTIVITIES

The SATS Program minimized its specification development pro-

cess by embracing current or planned Standards efforts. The fol-

lowing represents many of those being implemented under SATS:

(a) IEEE SSC20 Technical Committee for the IEEE P1226.X, VXI

Instrument Control [8]; (b) IEEE I&M Technical Committee for

the IEEE 488, VXI Instrument Control [9]; (c) IEEE P1505 I&

M Technical Committee for the Receiver Fixture Interface [10];

(d) VXI Consortium for the VXI Hardware Specification 1.4[11];

(e) VXIplug&play Operating Systems and Instrument Drivers,

VPP-3/4[12]; (f) EIA Standard, RS-310-C, Racks, Panels and

Associated Equipment [13]; (g) ANSI, VME/VME-64 Hardware

Standard [14]; (h) IEC 917 (DIN 43355) / IEC 603-2 (DIN 41612)

Connector Specifications [15] and (i) M-Module Mezzanine

Specification VITA 12[16]. Other Standards and related Organi-

zations may be consulted for electrical and packaging specifica-

tions.

VI. SATS STANDARD TECHNICAL APPROACH

The SATS Standard defines and implements a scalable/modular/

cableless ATE “Open System Platform” packaging specifica-

tion, conceptually shown in Figure 3, through an IEEE/IEC in-

dustry standardization process. The SATS architecture frame-

work and respective seven (7) interfaces are intended to mini-

mize design development by reducing complex functionality to

the level of a plug-on mezzanine card (IPM). This minimizes

impact to the integrated Carrier Module, Wiring Panel, and RFI

structure, thereby accommodating reconfigurability, upgradeabil-

ity/technical insertion and general reuse more effectively. By

distributing the Switch Matrix Bus Architecture from the Carrier

Module (functional access port), to the RFI System (UUT access

port), in a scalable and software selectable manner, I/O

selectability instrument sharing, fault tolerance, and system di-

agnostics are enhanced.

As the next generation to the current VXI/VME instrument/mod-

ule control standards, the SATS Frameworks “open” mechani-

cal and electrical packaging specification implements:

1) Mechanical Integration Structure (MIS) modular/scal-

able plug&play, cableless, environmental sealed, mainframe ar-

chitecture, utilizing EIA Electronic Rack Specifications [17], Eu-

rocard Mechanical Packaging and DIN 43355 Connectors Stan-

dards;

2) Plug-on Instrument/Power Mezzanine (IPM) Card pro-

visioning functionality at the lowest cost/technical impact and

Common Carrier Module with 3U/6U/9U scaleability;

3) Computer Control Distribution (CCD) high speed serial

bus control for instrument/functional operation, test signal/power

switch matrix distribution system management (see Figure 4);

4) Integrated scalable test/power distributed switch matrix

for multi-asset selection/sharing;

5) IEEE-P1505 Receiver Interface with I/O switchable and

scalable from 4 slot cable/PCB connector interface to 29 slot

multi-OTPS Fixture engagement; and

6) Support for legacy VME/VXI/PCI/PXI test standards.

• Integrated Receiver FixtureInterface (RFI)

• SATS-RFI Integration PrintedWiring Panel

• Modular/Scaleable Plug&Play CompositeEnvironmental Sealed Chassis

• Modular/Scaleable Plug&Play 3U/6U/9UIPM Module Implementation (configuration shown supports 12 Slots, 3-9U high, B Size depth Modules w/72 IPM Cards)

• SATS-IPM Module IntegrationPrinted Wiring Panel

• External Heat Exchanger withSealed Internal PressurizedCooling System

Figure 3. SATS Typical Multi-Framework ATE “Open System Platform”

VII. ELECTRICAL SYSTEM INTEGRATION FRAMEWORKS

A. ESI Overview

The Electrical System Integration (ESI) Specification defines

the overall SATS Frameworks electrical interconnect system, con-

nectorization, switching network, and electrical bus pathways for

power, control and stimulus/measurement test signals. The dia-

gram (Figure 4), correlates to the atypical configuration shown

in Figure 3, reflecting general interfaces and related elements of

the electrical frameworks and their respective relationships. When

implemented under a plug&play architecture, that utilizes ad-

vanced high speed digital/RF printed circuit board technology,

considerable benefits accrue. Specifically, it embeds and directly

couples control, power and test signal bus pathways between the

test system controller, instrument/power resource, and the UUT

interface. The advancement of embedded RF printed circuit

board transmission lines designs permit signals to reach 18GHz

bandwidths. ATE signal integrity and repeatability under

plug&play PCB construction, also dramatically improves pro-

ducibility, as well as reduce integration and test acceptance times

by 40%. A greater gain is achieved by through lower mainte-

nance support costs (40%), and product technology insertion/evo-

lution costs (60%).

The ESI specification supports/embeds three distribution sub-

systems within the plug& play board/wiring panel fabric. They

are: (a) the Computer Control Distribution (CCD) Subsystem;

(b) the Power Switching/Distribution Bus (PDB) Subsystem;

and (c) the Test Signal Switching/Distribution Bus (TSD) Sub-

system. The Eurocard DIN 43355 Connector serves as common

interconnect between board/wiring subelements.

Figure 4. Electrical System Frameworks Integration Overview

External Instrument/Power

Rack Mount Resource

IEEE488/Ethernet/Serial Bus

Operator Interface

and Display

IEEE488/Ethernet

ATE Host CPU

Power Distr Control

Timing& Synch

System Interrupt

System Serial Bus

Envirmt/Diag CntrlEmbedded/External/Multi-

Computer

Subsystem(s)

Switch/

Routing

Circuit,

Signal

Conditng,

Active

Instr/or

Personlty

PCB

Module

Fixture

Plug-in

Circuits/

Modules

Signal

Power

RF

Signal

Power

RF

Fixture

Frame-

work/

Enclo-

sure

and

Plug-in/

Direct

Mount

Assy

Recvr

Frame-

work

and

Mech

Drive

Assy

Receiver Fixture

Interface Subsystem

Unit

Under

Test

(UUT)

Wiring Panel

Bus

Interconnect

Subsystem

Instr/Power

Mezzanine

(IPM) Card(s)

& 3U Carrier

Module or

Custom 3U

Module

Instrument/Power

Mezzanine (IPM)

Card(s) & Carrier

6U Module

- or -

Custom 6U Module

System Serial Control Bus

Signal/Low RF Test Bus High

RF Test Bus

Power Test Bus

Instrument/Power Mezzanine (IPM)

Card(s) & Carrier 9U Module

- or -

Custom 9U Module

External Resource Bay

for VME Chassis

and

Instrument B-Size (6U)

Modules

External Resource Bay

for VXI/PXI Chassis

and Instrument

C-Size (6U) Modules

Instr/Power

Mezzanine

(IPM) Card(s)

& 3U Carrier

Module or

Custom 3U

Module

Instr/Power

Mezzanine

(IPM) Card(s)

& 3U Carrier

Module or

Custom 3U

Module

Instr/Power

Mezzanine

(IPM) Card(s)

& 3U Carrier

Module or

Custom 3U

Module

B. Computer Control Distribution (CCD) Subsystem Spec

Use of an advanced computer serial bus network embraces com-

puter industry trends as reflected in Figure 5. This distribution

subsystem (see Figure 6 illustrating Rapid I/O implementation),

incorporates physical electrical pathways that will host any num-

ber of advanced Computer Standards, such as Infiniband[18],

Rapid I/O [19], or PCI Express [20].Figure 5. Serial Bus Network and Distribution Subsystem Spec

This distributed network fabric will incorporate advanced trans-

mission line technology facilitating network speeds to 12G Bytes

performance. Employing parallel-multi-serial lines interface

fabric, distributed multi-task control, and segregated node con-

trol points, the test system control can achieve both speeds and

technology evolution without impact.

Figure 6. Serial Bus Network and Distribution Subsystem Spec

C. Power Switching/Distribution Bus (PDB) Subsystem Spec

Power Switching/Distribution Subsystem (see Figure 7), com-

bines distributed primary 48 Volts Direct Current (VDC) Bus with

DC-DC Fixed/Programmable Instrument and Power Mezzanine

(IPM) Submodules. Outputs from these DC-DC IPM’s are swit-

chable to the System Power Distribution Bus Matrix which feed

system resources or Unit-Under-Test (UUT) power requirements.

The power switch matrix design incorporates a: (a) 30 amp [30A]

High Current Primary 48VDC Feed and Multi-Return/Ground

Lines; (b) 16 wire - 8 output scalable System Power Distribution

Bus Matrix; and (c) Power Bus Entry Level Switching at the IPM

and In-line Receiver Fixture Interface (RFI) Power Switching.Figure 7 Power Switching/Distribution Subsystem Spec

D. Test Signal Switching/Distr Bus (TSB) Subsystem Spec

SATS defines an advanced distributed test signal switching fab-

ric, as shown in Figure 4 and 8, that routes resource signals to a

wide matrix of pin map contacts at the UUT interface. It in-

cludes: (a) Resource-to-Bus Entry Switching at the Instrument

Single Segment Broadcast <33MHzExamples: CompactPCI, VME, VXI

Bridged Hierarchy

Broadcast <133MHzExamples: PCI, PXI,

VME, VXI

Very

High

Frequency

• Packet Switched

• Point-to-Point

• Low Pin CountS

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1x8 SwitchMezzanine Card

Instr IPM Cntrl/Switch Carrier

..

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Mezzanine Card

Instr IPM Cntrl/Switch Carrier

Custom Instrw/Cntrl &

Switch Module

InstrumentMezzanine Card

Instr IPM Cntrl/Switch Carrier

Custom Instrw/Cntrl &

Switch Module

InstrumentMezzanine Card

Instr IPM Cntrl/Switch Carrier

OtherATE

Resources

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Embedded Panel N x 32 wireScalable Test SignalDistribution Matrix Bus

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UUTFixtureReceiver

Receiver1x4 Switch

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Receiver

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Module.. ..1x4 Switch 1x4 Switch

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VXI/PXIInstrument

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Embedded Panel N x 16 Wire Scalable Test Signal Distribution Matrix Bus

Part III

Logical SpecificationInformation necessary for the endpoint to process the transaction,(ie. transaction type, size, physicaladdress)

Transport SpecificationInformation to transport packet fromend to end in the system, (i.e. routingaddress)

Physical SpecificationInformation necessary to movepacket between two physical device,

Common

Part I Part II Part V

I/O System Message Passing Globally Shared Future

Compliance Checklist

Inter-Operability

8/16 LP=LVDS 1x/4x LP Serial Future Physical

Part IV Part VI

120/240VACInputPowerSource

48VDCPrimaryPowerFeed/

Return

Power EntryAC/DCModuleSource Power

SwitchModule

PowerSwitchModule

PowerSwitchModule

Receiver

UUT

Fixture

Fix/ProgmDCResource/UUTPower Output

Power MezzanineDC/DC Card

Power IPM ControlSwitch Carrier Module

Fix/ProgmDCResource/UUTPower Output

Power MezzanineDC/DC Card

Power IPM ControlSwitch Carrier Module

Fix/ProgmDCResource/UUTPower Output

Custom Powerw/Control &Switch

Module2x8 Scalable

Power DistributionMatrix Bus

Figure 8. Test Signal Switching/Distribution Subsystem Spec

and Power Mezzanine (IPM) Card level (located on the IPM Car-

rier Module; (b) In-line Bus Matrix Switching as dedicated re-

source modules (IPM Module); and (c) Receiver-to-Bus Matrix

Switching, that directs bus signals to specific Receiver Fixture

Interface (RFI) contacts. Combined with system control soft-

ware, the distributed switching architecture provides consider-

able signal routing flexibility, wire length and pin count reduc-

tion, while simultaneously enhancing system diagnostics and fault

tolerance.

E. Scalable High Performance Test Signal Bus Matrix Pin Map

Scalability of the embedded test signal matrix begins with 4 x 8

wire (16 transmission line signal connectivity-TLC), that can be

multiplied by the integrator to serve their respective requirements.

Pin Map shown in Figure 9, for a 9U high carrier module and

wiring panel interconnectivity can accommodate up to 64 TLC

test signal matrix, that can be in turn duplicated within the wiring

panel for a number of carrier modules.

Figure 9. Test Signal Switching/Distribution Subsystem Pin Map

Figure 10. Eurocard DIN 43355 Connectors

F. EUROCARD DIN 43355 CONNECTORS

The SATS electrical/pin map specifications builds upon the

“open” design of the IEC 917 (DIN 43355) Connector style,

shown in Figure 10. SATS will benefit from the well-defined

and established connector design, to characterize physical inter-

mateability properties of the interface. Utilizing predefined as-

pects of VME, VXI, PCI, PXI, and M-Module electrical bus/pin

definitions further reinforces SATS implementation of the IEC

917/DIN 43355 electrical pin functionality.

Z A B C D E F

2 2 GND TBP6+ TBS87 GND TBS88 TBP6- GND2 1 GND TBS83 TBS84 GND TBS85 TBS86 GND2 0 GND TBP5+ TBS81 GND TBS82 TBP5- GND1 9 GND TBS77 TBS78 GND TBS79 TBS80 GND1 8 GND TBP4+ TBS75 GND TBS76 TBP4- GND1 7 GND TBS71 TBS72 GND TBS73 TBS74 GND1 6 GND TBS68 TBS69 GND TBS70 TBS71 GND1 5 GND 3.3V TBS66 GND TBS67 3.3V GND1 4 GND TBS62 TBS63 GND TBS64 TBS65 GND1 3 GND 5V TBS60 GND TBS61 5V GND1 2 GND TBS56 TBS57 GND TBS58 TBS59 GND P 21 1 GND 3.3V TBS54 GND TBS55 3.3V GND1 0 GND TBS50 TBS51 GND TBS52 TBS53 GND9 GND 5V RES GND RES 5V GND8 GND TBS46 TBS47 GND TBS48 TBS49 GND7 GND TBS42 TBS43 GND TBS44 TBS45 GND6 GND TBS38 TBS39 GND TBS40 TBS41 GND5 GND TBP3+ TBS36 GND TBS37 TBP3- GND4 GND TBS32 TBS33 GND TBS34 TBS35 GND3 GND TBP2+ TBS30 GND TBS31 TBP2- GND2 GND TBS27 TBS28 GND TBS29 TBS30 GND1 GND TBP1+ TBS25 GND TBS26 TBP1- GND

2 5 GND 5V GND 5V GND2 4 GND TBS23 TBS24 GND GND2 3 GND 3.3V TBS21 GND TBS22 3.3V GND2 2 GND TBS17 TBS18 GND TBS19 TBS20 GND2 1 GND 5V TBS15 GND TBS16 5V GND2 0 GND TBS11 TBS12 GND TBS13 TBS14 GND1 9 GND 3.3V TBS9 GND TBS10 3.3V GND1 8 GND TBS5 TBS6 GND TBS7 TBS8 GND1 7 GND 5V RES GND RES 5V GND1 6 GND TBS1 TBS2 GND TBS3 TBS4 GND1 5 GND 3.3V RES GND RES 3.3V GND

1 41 3 KEY P 11 2

1 1 GND 3.3V RST# GND EALTHY# 3.3V GND1 0 GND TCK TMS GND TDI TDI GND9 GND 5V INTC# GND INTD# 5V GND8 GND INTA# TRG7 GND TRG8 INTB# GND7 GND -12V TRG5 GND TRG6 +12V GND6 GND TRG1 TRG2 GND TRG3 TRG4 GND5 GND 3.3V CLK+ GND CLK- 3.3V GND4 GND +T4x - T 4 x GND +R4x -R4x GND3 GND +T3x - T 3 x GND +R3x -R3x GND2 GND +T2x - T 2 x GND +R2x -R2x GND1 GND +T1x - T 1 x GND +R1x -R1x GND

• B-Size, 1.2 inch increment, 9Uhigh, Eurocard specifications

• Molded composite/extrusionmaterial framework with built-in engagement mechanism;

• Carrier Modulesmechanical support/alignment/shielding,and front mount andrear printed wiringpanel interconnect

• Carrier Modulesscaleable vertically3U, 6U, and 9U high,and horizontal in 1.2inch increments wide;

• Push-pull, temp controlled,high pressure cooling sub-system.

VIII. SATS MECHANICAL FRAMEWORKS

The SATS Frameworks Mechanical System Integration (MSI)

specification describes elements related to the: (a) mainframe and

engagement assembly; (b) printed wiring panels, CPCI connec-

tor family and bus matrix; and (c) instrument/power mezzanine

card and carrier module packaging. The SATS Frameworks is

based upon VMEbus: IEC 297-3[21], IEEE 1014[22]; and VXI-

bus IEEE 1155 Eurocard Mechanical Packaging[23] and con-

nector engagement/interoperability between the instrument,

power, switch/matrix and cooling module.

A. SATS Mainframe

The SATS Mainframe specification adopts a modular/scalable

Eurocard Packaging Standard design, that can be implemented

for either a suitcase or high end ATE system application. Al-

though, the mainframe specification permits smaller footprints,

typical implementations would build upon the standard B-size

depth, 3U/6U/9U VME/PCI or SATS I/PM carriers modules,

scaled to 9U chassis height and to 12 slots at 1.2 inch spacings

(see Figure 11). When fully integrated with cooling, engage-

ment mechanisms, and wiring panels total height can reach 14U

(24.5 inches) and 17.5 inch width. Multi-mainframes may be

integrated horizontally front-to-back, side-to side, and vertical to

meet various needs as illustrated in Figure 3.

Figure 11. SATS Base Mainframe Design

B. SATS Specification Mechanical InterfacesAn alignment/engagement mechanism necessary to integrate

multi-mainframes is not defined under the Specification and al-

lows unique solutions under the Standard as competitive incen-

tive to suppliers. Definition is however provided to assure com-

patible at module interface and direct mainframe pluggable inte-

gration levels. Many of these interfaces are related to connectors

applied to the module and mating wiring panel. These are criti-

cal to the overall objectives in reducing or eliminating the need

for wire and related costs and space. The chassis engagement

mechanism and test interface may be built upon the same distrib-

uted architecture used/proven in the IEEE P1505 Receiver Fix-

ture Interface (RFI) System.

C. SATS Wiring Panel/IPM Architecture

SATS architecture has been developed as a scalable, distributed

asset structure that can be employed independently, or in con-

cert, and matriced to a variety of Receiver Fixture Interface (RFI)

I/O pins, or with other RFI Ports. The unique High Speed Serial

Bus design (Infiniband, Rapid I/O, or PCI Express being consid-

ered), permits multi-tasking control at a rate as high as 13 Giga

Bytes/Sec. By reducing the functional stimulus/measurement,

power, and signal conditioning elements to mezzanine cards, the

lowest level of integration and I/O Control (TTL Interconnect)

can be implemented as was illustrated in Figure 12. At this level,

development costs are marginalized to card functionality, with

minimum or no costs expended for packaging, control, and ex-

ternal I/O. Instrument vendors who have developed products

previously for the M-Module Mezzanine Specification -VITA

12[16] will see direct similarities with enhanced I/O performance,

density, scaleability and common packaging.

Figure 12. SATS Plug&Play IPM/Carrier Module and Wiring Panel Design

• Implementaton is scaleable in threedimensions using options of multiple layersof mainframes, and various configurations of3U, 6U, and 9U high IPM Modules.

• SATS Implementaton Example Using Three (3) “B Size” SATSMainframes and multiples of 3U, 6U, and 9U Instrument/PowerMezzanine (IPM) Cards and Carrier Modules

• A single 19” SATS Mainframe withthirteen (13) 1.2 slots can integrate upto thirty-nine (39) 3U high IPM CarrierModules, which could supportseventy-eight (78) IPM Cards.

• A configuration of three (3) SATS Mainfranes supports 117 IPMCarrier Modules and 234 IPM Cards

0.1100

0.30000.3000

1.4717 1.5585 1.6609

0.1000

2.2000

0.59005.8039

1.6717

10.3091

0.1181

6.2992

FRONT PLANE

FRONT PANELBACK PANEL

BACK PLANE

2.1803

0.6811

0.1000

SEE 3U FOR TOP VIEW DIMENSIONS

connectorization to minimize signal path loss. A 3U module can

support two 1.5U IPM Cards, while a 6U module supports four

cards, and 9U six cards. SATS Specification permits vendors to

construct 3U, 6U, and /or 9U size IPM cards to optimize func-

tional component/circuit requirements. Custom combined card/

carrier modules may be supplied by vendors, as long as the me-

chanical/electrical interface specifications remain compatible

where the module/wiring panel integrates.

Figure 14. SATS 6U Instr/Power Mezzanine Card/Carrier Module

E. Wiring Panel /Backplane Specification

The SATS Wiring Panel/Backplane construction is a scalable

structured interconnect bus design that can be hybridized/cus-

tomized to meet unique test system requirements. It is the most

flexible aspect of any SATS implementation serving primarily

as the substitution for wire in current ATE configurations.

Digital I/O, Measurement and Stimulus Instrument/Power Mod-

ules (IPM) will apply current VXI Consortium and VXIplug&play

Specifications. SATS extends these specifications by applying

the DIN 43355 Connector to a transition device that converts

current VXI/PXI front panels to common SATS Carrier Module

I/O Specifications. The DIN Connector, shown in Figure 59,

provides direct signal interfacing direct to Expansion Bay Printed

Wiring Panel eliminating wiring while maintaining consistent

matched impedance/signal loss pathways to and from the Instru-

ment. Within the Expansion Bay Printed Wiring Panel (EBPWP),

SIZE: DWG NO:

RESCALE:

DRAFTSMAN

CHECKER

PRJ. ENG.

MFG. APRVL.

TITLE:

1. DIMENSIONS ARE IN INCHES. INTERPRET DIMENSIONING PER ANSI Y14.5M - 19942. FOR DIMENSIONS IN INCHES TOLERANCES ARE: `0.010 FOR ALL 2 PLACE DECIMALS `0.005 FOR ALL 3 PLACE DECIMALS `0.0005 FOR ALL 4 PLACE DECIMALS `1/2~ALL ANGLES `1/64'' ALL FRACTIONS

UNLESS OTHERWISE SPECIFIED

ENG. REF

315A W OOTTON STREETThe Complete Source for Your E

NEXT HIGHER ASSY:

3U-DaughtB

Modular Integratio

Administrator 10/4/2002

XX

XX

XX

XXXXX XXX X:X

1.7717

6.0039

6.2992

3.9370

0.5906

1.1960

FRONT PANEL

FRONTBACK PLANE

5.0591

0.2306

0.07770.0350

0.1181

1.0610

BACK PANEL

1.20001.2 in Center Line

0.0500 0.0500

0.0500

1.5743 1.5447

0.1000

0.1000

2.1803

0.4811

0.1500

0.1100

1.4717

0.1120

0.1000

5.8039

1.6717

0.5900

0.0500

0.1000

2.2000

Instrument/PowerMezzanine (IPM) Card

Adjacent Rear ChassisWiring Panel Rear/

Front PCI Connector

Adjacent ForwardChassis Wiring Panel

Rear/Front PCI Connector

IPM Carrier Module3U High Supporting

Two IPM Cards

IPM Connector SideComponent Mounting Areas

Carrier ModuleConnector Side

ComponentMounting Areas

IPM Back SideComponent

Mounting Areas

Figure 13. SATS 3U Instr/Power Mezzanine Card /Carrier Module

D. Instr/Power Mezzanine Card/Carrier Module Spec

The fundamental element of the SATS Standard describes the

packaging/interconnect definition of the Instrument/Power Mez-

zanine (IPM) Card and Carrier Module Specification. Serv-

ing as a stable modular/reconfigurable 3U/6U/9U structure, IPM/

Carrier Modules (shown in Figure 12), can be developed, inte-

grated and upgraded with minimum efforts. Packaging standards

implemented under VMEbus: IEC 297-3[21], Eurocard Mechani-

cal Packaging [17] and IEC 917/DIN 43355 [15] connector, de-

fine the mechanical/electrical interconnects between instruments,

power, switch/matrix and Receiver Fixture Interface elements.

As shown in Figure 13, the 3U IPM/Carrier Modules structure

supports a scaleable 1.5U/3U Instrument/Power Mezzanine Card

that is plugged on to a 3U Carrier Module. This IPM/Carrier

structure supports a broad range of applications in which func-

tionality can be packaged on the smallest 1.5U IPM card foot-

print, to a custom combined 9U card/carrier module footprint,

capable of supporting a vector analyzer capability. The

plug&play design also permits easy reconfigurability,

expandability, and upgradeability without modification each time

functional change is dictated.

Common carrier modules can support any number of functional

I/PM Cards through standard engagement/interoperability con-

nectorization. The Carrier Module also provides the embedded

Serial Interface Control, Switch Matrix, and Test/Power Bus in-

terface. Standardization of IEC 917 (DIN 43355) / IEC 603-2

(DIN 41612) Connector Specification at the dual interface points

of the Carrier Module and mating Wiring Panels points (see Fig-

ure 9). Combined, those features create a stable structural integ-

rity and interchangeability framework for the overall test system

architecture.

As described in Figures 13 and 14, the respective 3U and 6U I/

PM Card and Carrier Module Specification, IPM Cards are opti-

mized for double side board population and center short wire

16 Slot Receiver

Fixture ConnectorModules and Contacts

Four Slot Fixture withCable/Strain ReliefEnclosure

Receiver ConnectorModules and Contacts

Twelve Slot Fixturewith Enclosure

Receiver EngagementMechanism Operator”s Handle

SATS is defining a Common Instrument Signal Bus (CISB) that

can be matriced to other instruments through physical pin map-

ping and/or switching. Through common output ports (pin maps

of instrument front panels), categories of instruments having com-

mon pin maps can be interchanged, reconfigured/routed through

CISB access to any number of points defined by the system inte-

grator without dramatic modification of the hardware.

This Instrument Signal Bus architecture can be iterated between

each chassis, as shown in Figure 4 thereby extending/expanding

the routing possibilities to either the UUT or other instrumenta-

tion. This layering process provides multiple benefits in reduced

footprints of the hardware, elimination of costly/performance

degrading wiring, and tremendous savings in producing main-

taining and upgrading the product. Instrument selection, place-

ment, and functionality become more transparent to the system

controller and/or Test Program Set (TPS) software operation, that

in turn makes it more migratable between test systems.

IX. TEST SYSTEM INTERFACE TO THE UNIT-UNDER-TEST

The IEEE P1505 Receiver Fixture Interface (RFI) Standard,

shown in Figure 15, has been selected for the SATS Standard. It

provides a common mechanical quick disconnect for connecting

large numbers of electrical signals (digital, analog, RF, power,

etc.), between source and recipient of those connections. (a.k.a.

General Purpose Interface, Mass Connect Interface, Test Inter-

face System, Test Adapter, Interface Device, Interface Test

Adapter). The associated Fixture is thought of as the “buffer”

between the Unit-Under-Test (UUT) and Test System RFI Re-

ceiver. Its UUT-specific role being to translate standard I/O sig-

nal routing for as many as 5,600 pins offered at the Receiver to a

wiring interface that directly connects to the UUT. These UUT

interfaces can represent cable connectors, direct plug-in (printed

circuit board edge connectors), sensor monitoring, or manual feed-

back from the test technician.

X VXI/VME/PXI LEGACY SUPPORT

A. Technology Transition

SATS recognizes that solutions of the magnitude discussed will

not occur overnight and transitional support must be implemented

into the design of SATS to grandfather existing systems into the

architecture. This will permit integrators and users to apply ex-

isting VXI instruments and cabling where direct interfaces do

not exist. Transition extensions (translators) of the SATS archi-

tecture allows existing VXI/PXI front panels or cabling to couple

with follow-on standard printed wiring panels connectors. When

direct integration is possible (VXI/PXI front panels evolve to stan-

dard SATS), transition assemblies can be eliminated and the me-

chanical structure directly coupled with its mating module inter-

face. The Augmentation bay, shown in Figure 16, reflects inte-

gration of translator modules with VXI, PXI Modules standards

(conversion to cableless interconnect).

Figure 16. Hybrid Legacy/SATS Configuration

B. Hybrid SATS Standard ImplementationHybrid SATS Standard implementation will apply current VXI

Consortium and VXIplug&play Specifications into SATS wiring

panels and module packaging integration. The non-defined front

panels are resolved by applying the DIN 43355 Connector to a

transition device that converts current VXI/PXI front panels to

common SATS Carrier Module I/O Specifications. Power may

be alternatively distributed from the Power Module front panel

interfaces via the Augmentation Bay printed wiring panel, to ei-

ther the Augmentation Bay, RFI system or UUT. These options

permit more efficient use of the available power and support as

backup in event module failure. Suppliers are expected to apply

features that reconfigure or program outputs to meet multi-appli-

cations without augmenting resources. In standardizing on the

IEC 917 DIN 43355 Connector, illustrated in Figure 5, through-

out the SATS internal interfaces, common footprints and pin char-

acteristics can be defined.

Figure 15. IEEE P1505 Receiver Fixture Interface (RFI) Design

SATS Power Module

VXI Controller/Instrument

Module

Connector TransistionModule

Hybrid SATSPower/VXI Chassis

Cooling Module Cooling Module

RFI ReceiverSubsystem

PXI/

VME/

SATS IPMModules

OperatorDisplay

Interface

Hybrid VME/PXI/SATSB-Size/9U Bay Chassis

XI. SATS ATE APPLICATION

The Structured Architecture Test System (SATS) is the culmina-

tion of several years of study by both the government and indus-

try to define a more structured approach to integrating VXI, PXI

VME, IEC, RFI subset standards into a cohesive system solu-

tion. This is done primarily to preserve test program rehostabil-

ity, equipment reconfigurability, and technology evolution require-

ments. It further reduces customization/ augmentation, test pro-

gram development, and interface costs, while increasing compe-

tition.

Fundamental design is being developed through industry partici-

pation to assure product viability and long-term commitments to

the standard. Several current government ATE programs such

as RTCASS, ARGCS, JSF, and B1-B could benefit from the

standard’s process. SATS implementation, as illustrated in Fig-

ure 17, offers a fault-tolerant test system structure, that shares

35% of the assets, matrices test signal/power bus I/O to dual multi-

port RFI, and reduces overall costs, build process and footprint

by 50% of current ATE VXI/PXI/19” instrument hybrid system

solutions. The SATS program is actively seeking integrators

and instrument suppliers to refine and implement the specifica-

tion.Figure 17. SATS RTCASS, ARGCS, B1-B Implementation

AUTHORS BIOGRAPHY

Michael J. Stora is President and CEO of Modular Integration Tech-

nologies, Inc. of Boonton NJ, (973)299-8321/ E-Mail:

mjs@modintec.com. A member of the IEEE, VXIplug&play, VXIbus

Consortium, current Chairman of the IEEE P1505, Receiver Fixture

Interface Standards effort, past chairman of the IEEE 1149 Test Bus

Standard, and past chairman functions of the AUTOTESTCON efforts.

A Business Manager by education and past positions with Emerson

Electric, Raytheon, Harris, GenRad, and MAC Panel, Mike has been

directly involved with test technology for 25 years, a holder of four

patents, and developer of several industry test products.

David Droste is a BSEE graduate of the University of Evansville with

27 year career in military testing projects. In his twelve year tenure

with the Government David led a team which produced over 100 AN/

USM-465 test program sets. At Harris for 11 years, he was responsible

for the development of F/A-18 TPSs and MIL-STD-2165 testability

design efforts supporting Boeing on the P-3 ASW aircraft. Dave cur-

rently leads a team at PEI Electronics Inc., Huntsville Alabama, on the

Re-Entry System Test Set (RSTS) Program for the Minuteman III,

MK12/12A Re-Entry Systems. Mr. Droste also serves as Co-Chair for

the IEEE-P1552, Structured Architecture for Test Systems (SATS) and

Secretary for IEEE’s SCC20 Test and Diagnosis for Electronic Sys-

tems Standards Committee.

REFERENCES

[1] Electrical, Electronic Engineers (IEEE) Standards Organization; Piscat-

away, NJ; URL:http://standards.ieee.org.

[2] VMEbus; VITA-Scottsdale, AZ; URL:http://vita.com; ANSI- Washington,

DC; URL:http://ansi.org.

[3] VXIbus; San Diego, CA; URL:http://vxi.org

[4] PCIbus; Wakefield, MA; URL:http://picmg.com

[5] PXIbus; Austin, TX; URL:http://vxipnp.org.

[6] CompactPCI; Wakefield, MA; URL:http://picmg.com

[7] Joint Service Automatic Test Systems Research and Development Inte-

grated Product Team (ARI), govt/industry Critical Interfaces Working

Group; USAF-CIWG Contract Report;, Washington, DC, 6/1/98.

[8] IEEE SSC20 Technical Committee for the IEEE P1226.X, VXI Instru-

ment Control; Piscataway, NJ; URL:http://standards.ieee.org.

[9] IEEE I& M Technical Committee for the IEEE 488, VXI Instrument Con-

trol; Piscataway, NJ; URL:http://standards.ieee.org.

[10] IEEE P1505 I& M Technical Committee for the Receiver Fixture Inter-

face; Piscataway, NJ; URL:http://standards.ieee.org.

[11] VXI Consortium-VXI Hardware Specification 1.4; San Diego, CA;

URL:http://vxi.org.

[12] VXIplug&play Operating Systems and Instrument Drivers, VPP-3/4; Aus-

tin TX; URL:http://vxipnp.org.

[13] EIA Standard, RS-310-C, Racks, Panels and Associated Equipment; EIA-

Arlington, VA; URL:http://eia.org

[14] ANSI, VME/VME-64 Hardware Standard; VITA-Scottsdale, AZ; URL:http:/

/vita.com; ANSI- Washington, DC; URL:http://ansi.org.

[15] IEC 917 (DIN 43355) / IEC 603-2 (DIN 41612) Connector Spec; IEC-

Chicago, IL; URL:http://iec.org; DIN-Berlin Germany; URL:http://

en.din.de.

[16] M-Module Mezzanine Spec-VITA 12; Scottsdale, AZ; URL:http://vita.com.

[17] Eurocard VME/VXI/PCI/PXI Packaging; EIA Standard, 60796-3, 15 Feb

1990, Racks, Panels and Assoc Equipment; EIA-Arlington, VA; URL:http:/

/eia.org

[18] Infiniband Trade Assoc; URL:http://infinibandta.org

[19] Rapid I/O Trade Assoc; URL:http://rapidio.org

[20] PCI Express Trade Assoc; URL:http://pcisig.com

[21] VMEbus: IEC 297-3; IEC-Chicago, IL; URL:http://iec.org

[22] IEEE 1014; Piscataway, NJ; URL:http://standards.ieee.org.

[23] VXIbus IEEE 1155 Eurocard Mechanical Packaging; VXIbus-San Diego,

CA; URL:http://vxi.org; Piscataway, NJ; URL:http://standards.ieee.org.

• Modular/Scaleable Plug&Play CompositeEnvironmentalSealed Chassis for RuggedTransportability/Easy Integration;

• External Heat Exchanger with Sealed Internal Pressurized Cooling SystemProtects AgainstEnvironment Quiet Ops;

• Cableless Modular/Scaleable Plug&Play 3U/6U/9U IPM Module and Wiring Panel Con-struction Offers Easy Mftrg, Maintenance, and Technology Insertion;

• Switched Matrixed Bus Integration Supports Shared Assets and Multi-Port Test InterfaceAccess;

• High Speed Serial Bus Control Supports Point-to-Point Control at a 12GHz Rate;

• Open High Performance Receiver Fixture Interface Offers 2.0 GHz High Speed Digital,FiberOptics, 60GHz Distributed Pin Map, and Direct Cable Access.