analysis of hot-electron reliability and device performance in 80-nm double-gate soi n-mosfet's

1760 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 8, AUGUST 1999

Analysis of Hot-Electron Reliabilityand Device Performance in 80-nm

Double-Gate SOI n-MOSFET’sS. C. Williams, K. W. Kim, M. A. Littlejohn, and W. C. Holton

Abstract—In this paper, we employ a comprehensive MonteCarlo-based simulation method to model hot-electron injection, topredict induced device degradation, and to simulate and comparethe performance of two double-gate fully depleted silicon-on-insulator n-MOSFET’s (one with a lightly-doped channel andone with a heavily-doped channel) and a similar lightly-dopedsingle-gate design. All three designs have an effective chan-nel length of 80 nm and a silicon layer thickness of 25 nm.Monte Carlo simulations predict a spatial retardation betweenthe locations of peak hot-electron injection into the front andback oxides. Since the observed shift is a significant portionof the channel length, the retardation effect greatly influencesinduced degradation in otherwise well-designed SOI devices. Thiseffect may signal an important consideration for sub-100-nmdesign strategy. Simulations were also conducted to comparetransistor performance against a key figure of merit. Evaluationof reliability and performance results indicate that the double-gate design with a lightly doped channel offers the best tradeoff inimmunity to hot-electron-induced degradation and performance.

I. INTRODUCTION

T HROUGH innovative design, silicon technology contin-ues to demonstrate potential for deep submicron low-

power MOSFET applications. In this regime, the fully depletedsilicon-on-insulator (FD SOI) MOSFET offers impressive ad-vantages over bulk counterparts, including increased drain cur-rent, improved subthreshold slope, high transconductance, andimmunity to short-channel effects. Advanced FD SOI devices,such as the double-gate (DSOI) design, have demonstratedeven greater performance than single-gate (SSOI) devices(e.g., nearly ideal subthreshold slope and greater drain current).Attempts to control threshold voltage in DSOI designs have ledto several gate electrode configurations, including symmetricdesigns [1]–[7] employing the same electrode material forboth gates, and asymmetric [8]–[10] designs having twodifferent gate electrode materials. Extensive theoretical andexperimental investigation into device performance has beenconducted for both symmetric and asymmetric DSOI de-vices, and the viability of DSOI for sub-100-nm operationhas been established [3]. However, to our knowledge nopublished investigations into hot-electron reliability or direct

Manuscript received December 28, 1998; revised April 14, 1999. This workwas supported in part by the Office of Naval Research and the Center forAdvanced Electronic Materials Processing established at North Carolina StateUniversity by the National Science Foundation. The review of this paper wasarranged by Editor J. N. Hollenhorst.

The authors are with the Department of Electrical and Computer Engineer-ing, North Carolina State University, Raleigh, NC 27695-7911 USA.

Publisher Item Identifier S 0018-9383(99)06107-9.

comparisons of transistor performance between competingdouble-gate designs have been conducted.

In this paper, we employ a comprehensive Monte Carlo-based simulation method to compare the hot-electron-induceddevice degradation and transistor performance for two com-peting DSOI designs (DSOI-1 and DSOI-2) and a comparablesingle-gate design (SSOI). All three designs have an effectivechannel length of 80 nm. Simulations indicate a shift inlocations of peak hot-electron injection (HEI) into front andback oxides. In DSOI-1, the location of peak HEI into theback oxide is shifted beyond the position of peak HEI intothe front oxide by about 9% of . In SSOI, the oppositeresult is seen; that is, the position of peak HEI into the frontoxide is spatially retarded beyond the location of peak HEIinto the back oxide by about the same distance. In contrastto DSOI-1 and SSOI, the peaks in HEI for DSOI-2 are bothlocated at the same point along the channel; however, thesepeaks are displaced beyond the location of the first HEI peaksfor the other two designs. As a result of this phenomena,the DSOI-2 design is predicted to experience much less hot-electron-induced degradation of linear drain current than eitherof the other two designs. In contrast, when the three devicesare simulated in a ring oscillator circuit and evaluated againsta key figure of merit, DSOI-2 demonstrates somewhat worseperformance than the SSOI design, but greater performancethan DSOI-1.

II. DEVICE CONFIGURATIONS

As shown in Fig. 1, all three 80-nm SOI designs (DSOI-1,DSOI-2, and SSOI) used in this study have a four-layer devicestructure with a 4-nm front gate oxide, a 25-nm uniformly-doped silicon layer, a buried oxide thickness of 100 nm, anda thick p-type substrate. The SSOI device [Fig. 1(a)] employsa single front gate with midgap workfunction eV,and a light channel doping of cm . The deviceconfigurations for the two double-gate designs (DSOI-1 andDSOI-2) shown in Fig. 1(b) are identical to the single-gatedevice (SSOI), except for a second gate contact located withinthe buried oxide 4 nm beneath the silicon layer interface. Notethat the back gate is the the same length as the front gate.The DSOI-1 design has a npolysilicon front gate and a ppolysilicon back gate, and a heavily doped channel (cm ). In contrast, DSOI-2 has a midgap workfunction

eV for both front and back gates, and a light channeldoping of cm . Gate voltage is applied to both

0018–9383/99$10.00 1999 IEEE

WILLIAMS et al.: ANALYSIS OF HOT-ELECTRON RELIABILITY 1761

(a) (b)

Fig. 1. Schematic cross section of the three 80-nm SOIn-MOSFET designs. (a) and (b) show the cross sections for single-gate (SSOI) and double-gate(DSOI-1 and DSOI-2) designs, respectively. The source(VS), gate(VG), drain (VD) and substrate(VSUB) voltages are shown in each cross section. Notethat in (b) for the double-gate designs, the same gate voltage is applied to both front and back gates.

Fig. 2. Schematic for a comprehensive simulation method highlighting theessential components.

front and back gates in DSOI-1 and DSOI-2, but only to thefront gate in SSOI. As a result, the inversion layer in DSOI-1 and SSOI forms at the front interface, while for DSOI-2,inversion layers are activated at both surfaces. In all threedevices, the threshold voltage is 0.3 V (at V), andthe source and substrate contacts are at ground potential.

III. SIMULATION METHOD

For a comprehensive study, the simulation approach il-lustrated in Fig. 2 is used. The energy-balance-based TMAMEDICI device simulator [11] provides baseline electricalperformance for subsequent determination of hot-electron-induced device degradation, as well as initial parameter es-timates (e.g., initial electric field distributions, carrier concen-trations, etc.) for the self-consistent Monte Carlo simulator.In addition, a mixed mode circuit analysis module withinMEDICI is used to predict average gate delay times when thethree devices are used as switching FET’s in a ring oscillator.

For all energy-balance simulations, both field [12] and doping-dependent mobility models [12], [13] are selected, and theeffects of surface scattering on electron mobility due to thevertical electric field [14], [15] are also incorporated.

The Monte Carlo simulator is specifically adapted to modelhot-carrier transport in deep submicron devices under low-voltage bias [16], [17]. Key features of the Monte Carlo modelinclude a realistic silicon band structure for the two lowestconduction bands, and a two-dimensional Poisson solver that isrecalculated every 0.06 fs to provide self-consistent, dynamicelectric field distributions. Image force effects are accountedfor by varying the local barrier height along the oxide inter-faces as a function of the vertical electric field component.All relevant scattering mechanisms are considered, includingelectron-electron (e-e), acoustic and intervalley phonon, andionized impurity interactions, as well as impact ionizationand interface scattering. To provide details of the high-energycomponent of the electron energy distributions, the simulatorincorporates an enhanced particle statistics algorithm. Refer-ence [16] provides an extended description of the Monte Carlosimulator.

IV. RESULTS AND DISCUSSION

A. Hot-Electron Injection and Reliability

All three designs are stressed at Vand V. The gate voltage is near conditions forworst-case device degradation [18], while the drain voltage isnear expected operating conditions that are low enough forparasitic bipolar action to be quite small [19]. As a result, hot-hole injection is not expected to influence the overall devicedegradation behavior. The spatial distributions of hot-electroninjection (HEI) rates into both front and back oxides for DSOI-1, DSOI-2, and SSOI under the applied bias conditions areshown in Fig. 3. Simulations show that, for DSOI-1, the peakhot-electron injection rate into the front oxide is almost two


(a) (b) (c)

Fig. 3. Simulated hot-electron injection rates into both front (solid) and back (dotted) oxides as a function of distance along the channel. (a), (b),and (c)show injection distributions for DSOI-1, DSOI-2, and SSOI, respectively, calibrated to the same vertical scale. Device bias conditions areVD = 1:2 V andVG � VTH = 0:3 V, which corresponds to the maximum stress voltage condition. The metallurgical drain junction is located at 243 nm for DSOI-1, andat 234 nm for DSOI-2 and SSOI.The results in this figure are obtained from self-consistent Monte Carlo simulations.

(a) (b)

Fig. 4. Simulated (a) vertical and (b) horizontal components of the electric field near the front oxide interface (Eyf and Exf , respectively) versusdistance along the channel. Here, a positive value ofEyf is attractive to channel electrons.The results in this figure are obtained from self-consistentMonte Carlo simulations.

times greater than the peak HEI rate into the back oxide[Fig. 3(a)]. Moreover, the location of peak HEI into the backoxide is shifted beyond the position of peak HEI into the frontoxide by about 7 nm, which is a significant 9% of . TheSSOI device demonstrates the converse result to DSOI-1 asshown in Fig. 3(c); that is, the peak HEI rate into the frontoxide is less than the peak rate into the back oxide. Also, theposition of peak HEI into the front oxide is spatially retardedbeyond the location of peak HEI into the back oxide by aboutthe same distance as predicted for DSOI-1. Note that the peakHEI rate into the front oxide of DSOI-1 is significantly greaterthan the peak HEI rate into the back oxide for SSOI. Incontrast to the results for DSOI-1 and SSOI, the DSOI-2 designdemonstrates nearly equal peak HEI values into both oxides.The peaks are located at the same point along the channel, butbeyond the location of the first HEI peaks in DSOI-1 or SSOI.In addition, the values of peak HEI in DSOI-2 are less thanthe peak HEI value into the back oxide of SSOI. The results inFig. 3 may have important implications for sub-100-nm designstrategy since both the magnitude and the location of HEI areknown to influence induced device degradation.

The shift in locations of peak HEI into the front andback oxides is primarily attributable to the electric fielddistributions and the resulting channel carrier densities nearthe oxide interfaces. Fig. 4 provides the vertical (-directed)and horizontal (-directed) components of the electric fieldnear the front interface (denoted as and , respectively)for the three designs. Corresponding plots for the electric fieldcomponents near the back interface (denoted asandare shown in Fig. 5. For the DSOI-1 device, the contours ofelectron concentration in the channel and drain regions (shownin Fig. 6) are largely determined by and . As can beseen from Fig. 6, the conducting channel of this device isformed primarily at the front oxide interface and penetratesonly about 5 nm into the silicon layer due to the stronglyattractive nature of (up to about the 220-nm location inthe -direction). As the channel electrons drift into the drainregion, both and exert a force that directs channelcarriers away from the oxide interfaces, and the electrons beginto spread somewhat toward the back oxide interface. However,since is significantly more repulsive than in DSOI-1,channel electrons remain closer to the front oxide interface in


(a) (b)

Fig. 5. Simulated (a) vertical and (b) horizontal components of the electric field near the back oxide interface (Eyb andExb, respectively) versus distance alongthe channel. Here, a negative value ofEyb is attractive to channel electrons. The results in this figure are obtained from self-consistent Monte Carlo simulations.

Fig. 6. Simulated contours of electron concentration in the DSOI-1 design, obtained from energy-balance-based simulations. Concentrations in this figurerange from1� 10

17 cm�3 to 5� 1018 cm�3 in increments of1� 10

17 cm�3; darker shading represents regions of higher concentration. The locationsof peak horizontal electric field, peak concentration of high-energy electrons (with energies greater than 1.2eV), and peak HEI, into both front and backoxides, are denoted by A and D, B and E, and C and F, respectively. Note that the distance between A and B is 6 nm; between B and C, 5 nm;between D and E, 12 nm; between E and F, 3.5 nm.

this portion of the device. Near the front oxide, channel carriersare accelerated by the large , and the average energyof the channel electrons increases simultaneously. As thesecarriers travel beyond the location of peak (location A),the local electron density rapidly increases and e-e interactionsbecome significant [17] before the electron energy distributionis able to cool (i.e., while the average energy of the electronenergy distribution is still quite high). Therefore, the channelelectrons interact with the local carrier density fast enoughvia e-e scattering to generate a relatively large population ofcarriers with energies greater than the applied drain bias (1.2V) at location B approximately 6 nm beyond location A. Thechannel carriers travel about 5 nm further along the channelbefore those carriers with energies greater than the local oxidebarrier height inject into the front oxide, resulting in a highrate of peak HEI at location C.

Near the back oxide in DSOI-1, electrons that spread fromthe front channel are accelerated by , and the averageelectron energy increases simultaneously. However, unlike for

the electrons near the front oxide interface, the local carrierdensity near the back oxide interface remains low until muchfurther into the drain due to the highly repulsive nature of

. As a result, the electron energy distribution has almostcompletely thermalized (i.e., the average energy of the electronenergy distribution is near ) before the local electrondensity becomes high enough for e-e interactions to becomesignificant. A smaller population of high-energy electrons(with energies greater than 1.2 eV) is therefore generatedat location E approximately 12.5 nm beyond the peak(location D), about two times the distance between locationsB and A. The back channel carriers traverse a short distanceof about 3.5 nm beyond location E before those electronswith energies greater than the local oxide barrier height injectinto the back oxide. The peak rate of HEI into the backoxide (location F) is correspondingly lower than the peakHEI rate into the front oxide (location C) because of thesmaller number of high-energy carriers generated near the backinterface. Moreover, location F is displaced approximately 7


Fig. 7. Simulated contours of electron concentration in the SSOI design, obtained from energy-balance-based simulations. The range of concentrations inthis figure is the same as in Fig. 6. The locations of peak horizontal electric field, peak concentration of high-energy electrons (with energies greater than1.2eV), and peak HEI, into both front and back oxides, are denoted by A and D, B and E, and C and F, respectively. Note that the distance between Aand B is 11 nm; between B and C, 5 nm; between D and E, 7 nm; between E and F, 4 nm.

Fig. 8. Simulated contours of electron concentration in the DSOI-2 design, obtained from energy-balance-based simulations. The range of concentrations inthis figure is the same as in Fig. 6. The locations of peak horizontal electric field, peak concentration of high-energy electrons (with energies greater than1.2 eV), and peak HEI, into both front and back oxides, are denoted by A and D, B and E, and C and F, respectively. Note that the distances betweenA and B, and D and E, are 14.5 nm; between B and C, and E and F, 5.5 nm.

nm beyond location C, primarily due to the locations nearthe oxide interfaces where the local electron density becomeshigh enough for significant e-e interactions to occur, therebygenerating high-energy electrons for injection into the oxide.

Similar analyses for SSOI and DSOI-2 explain the trendsin HEI observed in Fig. 3 for these devices. For the SSOIand DSOI-2 designs, Figs. 7 and 8, respectively, show thecontours of electron concentration in the channel and drainregions, as well as the locations of 1) peak and ,2) peak concentration of high-energy electrons (with energiesgreater than 1.2 eV) near the front and back oxides, and 3) peakHEI rates into both the front and back oxides. These locationsare denoted in both figures by A and D, B and E, and Cand F, respectively. In contrast to the DSOI-1 design, Fig. 7demonstrates that as channel carriers in SSOI drift into thedrain region, they are concentrated nearer the back oxide dueto the nature of and in this device. Correspondingly,near the back oxide, the average energy of the electron energydistribution is still quite high as the local electron density

increases; near the front oxide interface, the electron energydistribution is almost thermalized before the local carrierconcentration increases. A larger population of high-energycarriers is therefore generated at the back interface (locationE) than at the front interface (location B), and subsequentlythe peak HEI rate into the back oxide is greater than the peakHEI rate into the front oxide. Due to the locations near theoxide interfaces where carrier concentrations are large enoughto generate significant e-e interactions, location C is displacedabout 7 nm beyond location F. Moreover, carriers near theback oxide in SSOI are accelerated by , which has asmall peak value when compared to in DSOI-1. Sincethe amount of electron injection is strongly correlated withthe strength of the electric field [19], the peak HEI value intothe back oxide for SSOI is expected to be small relative tothe value of peak HEI into the front oxide for DSOI-1. Thiseffect is observed when comparing Fig. 3(a) and (c).

For the DSOI-2 design, the symmetry of the vertical electricfield results in nearly identical contours of electron concentra-


Fig. 9. Simulated degradation of linear drain current (obtained atVG = 1:2

V, VD = 0:05 V) versus stress time.

tion near the front and back interfaces, as shown in Fig. 8.The horizontal electric field components are also symmetric.As a result, the peak HEI values into both oxides are roughlyequal and are located at nearly the same point along thechannel, but beyond the location of the first HEI peaks inDSOI-1 or SSOI. Note that the distance between location Band location A in DSOI-2 is about 3.5 nm longer than inSSOI. However, since the peak value of is slightly largerin DSOI-2 when compared with SSOI, the average energy ofthe channel electrons is about the same at location B in bothdevices. Correspondingly, the peak values of HEI into the frontoxides for DSOI-2 and SSOI are nearly equivalent.

In order to study the impact of this HEI behavior on deviceperformance, hot-electron-induced interface states are incor-porated into MEDICI at both oxide interfaces to characterizeinduced device degradation of linear drain current versusstress time. As shown in Fig. 9, DSOI-1 and SSOI experiencecomparable device degradation which is significantly higherthan that predicted for DSOI-2. Since the location of interfacestate damage has a strong influence on device degradationbehavior [20], the positions of peak HEI in each device mustbe carefully considered. In DSOI-1 and SSOI, a large portionof interface state damage is located over the channel, wherecharged states induce Coulombic scattering and produce thegreatest deteriorating effects. In DSOI-2, most of the interfacestates are located over the drain. Since charge in this regionhas the least impact on device performance due to screening,DSOI-2 experiences substantially less degradation than theother two designs. The trends in Fig. 9 clearly demonstratethat differences in the locations of peak HEI at front andback oxides observed in the DSOI-1 and SSOI designs sig-nificantly degrade device reliability in otherwise well-designedstructures. Therefore, this phenomena may signal an importantconsideration for sub-100-nm design strategies.

B. Performance

The circuit analysis module of the MEDICI device simulatoris used to model the performance of the DSOI-1, DSOI-2, andSSOI n-MOSFET’s in a basic test circuit. Each of the three

Fig. 10. Schematic for the nine-stage resistively-loaded ring oscillator usedto evaluate device performance. Each of the three designs (DSOI-1, DSOI-2,and SSOI) is usedas the switching FET. The supply voltageVDD is maintainedat a constant 1.2 V, and the load resistancesRL are 20mm. The transistorwidths for this simulation are 10�m.

SOI designs are used as a switching FET in a resistively-loadedinverter; the inverters are connected to form a nine-stage ringoscillator, shown in Fig. 10. For all mixed mode simulationsof the three oscillator circuits (DSOI-1, DSOI-2, and SSOI),the supply voltage is 1.2 V, the resistive loads are 20

mm, and the transistor widths are 10m. Since the numberof stages in the oscillator circuit is not a prime number (inthis case due to limitations of the circuit analysis module),care has been taken to insure that the observed waveforms arenot a product of higher-order harmonics.

The performance of the ring oscillator circuits are evaluatedagainst average gate delay time as a figure of merit. Theaverage gate delay time determines the maximum clockfrequency at which the inverter can be driven; a small delaytime equates to a high maximum frequency. To be certain thatthe performance comparison between designs is a product onlyof intrinsic device properties, we briefly examine the effect ofthe resistive load value on . The average gate delay time ofthe ring oscillator circuit is directly related to the rise and falltimes of one of the inverter stages. The rise time is proportionalto , where is the average capacitance seen atthe inverter output node. Therefore, one value of for allthree oscillator circuits insures that the rise times are a productonly of intrinsic device capacitances, and not a product of.Secondly, the fall time is proportional to ,where is the averaged equivalent internal resistance ofthe MOSFET. If the load resistance is large relative to theequivalent internal resistance, then the fall time is dependentsolely upon the intrinsic device resistance and capacitances. Adetailed analysis verifies that the value of used in this studyis large enough to meet this criteria. As a result, the choice ofa sufficiently large, single value of load resistance for all threeoscillator circuits insures that the performance results representa fair and direct comparison between the three designs.

For brevity, the simulated waveform of the nine-stageresistively-loaded ring oscillator is shown in Fig. 11 for DSOI-1 only. To calculate , the time period to complete onefull oscillation is averaged over the rise and fall times, anddivided by two times the number of stages in the ring. Thegate delay times for DSOI-2 and SSOI are obtained using the


Fig. 11. Simulated DSOI-1 transient response used to determine the averagegate delay timetD of a nine-stage resistively-loaded ring oscillator, obtainedfrom the mixed mode circuit analysis module within MEDICI. To calculatetD , the time period to complete one full oscillation is averaged over the riseand fall times, and divided by two times the number of stages in the ring.

same method applied to DSOI-1. The average gate delay timesare approximately 9 ps/stage for SSOI, 14 ps/stage for DSOI-2, and 19 ps/stage for DSOI-1. Clearly, SSOI shows a lower

than the other two designs, indicating a somewhat largerperformance advantage over the other devices.

The performance results may be understood by exam-ining the trends in unity-gain frequency, ,as determined by the total gate capacitance and themaximum value of long channel transconductance foreach design. The SSOI design has the lowest gate capacitance,while DSOI-1 and DSOI-2 have about and the gatecapacitance of SSOI, respectively. On the other hand, theDSOI-1 device has the smallest value of , DSOI-2 has thelargest transconductance value, and SSOI falls about halfwaybetween. Based upon these intrinsic device characteristics, theSSOI design demonstrates the highest, followed in order byDSOI-2 and DSOI-1. The results of the unity-gain frequencyanalysis correlate directly with the trends in performancepredicted by the ring oscillator circuit simulations.

V. CONCLUSION

In this paper, trends for hot-electron injection into both frontand back oxides are investigated for two double-gate SOI de-signs and a comparable single-gate SOI device. Furthermore,all three designs are evaluated for resulting hot-electron-induced device degradation and inverter performance usinga comprehensive simulation method. Monte Carlo simulationsindicate a difference in the locations of peak HEI into thefront and back oxides for these three designs that is primarilyattributable to the electric field distributions as well as theextremely high average (-directed) velocities of the chan-nel carriers. This HEI behavior significantly degrades devicereliability in the DSOI-1 and SSOI devices versus the DSOI-2 design. However, ring oscillator circuit simulations revealthat the DSOI-2 design demonstrates a larger delay time (lessperformance) than SSOI, but a smaller delay time than DSOI-

1. Therefore, when compared to DSOI-1 and SSOI, the 80-nmDSOI-2 design offers the best tradeoff in immunity to hot-electron-induced degradation and circuit performance.

ACKNOWLEDGMENT

The authors would like to thank W. Liu for his usefuldiscussions on the topic of MOSFET performance modeling.

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S. C. Williams, photograph and biography not available at the time ofpublication.


K. W. Kim , photograph and biography not available at the time of publication.

M. A. Littlejohn , photograph and biography not available at the time ofpublication.

W. C. Holton, photograph and biography not available at the time ofpublication.

analysis of hot-electron reliability and device performance in 80-nm double-gate soi n-mosfet's

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