analysis and pcb design of class d inverter for wireless

IEEJ Journal of Industry ApplicationsVol.4 No.6 pp.703–713 DOI: 10.1541/ieejjia.4.703

Paper

Analysis and PCB Design of Class D Inverterfor Wireless Power Transfer Systems Operating at 13.56 MHz

Nguyen Kien Trung∗a)Student Member, Takuya Ogata∗ Non-member

Shinichi Tanaka∗ Member, Kan Akatsu∗ Member

(Manuscript received Nov. 5, 2014, revised April 4, 2015)

This paper presents the analysis and PCB design of a class D inverter for wireless power transfer systems operatingat 13.56 MHz. The effects of parasitic inductance on the switching performance of MOSFETs, transfer efficiency ofWPT systems, and power loss are analyzed. At high frequencies, the print circuit board (PCB) design is very criticalbecause it control the parasitic elements on the circuit. This study proposes an improved PCB design that can providea 23.4% decrease in parasitic inductance over the conventional PCB design.

Keywords: class D inverter, high frequency inverter, PCB design, wireless power transfer (WPT)

1. Introduction

Recently, wireless power transfer (WPT) systems havebeen proposed for many applications but the application areais being limited due to low power level and short distanceof transfer. There are studies which have been successfulon transferring power with the distance within 1–2 meter asshown in (1), (2), but the power level is lower than 100 W.And in the other side, there are also studies which designWPT systems at high power level but the operating frequencyis low as shown in (3)–(5). Therefore, due to the low operat-ing frequency, the transfer distance is short and the size of thecoil is large, it is difficult to meet the recent real demands bythese techniques.

Our research expands the applications of WPT systems tosuch as wireless vehicle charging systems with vehicle run-ning or industrial applications. Two important things are totransfer high power over large air gap and to make the WPTsystem in a compact size. Therefore, we design the WPTsystems which operate at high power, high frequency andachieve high efficiency. In WPT systems, the transmittingcoil is fed up by a high frequency inverter. The performanceof WPT systems is heavily dependent on the performance ofthe inverter. This paper presents the analysis and PCB designof a class D resonant inverter operating at 13.56 MHz feedingup to the WPT systems. The final target is to design a 10 kWWPT system to meet with the running vehicle charging sys-tem by using multiphase resonant inverter which is built baseon many class D resonant inverters.

At high frequency, the inverter is strongly affected by para-sitic elements. The effects of parasitic elements on MOSFETswitching characteristics are widely investigated as shown

a) Correspondence to: Nguyen Kien Trung. E-mail: [email protected]∗ Graduate School of Engineering and Science, Shibaura Institute

of Technology3-8-5, Toyosu, Koto-ku, Tokyo 135-8548, Japan

in (6)–(11). All of previous studies showed that the switch-ing performance of MOSFET will be worse at high frequencydue to the influence of parasitic elements. As the switchingpower loss increases, the voltage stress and voltage slew ratealso increase. Furthermore, the circuit might be unstable dueto the oscillation in the gate driver circuit (6). Even though theeffects of parasitic elements are carefully investigated but theinvestigating frequency is around 1 MHz (6). Since the ringingfrequency is much higher than the switching frequency, theringing in power loop will be damped before the next switch-ing period, so the inverter is stable. However, at 13.56 MHz,the ringing frequency is near to switching frequency, the in-verter will be more unstable because the ringing in powerloop is very difficult to damp. Furthermore at high frequencyand high power condition, since the current and voltage arehigh and ringing, the effect of parasitic elements will be muchheavier. The power switches can be easily destroyed due tovery high peak voltage, very high slew rate voltage du/dt orvery high slew rate current di/dt.

At high frequency, PCB layout design is always very crit-ical. The effect of parasitic elements can be minimized byoptimizing the PCB layout design. A lot of techniques andstudies have been already discussing about this problem (12) (13).But almost of them design the PCB layout at low power levelwith very small device and the operating frequency is around1 MHz. When using high power device, PCB design is diffi-cult to minimize parasitic inductance due to the size of deviceand the heat sink of device. Furthermore, at 13.56 MHz, themutual effect is stronger. Therefore the direction of currentin the circuit is critical in PCB design to reduce parasitic in-ductance.

This paper investigates the effect of parasitic inductanceon the switching performance of MOSFET in half-bridgeclass D inverter at 13.56 MHz. The high power MOSFETDRF1400 is used to design the inverter. A PCB layout de-sign is proposed to obtain low parasitic inductance. Allof PCB layout designs are simulated and analyzed by a

c© 2015 The Institute of Electrical Engineers of Japan. 703

PCB Design of a 13.56 MHz Class D Inverter（Nguyen Kien Trung et al.）

full-wave electro-magnetic (EM) simulations using Sonnetem software. In the simulation and experiment results, theringing frequencies, parasitic inductances, overshoot voltageare compared to the conventional design. Our optimal PCBlayout can provide a 23.4% decrease in parasitic inductanceover the conventional PCB design.

2. Effect of Parasitic Elements

The circuit diagram of an inverter included of parasitic el-ements is shown in Fig. 1. Two MOSFETs V1 and V2 areconnected in a half-bridge topology. The considered para-sitic elements of the MOSFET include gate-source capaci-tance Cgs1,2, gate-drain capacitance Cgd1,2, drain-source ca-pacitance Cds1,2, common source inductance Ls1,2, and draininductance Ld1,3. The internal gate drive resistance (which isusually around 1 ohm for high-frequency power MOSFETs)and inductance are merged into the external gate drive re-sistance Rg1,2 and inductance Lg1,2 as they are connected inseries and play the same role in the circuit. All stray induc-tances in the power loop and external to the MOSFET arelumped and represented by Ld2, Ld4, Ld5, Ld6 and Ld7. Ld6

and Ld7 are stray inductances of connection wire from DCsource to the MOSFETs of inverter. Ld2 and Ld3 are strayinductances of connection wire among two MOSFETs. Res-onant load in this case is the coupling system which is madeby resonant transmitting coil and resonant receiving side ofWPT system. Figure 1 includes the equivalent circuit of cou-pling system which is inside the dash line loop.

The parasitic inductances which are serially connectedwith the MOSFET in power loop impact the switching speedand the peak drain to source voltage of device. During theswitching transition, the voltage across the parasitic induc-tance Lp can be expressed as follow:

Vp = LpdiDdt· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (1)

Where Lp =∑7

i=1 Ldi +∑2

i=1 Lsi

During the turn on transition of MOSFET, the drain currentis rising. Therefore, across the parasitic inductances will gen-erate a positive voltage. This voltage will reduce the effec-tive voltage across the MOSFET. Consequently, the switch-ing power loss is reduced and a negative voltage spike is ap-peared. During the turn off transition, the drain current isfalling and a negative diD/dt across the parasitic inductancesinduce a negative voltage, increasing the effective voltageacross the MOSFET, inducing a positive voltage spike andincreasing switching power loss (12). The results in (12) showthat the power loss significantly increase when parasitic in-ductance in power loop increase at high operating frequency.

To remove effects of parasitic inductance Ld6 and Ld7

which are created by connection wire between DC source andinverter, input capacitors Cin and input inductor filter Lin areadded as shown in Fig. 2. These capacitors and inductor actas an input filter which provide a path for high-frequency os-cillations bypassing and prevent the high frequency currentcomeback to the DC source. Figure 3 presents the voltagewaveform and current waveform across MOSFETs during itsturn-off period. We assume the voltage across input capaci-tor Cin is constant Vin when the input filter is successfully de-signed. At t1, the drain-source voltage reaches its peak value

Fig. 1. Equivalent circuit of class D resonant inverter in-clude of parasitic elements

Fig. 2. Ringing loop in class D, half-bridge inverter

Fig. 3. Turn-off wave forms of MOSFET

while drain current reaches zero. The peak value of drain-source voltage is greater than input voltage value across theinput capacitor due to effecting of parasitic inductances. Af-ter t1, the MOSFET is fully turn-off but the voltage across theoutput capacitor Coss of MOSFET is greater than the voltageacross the input capacitor. Therefore, a ringing loop exits asshown by dash line in Fig. 2.

In this research, we use an integrated MOSFET module

704 IEEJ Journal IA, Vol.4, No.6, 2015


Fig. 4. Equivalent circuit of ringing loop in operating(a) V1: OFF and V2: ON, (b) V1: ON and V2: OFF,(c) Final equivalent circuit

DRF1400 from Microsemi Corporation. This module in-cludes two power MOSFETs in a half bridge topology asshown in Fig. 2. The total equivalent parasitic inductance ofringing loop is given as

Lloop = Lmod + Llin · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · ·(2)

where

Lmod = Ld1 + Ls1 + Ld2 + Ld3 + Ls2 + Ld5 · · · · · · · · (3)

Llin = Ld8 + Ld9 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · (4)

are the parasitic inductances of the MOSFET module and thetrace lines, respectively.

Figure 4(a) and Fig. 4(b) show two equivalent circuits ofringing loop in operating. The power loop is represented bycontinuous line and the ringing loop is represented by dashline. In both of case, the ringing loop is created by self-oscillation of parasitic inductance of ringing loop Lloop andoutput capacitor of MOSFET Cossas shown in Fig. 4(c).

Based on the equivalent circuit in Fig. 4 and with the ini-tial value at t1, the drain-source voltage of low-side MOSFETwhen it turns off is derived as:

vds(t) = Vin +(Vpeak − Vin

)e−

tτd cos (ωrt)

= Vin + vringing · · · · · · · · · · · · · · · · · · · · · · · · · · · · (5)

Where

τd = 2Lloop/Rloop

ωr =

[1/LloopCoss −

(Rloop/2Lloop

)2]1/2

Rloop = RAC + Rds

vringing = Vre− tτd cos (ωrt)

· · · · · · · · · · · (6)

Vin is input voltage across input capacitor Cin. Vpeak is thepeak value of voltage across MOSFET. RAC represents the acand dc resistance of trace line in ringing loop. The ac resis-tance increases as the ringing frequency increases. Rds is the

Table 1. Amplitude of ringing at the end of switchingperiod

resistance of MOSFET when it is in ON state.The amplitude of ringing part reduces base on exponential

function with the time constant τd. Table 1 shows the am-plitude of ringing part at the end of switching period with1 MHz and 13.56 MHz switching frequency.

The results in Table 1 show that at 1 MHz switching fre-quency, almost ringing will be damped at the end of theswitching period by nature way. But at 13.56 MHz, the ring-ing can not be damped by nature way at the end of switch-ing period. And the amplitude of ringing part at the end ofswitching period when the MOSFET change the state de-pends on the parasitic inductance of ringing loop. In thisanalysis, if the parasitic inductance of ringing loop is over10 nH, the ringing is still very high when the MOSFETschange the state. As the result, the voltage across the MOS-FET will be changed based on the ringing waveform. If theringing frequency is low, the switching power loss will bevery high and the output voltage waveform will excite har-monics. The very high switching power loss may damage thepower MOSFETs immediately. Furthermore, the very highfrequency oscillation is fed to the transmitting coil. The con-duction loss in the transmitting coil will be very high due toskin effect.

The ringing current can be calculated as following equa-tion:

iringing(t) = Cossdvds(t)

dt

= −Coss

(Vpeak − Vin

)e−

tτd

[ωr sin (ωrt) +

1τd

cos (ωrt)

]

· · · · · · · · · · · · · · · · · · · · (7)

The drain current of MOSFET can be calculated as follow:When it is in ON state:

iD(t) = iload(t) + iringing(t) · · · · · · · · · · · · · · · · · · · · · · · · (8)

The ringing current is added to the drain current of con-ducting MOSFET which causes increasing conduction lossand peak current on the MOSFET.

The Drain-source voltage of MOSFET when it is ON statecan be expressed as follow:

vds ON(t) = Rds

(iload(t) + iringing(t)

)· · · · · · · · · · · · · · · (9)

The ringing current makes the ringing in the Drain-Sourcevoltage waveform of MOSFET when it is in ON state. Andthe zero voltage switching condition is very difficult to ob-tain.

The output voltage also can be expressed as follow:



vout(t) = vds2(t) + (Ld3 + Ls2 + Ld5)diD2(t)

dt· · · · · · ·(10)

Where vds2(t) and iD2(t) are the drain-source voltage anddrain current of low-side MOSFET V2, respectively.

The common source inductance Ls has been shown to becritical to switching performance because it plays as a feed-back component from power loop to driver loop (6). The volt-age equation of the gate driver loop can be expressed by fol-lowing equation:

Vdriver = Vgs + RgiG + LgdiGdt+ Ls

diDdt· · · · · · · · · · · (11)

Where iD, iG are drain-source current and gate driver cur-rent of MOSFET, respectively. The feedback part of com-mon inductance Ls and drain current iD directly effect tothe switching speed of MOSFET leading to switching powerloss increasing. The value of common source inductance ismainly controlled by the packing technique of the device.

The circuit might be unstable due to the oscillation in gatedriver loop (6). The value of parasitic inductance in gate driverloop Lg depends on the distance between driver IC and MOS-FET. In practical design, such the distance should be de-signed as short as possible.

At 13.56 MHz, the ringing is un-damped. The gate-sourcevoltage of MOSFET will be added a part as following:

Δvgs = −Lsdiringing

dt· · · · · · · · · · · · · · · · · · · · · · · · · · · · · (12)

When the MOSFET is in OFF state, Δvgs can make the MOS-FET re-turn ON and make the circuit unstable.

Furthermore, the ringing current in the power loop alsomake the EMI noise which will effect to the driver circuit.The driver pulse waveform will be effect by noise and theswitching performance of MOSFET will be reduced.

Base on the analysis in this section, we can conclude thatwhen the class D inverter operating at 13.56 MHz, the ring-ing in the circuit is un-damp able by nature way. Therefore,in addition the effects which have been mentioned in previ-ous research, the effects of parasitic inductance may damagethe power switch due to very high switching power loss andunstable due to the effects of ringing current to gate-sourcevoltage of MOSFET. Therefore, minimizing the parasitic in-ductance in the ringing loop is very importance when we de-sign the inverter at 13.56 MHz.

In practical, the totally value of parasitic inductance ofringing loop can be estimated by measuring the ringing fre-quency of drain-source voltage across MOSFET. The estima-tion value can be calculated by Eq. (6).

At high frequency, when using the integrated module, all ofparasitic elements inside the module were optimized. Then,the parasitic inductances controlled by PCB layout designnow becomes a major factor. In the next section we willproposed a new PCB design to minimized the parasitic in-ductance of ringing loop in class D resonant inverter.

3. PCB Layout Design

3.1 Parasitic Inductance As presented in (14), theparasitic inductance of trace line and via in designed PCBcan be calculated as following equation:

Parasitic inductance of trace line

Fig. 5. Conventional PCB layout (Layout 1)

L = 0.002l

[ln

(2lw + t

)+ 0.5 + 0.2235

(w + t

l

)](μH)

· · · · · · · · · · · · · · · · · · (13a)

Where l, t and w is length, thickness and width of the line,respectively which are given in centimeter.

Parasitic inductance of via

L =μ0

2πh

⎡⎢⎢⎢⎢⎢⎣ln⎛⎜⎜⎜⎜⎜⎝h +

√r2 + h2

r

⎞⎟⎟⎟⎟⎟⎠ + 32

(r −√

r2 + h2)⎤⎥⎥⎥⎥⎥⎦ (H)

· · · · · · · · · · · · · · · · · · (13b)

Where h is high and r is radius of via.To reduce the value of parasitic inductance, the PCB trace

line length should be designed as short as possible and thetrace line width should be designed as lager as possible. Theparasitic inductance of via depends on board thickness.

3.2 Conventional PCB Layout Generally, the lam-inate structure is applied in DC side of inverter to realizinglow parasitic inductance by using field self-cancellation ef-fect. However, that method can not be applied for DRF1400MOSFET module due to its physical packing shape. Further-more, at high frequency almost device is packed in surfacemount type. The connections among layers of PCB have touse vias. Therefore, when the field self-cancellation effectcan not be applied, using laminate structure is not optimizeddesign as following analysis.

The conventional PCB layout is presented in Fig. 5 (15). Theinput capacitor is placed on the top layout of PCB board withMOSFET module and in close proximity with Drain pin ofMOSFET module. In the bottom layout, the ground plane isconnected to the top layout by vias. In this design, the ringingloop travels through two physical loops. The lateral loop ison the top layout shown in Fig. 5 with dash arrows. The verti-cal loop traveling perpendicular to the ground plane with viasconnecting is shown in Fig. 5 with solid arrows.

The parasitic inductance on the vertical loop mainly in-fluences the parasitic inductance of ringing loop because thetrace length of vertical loop is shorter than that of lateral loop.The parasitic inductance on vertical loop includes of parasiticinductance of trace line on the top layout, trace line on thebottom layout and vias through the board. In practical de-sign, the parasitic inductances of vias depend on vias designand board thickness. The board thickness must be minimizedto minimize the parasitic inductance of vias.

For the conventional PCB layout, the loop inductance isheavily dependent on the board thickness and vias when theringing loop is on both top and bottom layout of the PCB.



Fig. 6. Proposed PCB layout (Layout 2)

3.3 Proposed Optimal PCB Layout The proposedPCB layout design is shown in Fig. 6. The input capacitorand MOSFET are still placed on the top layout of the PCB.However, in this design, the output port is placed on the bot-tom layout. Consequently, the input capacitors can be placedin the middle distance between drain and source of MOSFETmodule to minimize physical trace length of ringing loop.The trace lines are designed as large as possible to minimizeparasitic inductance. In this design, the ringing loop onlytravels in the TOP layout of circuit board as shown in Fig. 6.

The proposed PCB layout provides three advantages com-paring to the conventional PCB layout design:

(1) Minimizing parasitic inductances design on one sideof PCB is easier than that on the vias.

(2) Parasitic inductance of ringing loop is independent ofboard thickness.

(3) The trace length is shorter and the trace width islarger. Therefore the AC resistance due to skin ef-fect is smaller. As a result, the conducting power losson the circuit will be reduced.

In this design, the parasitic inductance on the output portwill be increased and depended on the board thickness. For-tunately, an external inductance is always added to the outputport of resonant inverter. Consequently, the parasitic induc-tance on the output port of inverter does not effect to the in-verter performance.

While minimizing the physical size of the ringing loop isimportant to reduce parasitic inductance, the field self- can-cellation method can also reduce parasitic inductances. Inthis design, a metal heat sink is designed to cover not onlythe bottom of MOSFET module but also the area of PCBwhere contains the power loop. Heat sink will act as a “shieldlayer”. The power loop generates a magnetic field that in-duces a current, opposite in direction of current in the powerloop, inside a shield layer. In turn, the current in shield layergenerates a magnetic field to cancel the original magneticfield of power loop (12). As a result, the parasitic inductanceswill be reduced.

A bypass board, which is vertical with respect to the PCB,is designed and placed in close proximity to the MOSFETmodule, as shown in Fig. 7. The ringing loop inductance af-ter the bypass board is added to the PCB can be expressedas

Lloop =Llin · Lbyp

Llin + Lbyp+ Lmod − ΔL, · · · · · · · · · · · · · · · · (14)

where Lbyp is the parasitic inductance of the bypass board, ΔL

(a) PCB design

(b) Equivalent circuit

Fig. 7. Inverter design using bypass board

is the amount of reduction in Lloop as a result of the field self-cancellation effect. Note that the bypass board reduces Lloop

in two ways: (1) through providing a current path in paral-lel with the main trace line (see Fig. 7) (15), and (2) throughproviding a ringing current flowing in the opposite directionwith regard to the current in the MOSFET module. The latterfield self-cancellation effect becomes mostly effective whenthe dominant current flow direction in the bypass board be-comes anti-parallel with respect to the current direction in theMOSFET module. Since the current in the conventional by-pass board (15), which we refer to as Type 1 (Fig. 7), mostlyflows in vertical direction with respect to the current in theMOSFET module, we propose a bypass board of Type 2 withimproved layout enabling the dominant current flowing in thedesired direction.

Summarizing techniques of the proposed layout to reducethe parasitic inductances is as follows,• Design the ringing loop only on the top layout.• Place the arranged bypass board by using self-

cancellation of magnetic field.• Using the heat sink as a shield layer.

Next, the effect of the proposed layout is analyzed by EMsimulation.

4. EM Simulation Analysis

To verify the effectiveness of the inverter design proposedin the previous section, full-wave electro-magnetic (EM)simulations are performed using Sonnet em. Different in-verter configurations using various design options, such asdifferent PCB layouts, the heat sink (acting as a shield layer)and the bypass board, are analyzed.

4.1 Simulation Method Figure 8 illustrates an ex-ample of EM simulation model for the PCB of Layout 2 in



Fig. 8. EM Simulation model for analyzing PCB layoutinductance

Table 2. Summary of major parameters used in simulation

Fig. 6, consisting of two metal layers, vias, and input capac-itors. The major parameters used in the simulation are listedin Table 2. The shielding effect of the heat sink is takeninto account by placing additional metal layer underneath thebottom layout of the PCB. The thickness of the air (Air2 inFig. 8) defining the separation between the PCB bottom layerand the shield layer was set as 0.1 mm.

In order to extract the parasitic inductance of the trace lineof (4), the ringing loop in the PCB is disconnected at theinterface of the MOSFET module, leaving a two-port cir-cuit consisting solely of the trace lines and the input capac-itors. The ports to excite the circuit are placed at the wallof the analysis box using port extension lines which are de-embedded so as not to effect the simulation results. Theequivalent circuit of the two-port circuit is an inductor (Llin)and a capacitor (Cin) connected in series, so it should behaveeffectively as an inductor with inductance Llin at sufficientlyhigh frequency. The inductance Llin is estimated using thefollowing steps:1) Convert the simulated S-parameters of the two-port circuitto Y-parameters to compute the effective inductance seen be-tween ports 1 and 2 by using following equation,

Le f f (ω) =1ω

Im

⎛⎜⎜⎜⎜⎝Y11 + Y22 + 2Y12

Y11Y22 − Y212

⎞⎟⎟⎟⎟⎠ . · · · · · · · · · · · · (15)

This formula can be applied when the inductor is used in dif-ferential configuration (16). Figure 9 shows the EM-simulatedLe f f (ω) as a function of frequency (solid lines). It can be seenthat as the frequency becomes higher Le f f (ω) turns from neg-ative to positive value at the frequency of series LC resonanceand converges to the constant as the frequency is increased.

Fig. 9. Frequency dependence of effective inductance

2) Assume an equivalent circuit of simple series-connectedLlin and Cin. Then compute Le f f (ω) for the equivalent circuitand optimize Llin so that the overall frequency variation fit theEM-simulated Le f f (ω) obtained in step 1.

4.2 Effect of PCB Layout and Shield Layer Figure 9summarizes the simulated Le f f (ω) frequency dependence forLayout 1 and 2. It can be seen that with the optimum Llin

value (with Cin fixed at 4000 nF) the equivalent circuit resultfits the EM-simulation result. The validity of the obtained Llin

values can be confirmed by observing that the Le f f (ω) curvesfor both EM simulation and equivalent circuit cross zero atthe same series-LC resonant frequencies and both have thesame converging levels determined by the Llin value. Thus,the Llin value for Layout 1 is obtained as 2.6 nH, regardlessof using the shield layer (heat sink) because the PCB itselfis already shielded by the GND metal pattern on the backside. On the other hand, in the case of Layout 2, the optimumLlin value is 1.8 nH with the shield layer whereas it is 4.3 nHwithout the shield layer.

While the overall Le f f (ω) frequency response obtained bythe EM simulation can be reproduced by using a series LCcircuit, there are some other sub-resonating behaviors thatcannot be explained by such simple equivalent circuit. Thisis particularly evident in Layout 1, in which case the com-plicated layout leads to distributed L, C elements causingadditional parallel LC resonances (see inset of Fig. 9). Theproposed PCB of Layout 2 has thus additional advantage ofpreventing unpredictable sub-resonances that could lead tomalfunctioning of the inverter.

4.3 Effect of Bypass Board In order to confirm thefield self-cancellation effect of the bypass board, we comparethe ringing loop inductances for the inverter with and withoutthe bypass board. Figure 10 shows EM simulation modelsused for this particular purpose. Since the simulator uses aplanar solver, horizontal dummy metal pads are used to rep-resent the current paths through the MOSFET module andthe overlying bypass board, although the latter is intended tobe vertical in the real design (Fig. 7).



Fig. 10. EM simulation models used to evaluate the ef-fect of the bypass board (without shield layer)

Fig. 11. Schematic illustration of the parasitic induc-tance components

The proximity effect of the bypass board and the MOSFETmodule can be studied by varying the distance (d) betweenthe two opposite current paths. This can be done by varyingthe thickness of the air between the top layout and the bottomlayout, as shown in Fig. 10. Figure 11 is a schematic illustra-tion of how the total inductance components vary with theinverter design. If the PCB layout is fixed, Lloop obtained bythe afore-mentioned method should decrease as the bypassboard becomes close to the MOSFET module, as illustratedin Figs. 11(a) and (b). Now, however, this method overesti-mates the proximity effect of the bypass board, because it in-cludes the effect of the reduction in the via inductance (Lvia).

In order to avoid this problem, the following method isused. Since the field self-cancellation effect is not in effectwhen the two current paths become perpendicular to eachother, the dummy metal as the MOSFET module in Fig. 10(a)is rotated by 90 degree, as shown in Fig. 10(b). Since Lvia isnot changed in this modification, by taking the difference be-tween the total inductance for the two cases (Figs. 11(b) and(c)), only the desired inductance difference ΔL due to the fieldself-cancellation effect is obtained. This method is based onthe assumption that the inductance of the MOSFET moduleis not changed by the 90 degree rotation. To confirm this, thetotal inductances for Figs. 11(a) and 11(d), in which cases

Table 3. Summary of simulation results

Table 4. The parameters of probe

the two current paths are sufficiently distant (d = 16.0 mm)and thus the field self-cancellation effect should be negligibleanyway, are computed and found to be identical.

The values of ΔL for bypass board of Type 1 and Type 2 es-timated this way are 0.4 nH and 1.2 nH, respectively, clearlyshowing the advantage of the Type 2 bypass board. The Lloop

values for various PCB designs, obtained by taking the sumof the inductance elements in (14), are summarized in Ta-ble 3. Here, Lbyp is obtained by EM-simulation for an isolatedbypass board, Lmod is estimated using the data sheet from themanufacturer of the MOSFET module (17). The results indi-cate that the optimal layout for the PCB and the bypass boardas well as the shield layer significantly reduce the ringingloop inductance.

5. Experiment Result

5.1 Experiment Condition To compare the perfor-mance of the proposed PCB design with conventional design,two separate boards are created:

Layout 1: Conventional PCB layoutLayout 2: Proposed optimal PCB layoutAll of boards are made from the same type of copper board

and all of devices using on each board are also the same. Theparameter of PCB board is shown in Table 2 which is used tosimulate the PCB designs.

Measurement point is shown in Fig. 2. The measured sig-nal includes of the voltage across low-side MOSFET V2 andthe voltage across parasitic inductances as expressed in (10).

At high frequency, the measurement technique is very im-portant to properly measure the ringing transient. The ring-ing waveform measurements have been performed with Tek-tronix MSO3014 which the bandwidth and sample rate are100 MHz and 2.5 GS/s respectively. The voltage probe isTektronix P6139B. The parameters of probe are shown in Ta-ble 4.

The probe is directly soldered on the output pin of MOS-FET module. The ground wire of probe is as short as possi-ble.

The rising time and falling time of signal which we obtainin the measurement result is affected by parameters of probeand oscilloscope as shown in Fig. 12.

5.2 Experiment Result Figure 14 shows the out-put voltage waveform of class D inverter when switching



Fig. 12. Composite rise time of the series connection ofvoltage probe and oscilloscope

Fig. 13. Capacitance and Drain-to-Source voltage ofMOSFET ARF300 (18)

Table 5. Circuit parameter

frequency changes from 1 MHz to 13.56 MHz. These resultsare taken in the conventional PCB board without bypassboard. The result shows the effect of parasitic inductancesto the performance of inverter. The ringing frequency in theoutput voltage did not change when the switching frequencychanges. This result matched with the equation which isshown in (6). The ringing frequency is 58.14 MHz. Whenthe switching frequency increases, the amplitude of ringingpart at the end of period is bigger. From 3 MHz, the ringingcannot be damped. And from 8 MHz, the output voltage be-gins excised harmonics. At 13.56 MHz, the output voltagewaveform is almost ringing.

The parameter of circuit to estimate parasitic inductance ofringing loop is shown in Table 5. DRF1400 MOSFET mod-ule includes two ARF300 RF power MOSFETs connectingin half-bridge topology (17). In this case the output capacitorof MOSFET at 15 V is estimated from characteristic curvein datasheet of ARF300 RF power MOSFET as shown inFig. 13.

The parasitic inductance of ringing loop is estimated basedon (6). The measurement and estimation results are shown inTable 6 and Fig. 15. The design in case 2 is the conventionalPCB design and the design in case 5 is proposed PCB design.

Figure 15 shows that the experiment results and simulation

Table 6. Measurement and estimation result

Table 7. Experiment parameter

results have the same trend in parasitic inductance reduction.The difference between experiment results and simulation re-sults is acceptable. There are reasons which make that differ-ence. In simulation, we did not simulate the effect of shieldlayer to the parasitic inductance of MOSFET module. In theexperiment result the output capacitor of MOSFET which isused to estimate parasitic inductance of ringing loop is esti-mation value. This value makes error in the experiment re-sult. The parasitic inductance of probe also makes the errorin the measurement result. But we use the same method withboth of proposed PCB design and conventional PCB design.Therefore the error does not effect to the comparison relation-ship between proposed design and conventional design.

The results in case 2 and case 3 shows that the proposed by-pass board can reduce parasitic inductance of layout 1 from9.27 nH to 8.04 nH. These results verify the effectiveness offield self-cancellation effect which was simulated in Sect. 4.

The results in case 1 and case 4 verify the effectivenessof proposed main PCB board. The parasitic inductance ofPCB board without bypass board reduces from 10.7 nH to9.04 nH. If we assume that the parasitic inductance of MOS-FET module is 5.8 nH, the parasitic inductance of trace lineoutside MOSEFT in ringing loop will reduce from 4.9 nH to3.24 nH. In other word, the proposed main PCB board can re-duce 33.9% parasitic inductance of PCB trace line. And theparasitic inductance of ringing loop is independent of boardthickness.

The experiment results in case 2 and case 5 show that theproposed design can provide overall 23.4% reduction in par-asitic inductance in ringing loop compared to the conven-tional design, which agree reasonably well with the simula-tion. With proposed design, the parasitic inductance of PCBtrace line is minimized and independent of boar thickness.The parasitic inductance inside MOSFET module also is re-duced by applying field self-cancellation effect.

To compare the switching performance of MOSFET inconventional PCB design and proposed PCB design, we doexperiment with two boards in the same condition as shownin Table 7.

Figure 16 shows the prototype of a half-bridge class D in-verter using MOSFET DRF1400 which is designed accord-ing our proposal.



Fig. 14. Output voltage waveform when switching frequency change from 1 MHz to 13.56 Mhz (case 1) (DCvoltage = 15 VDC, Iload = 1 A)

Fig. 15. Experiment and simulation results of loop in-ductance

Fig. 16. Experiment prototype for proposed design

Figure 17 and Figure 18 show the output voltage waveformin conventional PCB board and proposed PCB board, respec-tively operating at 13.56 MHz. Experiment results are shownin Table 8.

In the MOSFET module, parasitic inductances are mini-mized. Therefore the output voltage of inverter can be con-sidered as the drain-source voltage of low-side MOSFET V2.

Fig. 17. Output voltage in the conventional PCB (case2) (50 V/div; 20 ns/div)

Fig. 18. Output voltage in the proposed PCB (case 5)(50 V/div; 20 ns/div)

Compare to the conventional PCB design, in this case theproposed PCB design can reduce positive peak voltage from145 V to 132 V. In other word, the overshoot voltage reduces13%. The negative peak voltage also reduces from −49 Vto −20 V (reduce 59%) and the amplitude of voltage ringingwhen MOSFET is in on state is significantly reduced. TheRise time of drain-source voltage is similar in two cases and



Table 8. Experiment result

the fall time is slightly reduced in proposed design. Theseresults agree reasonably well with the analysis in Sect. 2 andsimilar trend with the results in (6).

The ringing of drain-source voltage when MOSFET is inON state make the zero voltage switching (ZVS) conditionis very difficult to achieve. Therefore when the amplitude ofvoltage ringing reduces, the switching power loss will sig-nificantly reduce. In the proposed design, the amplitude ofdrain-source voltage ringing when MOSFET turn ON is sig-nificantly reduced but it is still high. As a result, the switch-ing power loss is still high even if the ZVS is applied.

6. Conclusion

This paper presented an analysis and PCB design for aclass D inverter operating at 13.56 MHz using MOSFETDRF1400. At high frequency, the parasitic inductances be-come a major factor effect on performance and stability ofinverter. PCB design is a key solution to minimize parasiticelements in the circuit.

An optimal PCB design was proposed to achieve the betterperformance than that of conventional design. The ringingfrequency increased 14.3%, the parasitic inductance reduced23.4% and the overshoot voltage also reduced 13%. The sta-bility of inverter also increased. In ringing loop, the tracelength was minimized and the trace width also was maxi-mized. Therefore the conduction loss of trace line was mini-mized. The switching performance of MOSFET was signifi-cantly improved and the switching power loss might reduce.

In the future work, the ringing damping methods will bestudy to reduce the switching power loss of MOSFETs.

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Nguyen Kien Trung (Student Member) received the B.E. (2008) andM.E. (2011) degrees in control and automation engi-neering from Hanoi University of science and Tech-nology. He is currently working toward the Ph.D.degree in Functional control systems at Shibaura In-stitute of Technology. His research interests includehigh-frequency dc/dc converter and wireless powertransfer systems.

Takuya Ogata (Non-member) received the B.E. degree in electricalcommunications engineering from Shibaura Instituteof Technology, Tokyo, Japan, in 2014, where he iscurrently working toward the M.E. degree.



Shinichi Tanaka (Member) received the B.E. and M.E. degrees inapplied physics from the University of Tokyo andthe D.E. degree in electrical engineering from To-hoku University in 1984, 1986 and 1997, respectively.In 1986, he joined the Central Research Laborato-ries, NEC Corporation, where he was involved inthe development of III-V compound semiconductortransistors and their applications to microwave andmillimeter-wave MMICs. From 1992 to 1993, he wasat Purdue University, West Lafayette, IN, as a Visiting

Scholar. Since 2009, he has been a Professor at the Department of ElectricalCommunications, Shibaura Institute of Technology, Tokyo. Dr. Tanaka issenior member of the IEEE and IEICE.

Kan Akatsu (Member) received B.S., M.S., and Ph.D. degrees inelectrical engineering from Yokohama National Uni-versity, Yokohama, Japan, in 1995, 1997, 2000 re-spectively. He joined Nissan Research Center, Yoko-suka, Japan, in 2000, he contributed to the design andanalysis of the new concept permanent magnet ma-chines. In 2003, he joined the department of Electri-cal and Electric Engineering at Tokyo University ofAgriculture and Technology, Tokyo, Japan, as an as-sistant professor. From 2005 to 2007, he is a JSPS

Postdoctoral Fellowship for Research Abroad, visiting professor in WEM-PEC (Wisconsin Electric Machines and Power Electronics Consortium),University of Wisconsin-Madison. From 2009, he was an associate profes-sor, now he is a full professor in Shibaura Institute of Technology, Tokyo,Japan. His research interests are motor control, motor design and invertercontrol. Dr. Akatsu is a member of the IEEE PELS, IAS, IE and IEE ofJapan.


analysis and pcb design of class d inverter for wireless

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