An Integrated ECC and Redundancy Repair Scheme for Memory

Reliability Enhancement

National Tsing Hua University

Hsinchu, Taiwan

Chin-Lung Su, Yi-Ting Yeh, and Cheng-Wen Wu

2IC-DFN/08-06/cww

IntroductionIntroduction Memory cores are widely used in SOC designs

They have higher density and occupy larger area Dominate the chip yield

Their use is increasing in nano-technologies according to ITRS

Reliability is also an important issue for memory

ECC and redundancy repair are both widely used fault tolerance techniques

After production test, there may be some un-used redundancy Combine ECC and un-used redundancy

Higher yield and greater degree of fault tolerance

3IC-DFN/08-06/cww

Chip Area BreakdownChip Area Breakdown

Source: International Technology Roadmap for Semiconductors (ITRS), 2001-2005

0%

20%

40%

60%

80%

100%

Area Memory

Area Reused Logic

Area New Logic

4IC-DFN/08-06/cww

Typical RAM BIST ArchitectureTypical RAM BIST Architecture

RAMT

est C

ollar (M

UX

)

BIST Module

Controller

Comparator

Pattern

Generator

Go/No-Go

RAM Controller

Counter

LUT

LFSR

Microprogram

Hardwired

CPU core

IEEE 1149.1

5IC-DFN/08-06/cww

Sharing Controller & SequencerSharing Controller & Sequencer

6IC-DFN/08-06/cww

Typical RAM ECC ArchitectureTypical RAM ECC Architecture

RAMCb GenCb Gen

Decoder

Syndrome Gen

Corrector16 16

16 16 16

6

6 66

Single Double

Syndrome

Data Bus

Mainly for improving reliability

7IC-DFN/08-06/cww

RAM Built-In Self-Repair (BISR)RAM Built-In Self-Repair (BISR)

RAM

MU

XBIST

Redundancy

Analyzer

Reconfiguration Mechanism

Sp

are E

lem

en

ts

I/O

Mainly for improving yield

8IC-DFN/08-06/cww

Main Memory

Spare Memory

BIRA

BIST

Wrapper

Q

D

A

A Power-On BISR SchemeA Power-On BISR Scheme

MAO

POR

MAO: mask address output; POR: power-on reset Source: ITC’03

9IC-DFN/08-06/cww

Proposed SchemeProposed Scheme Integrated ECC and Redundancy Repair Scheme

Hard errors are repaired by physical redundancy in field

Soft-error correction ability is not harmed by hard errors

Enhance reliability

Assumptions During Error Identification phase, no other faults

may occur Error rate << system clock speed

10IC-DFN/08-06/cww

Phases of Proposed SchemePhases of Proposed Scheme

11IC-DFN/08-06/cww

Error Identification PhaseError Identification Phase Write back process

Write the corrected data back to memory Read data from the same address

Soft error may be eliminated with this process

Assume that no other errors may occur

After error identification “Hard repair phase” for a hard error/fault “Fault-free phase” for a soft error

12IC-DFN/08-06/cww

Hard Repair PhaseHard Repair Phase Repair this hard fault with spare

Map the faulty word to redundant word Write the corrected data into redundant word

Hard fault location In main memory: follow the above procedure In redundant memory: mark the faulty redundant

element

During this phase, memory cannot be accessed Idle mode

Hard fault is removed after this phase Reliability and MTTF is increased

13IC-DFN/08-06/cww

Experimental ResultsExperimental Results Technology: TSMC 0.25um CMOS process

The redundant memory consists of eight spare rows and four spare columns

Memory Size ECC BIST RC Total (%)

32K x 32 1,084 2572 824 0.52

32K x 64 1,502 3895 824 0.48

32K x 128 2,033 6434 824 0.41

16K x 64 1,391 3855 783 0.77

8K x 128 1,955 6396 728 1.16

TotalMemory Area+BIST+RC

ECC

14IC-DFN/08-06/cww

Experimental Results (cont.)Experimental Results (cont.)

Memory Size Area (gates) MTTF (hours) Cost

8k X 32 !ECC 195413 321.74 613.6

SEC 220862 37147 5.96

SECP 222030 39786 5.58

4k X 64 !ECC 171522 344.36 498.1

SEC 192610 28010 6.88

SECP 194153 30834 6.30

2k X 128 !ECC 157622 359.53 438.4

SEC 176159 20681 8.52

SECP 178380 23629 7.54

Cost = Area / MTTF

!ECC: Without ECCSEC: With SEC/DED ECCSECP: Proposed Scheme

Area = Memory + ECC + BIST

15IC-DFN/08-06/cww

Reliability ImprovementReliability Improvement

8K x 64 memoryr+c = 12

16IC-DFN/08-06/cww

ConclusionsConclusions An integrated ECC and redundancy repair

scheme is proposed Enhancing memory reliability and MTTF

Low area overhead Integrating ECC Controller with BIST

No timing penalty in normal operation

Cost-effective way for reducing the effect of parametric defects