defect-tolerant fpga switch block and connection block with fine- grain redundancy for yield...

Defect-tolerant FPGA Switch Block Defect-tolerant FPGA Switch Block and Connection Block with Fine-and Connection Block with Fine-

grain Redundancy for Yield grain Redundancy for Yield EnhancementEnhancement

Anthony J. YuAnthony J. Yu Guy G.F. LemieuxGuy G.F. Lemieux

August 25, 2005August 25, 2005

FPL'05 - PresentationFPL'05 - Presentation 22

OutlineOutline

Introduction and MotivationIntroduction and Motivation

Previous ApproachesPrevious Approaches

Fine-grain RedundancyFine-grain Redundancy

ResultsResults

ConclusionsConclusions


Introduction and MotivationIntroduction and Motivation

Scaling introduces new Scaling introduces new types of defectstypes of defectsNumber of defects Number of defects expected to increase as expected to increase as chip density increaseschip density increases– As a result, chip yield is on As a result, chip yield is on

the declinethe decline

FPGAs are mostly FPGAs are mostly interconnectinterconnect

To improve yield (and To improve yield (and revenue), we must revenue), we must tolerate multiple tolerate multiple interconnect defectsinterconnect defects


Previous ApproachesPrevious Approaches

Defect-tolerance is one method to Defect-tolerance is one method to minimize impact of manufacturing defectsminimize impact of manufacturing defectsTwo approaches taken by industry: avoid Two approaches taken by industry: avoid the defective resources (Xilinx EasyPath) the defective resources (Xilinx EasyPath) or make the defective resources or make the defective resources inaccessible (Altera)inaccessible (Altera)Past attempts either did not scale well, Past attempts either did not scale well, required too much reprogramming time or required too much reprogramming time or affected signal timingaffected signal timing


ObjectiveObjective

ProblemProblem– FPGA yield is on decline because of FPGA yield is on decline because of

aggressive technology scalingaggressive technology scaling

Important objectives to improve yield:Important objectives to improve yield:– Tolerate interconnect defects (dominates Tolerate interconnect defects (dominates

area)area)– Tolerate multiple defects (future trend)Tolerate multiple defects (future trend)– Preserve timing (no timing re-verification)Preserve timing (no timing re-verification)– Fast correction time (production use)Fast correction time (production use)


Fine-grain Redundancy (FGR) – Fine-grain Redundancy (FGR) – Defect Avoidance by ShiftingDefect Avoidance by Shifting

DefectSpare

a) Original b) Corrected

+1

+1 -1-1

-1+1


Island-style FPGAIsland-style FPGA


Directional Switch BlockDirectional Switch Block


Defect-tolerant Switch BlockDefect-tolerant Switch Block

-1 0-2

+1 0+2

-10

-2

+10

+2

-1 0-2

+1 0+2

-10

-2

+10

+2

omux

imux

a) Original b) Defect-tolerant


Switch Implementation OptionsSwitch Implementation Options


Defect Avoidance - Example 1Defect Avoidance - Example 1


Defect Avoidance - Example 2Defect Avoidance - Example 2


ResultsResults

AreaArea

DelayDelay

Area Delay ProductArea Delay Product

YieldYield

SummarySummary


Area ResultsArea Results


Delay ResultsDelay Results


Area-Delay ProductArea-Delay Product


Yield - 1Yield - 1

* Assumes all bridging defects


Yield - 2Yield - 2


SummarySummary


ConclusionConclusion

FGR meets desired objectives:FGR meets desired objectives:– Tolerates Tolerates multiplemultiple randomly distributed defects randomly distributed defects– Defect correction Defect correction does not perturb timingdoes not perturb timing– Tolerates an Tolerates an increasing numberincreasing number of defects as array of defects as array

size increasessize increases– Correction can be applied Correction can be applied quicklyquickly

FGR has different implementation optionsFGR has different implementation options– Trade-offs between yield, area and delay can be Trade-offs between yield, area and delay can be

mademade

Thank you!Thank you!

[email protected]@ece.ubc.ca

defect-tolerant fpga switch block and connection block with fine- grain redundancy for yield...

Documents

fpl05 presentation

signal timing slide

directional switch block

areadelay product slide

islandstyle fpga slide

bridging defects

multiple interconnect

chip yield