pcb design dr. p. c. pandey ee dept, iit bombay revised aug’07
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1PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
PCB DESIGNPCB DESIGNDr. P. C. Pandey
EE Dept, IIT Bombay
Revised Aug’07
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2PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
Topics1.General Considerations in Layout Design2.Layout Design for Analog Circuits3.Layout Design for Digital Circuits4. Artwork Considerations
ReferencesW.C. Bosshart, Printed Circuit Boards: Design and Technology, TMH, 1992
C.F. Coombs : Printed Circuits Handbook , McGraw-Hill, 2001R.S. Khandpur : Printed Circuit Boards : Design, Fabrication, and Assembly, McGraw-Hill, 2005.
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3PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
1.1.GENERAL CONSIDERATIONS GENERAL CONSIDERATIONS IN LAYOUT DESIGNIN LAYOUT DESIGNMain issues• Component interconnections • Effects of parasitics• Physical accessibility of components • Power dissipation
Subtopics 1.1 Parasitic effects1.2 Supply conductors1.3 Component placement
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4PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
1.1 Parasitic Effects1.1 Parasitic Effects R & L of conductor tracksC between conductor tracks
ResistanceResistance of 35 μm thickness, 1 mm wide conductor = 5 mΩ/cmChange in Cu resistance with temperature = 0.4% / °CCurrent carrying capacity of 35 μm thickness Cu conductor (for 10 °C temperature rise):
Width (mm) 1 4 10Ic (A) 2 4 11
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5PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
Capacitance• Tracks opposite each other
- Run supply lines above each other- Don’t let signal line tracks overlap for any significant distance
• Tracks next to each other- Increase the spacing between critical conductors- Run ground between signal lines
InductanceTo be considered in• High frequency analog circuits• Fast switching logic circuits
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6PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
1.2 Supply Conductors1.2 Supply ConductorsUnstable supply & ground due to• Resistive voltage drop• Voltage drop caused by track L and high freq. current• Current spikes during logic switching local rise in ground potential & fall in Vcc potential possibility of false logic triggering.
Solutions• Conductor widths : W (ground) > W (supply) > W(signal)• Ground plane• Track configuration for distributed C between Vcc & ground• Analog & digital ground (&supply) connected at the most stable point
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7PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
1.3 Component Placement1.3 Component Placement
• Minimize critical conductor lengths & overall conductor length • Component grouping according to connectivity • Same direction & orientation for similar components • Space around heat sinks • Packing density
• Uniform• Accessibility for
• adjustments • component replacement • test points• Separation of heat sensitive and heat producing components
• Mechanical fixing of heavy components
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8PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
2. LAYOUT DESIGN FOR 2. LAYOUT DESIGN FOR ANALOG CIRCUITSANALOG CIRCUITS• Supply and ground conductors • Signal conductors for reducing the inductive and capacitive coupling • Special considerations for
• Power output stage circuits • High gain direct coupled circuits • HF oscillator /amplifier • Low level signal circuits
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9PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
2.1 Ground & Supply Lines2.1 Ground & Supply Lines
• Separate GND (& Vcc) lines for analog & digital circuits• Independent ground for reference voltage circuits• Connect different ground conductors at most stable reference point
• Supply lines with sufficient width and high capacitive coupling to GND (use decoupling capacitors)• Supply line should first connect to high current drain ckt blocks• Supply line independent for voltage references
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10PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
2.2 HF Oscillator / Amplifier2.2 HF Oscillator / Amplifier• Decoupling capacitor between Vcc & GND Capacitive load on o/p• Reduce capacitive coupling between output & input lines• Vcc decoupling for large BW ckts. (even for LF operation)• Separation between signal & GND to reduce capacitive loading
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11PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
2.3 Circuits with High Power O/P 2.3 Circuits with High Power O/P StageStageResistance due to track length & solder joints modulation of Vcc & GND and low freq. oscillations • Large decoupling capacitors • Separate Vcc & GND for power & pre- amp stages
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12PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
2.4 High Gain DC 2.4 High Gain DC AmplifierAmplifierSolder joints thermocouple jnTemp gradients diff. noisy voltages
• Temp.gradients to be avoided • Enclosure for stopping free movement of surrounding air
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13PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
2.5 Low Level Signal 2.5 Low Level Signal CircuitsCircuits
A) High impedance circuits - Capacitive coupling
B) Low impedance circuits - Inductive coupling
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14PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
High -Z circuitsHigh -Z circuits
If R » 1∕ jw(Cxy+Cy)then coupled Vy = Va × [Cxy/(Cy+Cxy)]
• Increase separation between low level high Z line and high level line(decrease Cxy)• Put a ground line between the two (guard line)Example: Guard for signal leakage from FET output to input
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15PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
Low – Z CircuitsLow – Z Circuits• Voltage induced in ground loops due to external magnetic fields • Current caused in the low- Z circuit loop due to strong AC currents in nearby circuits
Vm= - (d/dt) B dA
• Avoid ground loops • Keep high current ac lines away from low level,low Z circuit loops • Keep circuit loop areas small
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16PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
3. LAYOUT DESIGN FOR DIGITAL 3. LAYOUT DESIGN FOR DIGITAL CIRCUITSCIRCUITS
Main problems
• Ground & supply line noise• Cross-talk between neighboring signal lines• Reflections : signal delays, double pulsing
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17PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
3.1 Ground & Supply Line Noise3.1 Ground & Supply Line NoiseNoise generated due to current spikes during logic level switching, drawn from Vcc and returned to ground
• Internal spike: charging & discharging of transistor junction capacitances in IC ( 20 mA, 5ns in TTL)• External spike: charging & discharging of output load capacitance
Ground potential increases, Vcc decreases: improper logic triggering.Problem more severe for synchronous circuits.Severity of problem (increasing): CMOS, ECL, TTL.
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18PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
Solution for ground & supply noiseSolution for ground & supply noise • Decoupling C between Vcc & ground for every 2 to 3 IC’s :
ceramic, low L cap. of 10 nf for TTL & 0.5 nF for ECL & CMOS•Stabilizes Vcc-GND (helps against internal spikes• Not much help for external spikes
• Low wave impedance between supply lines (20 ohms):5 to 10 mm wide lines opposite each other as power tracks
• Ground plane : large Cu area for ground to stabilize it against external spikes
• Closely knit grid of ground conductors (will form ground loops, not to be used for analog circuits)
• Twist Vcc & GND line between PCBs
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19PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
3.2 Cross-talk3.2 Cross-talk
• Occurs due to parallel running signal lines (ECL: 10cm,TTL: 20 cm, CMOS: 50 cm)• Problem more severe for logic signals flowing in opposite directions
Solutions• Reduce long parallel paths• Increase separation betw. signal lines• Decrease impedance betw. signal & ground lines• Run a ground track between signal lines
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20PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
3.3 Reflections3.3 Reflections
Caused by mismatch between the logic output impedance & the wave impedance of signal tracks. • Signal delay (low wave imp.) • Double pulses (high wave imp.)
TTL (Z: 100 - 150 )0.5 mm signal line with GND plane, 1 mm without GND plane.Signal lines between PCBs twisted with GND lines.
ECL (Z: 50 )1 - 3 mm signal line with GND plane, or nearby gnd conductor.
CMOS (Z: 150 – 300 )0.5 mm signal line without GND plane. Gnd not close to signal lines.
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21PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
Logic Family: TTL ECL CMOSSignal–GND Zw () 100 - 150 50 - 100 150 - 300
Signal line width (mm)
0.5 with gnd1, no gnd
1 - 3 with gnd 0.5, no gnd
Vcc -GND Zw () < 5 < 10 < 20
Vcc line (mm) 5 2 to 3 2GND line (mm) Very broad
(plane /grid)Broad(plane/grid)
5
Summary of Layout Design Considerations(for 1.6 mm thickness, double sided boards)
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22PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
4. ARTWORK RULES4. ARTWORK RULES
Conductor orientation • Orientation for shortest interconnection length. • Conductor tracks on opposite sides in x-direction & y-direction to minimize via holes.• 45° or 30° / 60° orientation for turns.
Conductor Routing • Begin and end at solder pads, join conductors for reducing
interconnection length.• Avoid interconnections with internal angle <60°.• Distribute spacing between conductors .
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23PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
Conductor routing examples
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24PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
Solder PadsSolder Pads
Hole dia• Reduce the number of different sizes.• 0.2 - 0.5 mm clearance for lead dia.
Solder pad• Annular ring width
≥ 0.5 mm with PTH ≈ 3 × hole dia without PTH
• Uniformity of ring around the hole.• Conductor width d > w > d/3.
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25PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03
>>> <<<• Artwork• Digital Ckts• General • Analog Ckts
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