paul tindall head of software
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Paul Tindall Head of Software
Software Defined Radio – SDRThe Future of Wireless
SDR - "Radio in which some or all of the physical layer functions are software defined“- Wireless Innovation Forum
2
Future of Wireless
Complexity: “I need to support 10 Radio bands a 8 standards/modes to make a phone
that works anywhere on the Vodafone network” - Trevor Gill, Chief Scientist Vodafone
Post Production Flexibility “I wish I could change the radio filter in the Heathrow ATC RADAR so I can use
the adjacent spectrum” “I’d prefer totally dynamic spectrum assignment” – Graham Louth – Ofcom : UK regulator
Dynamic Behaviour Cognitive radio is required to manage licensed and unlicensed spectrum Terminals will sense and reconfigure themselves according to
location/environment –Jussi Kahtava
Or considerably longer
4
GSMWCDMA
WiMax
CDMA2000/EVDOHSPA
TD-LTELTE-A
WhiteSpaceWiFi
LTE
TETRA
Automotive Market Long product lifetime: >10 years Networks and spectrum allocations will change Manufactured for a global market A great Mimo Platform
Instead of you carrying the mobile;
the mobile carries you
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Designing Modems
Channel Codec
Radio I/F
Timebase Counters
Cipher Equalser
Speech Codecs
Control Loops
Channel Measurement
s
DSP
L1/PS
RTOS
L1
PSPower Saving Device
Man
Rake
L1
DSP
PS
RTOS
PSPower Managem
ent and control DeviceMan
System Time Controller
Radio Controller
Speech
Power Controller
Mimo RFTiming Gen Eq
Demapper
FFT
Mimo RFMimo RF
Mimo RFMimo RF
OSDevice Drivers Control loops L1
L1L1
L1
RTOS Device Ctrl RLC/Mac• Companies have ‘Velcro’ed modems together• (investment in legacy high) BUT• The future predicts greater complexity• Lack of reuse costs
• Si area• SW dev time• Maintenence
The SDR Way• Replace bespoke hardware with a general purpose “Wireless Computer “• Create a Modem Specific OS
• To mop up/factor out common services• Hide/abstract the underlying h/w
complexity• Publish the modem developer an API• Add Modem ‘waveform’ deployment and
management functions•Create tools (like the Android SDK) to develop, simulate and test modem apps
GSM
3GLTE
SDMOS
Modem Computer
6
The Complexity Problem
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Many Modes in the same box
0
50
100
150
200
250
300
350
400
450
500
1990 1995 2000 2005 2010 2015
Bitr
ate,
Mbp
s
GSMGPRS200MOp/s
HSPA 5GOp/s
LTE 50GOp/s
LTE-A 1Gbps 300GOp/s
HSPA+ 20GOp/s
GSM 3G HSPA
LTE WiFi GPS FM BT
GSM M M Y Y Y Y3G HSPA M M Y Y Y YLTE M M Y Y Y YWiFi Y Y Y Y Y YGPS Y Y Y Y Y YFM Y Y Y Y Y YBT Y Y Y Y Y Y
(M = measurement)
3GPP R10
8
GSMGPRS
EDGE
3GPP 99
3GPP R5 HSDPA
3GPP R6 HSUPA
3GPP R7 HSPA+3GPP R8
3GPP R9
164Mbps
28Mbps
11Mbps
42Mbps
84Mbps
23Mbps
LTE R8/R9150Mbps
50Mbps
The Scaling ProblemLTE-A1Gbps
500Mbps
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SDR Types/Flexibility
Flexibility
Hardware only
Processor Assisted H/W
Hardwired , specialised processors
General PurposeSDM Platform
• Complex• Flexible• Dynamic • Permit innovation • Efficient• Field Upgradable• Reasonable Cost• Scalable
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Analogue Domain Digital Domain
LTE FDD, MIMO
SerA/DBPF
SerA/DBPF
LO
SerD/APABPF
ofdm_demux chan_est
symbol_detect
ofdm_demux chan_est
tx_front mod_map
prach_gen
uplink_enc
cell_search
metrics
agc_man
COM
MDM
ADM
ADM
A
timing_man
GPIO
TSCU
rx_front
rx_front
afc_man
DL-SCHPCH
CFIDCIHARQ N/ACKBCH
Cell IDSlot TimingFrame TimingFreq. Offset
Rank CQIPMI
UL-SCH
CQIRIPMIHARQ N/ACK
UE Params.
data_dec
control_dec
RX1
RX2
TX
SDR starts at the Digital I/Q interface
Processes were mapped to h/w blocks running
in parallel;Now mapped to sw running
on a processor
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The VSP – a key enabling technology
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Register File
Connection Network
Scalar unit
Control Unit
FUFUFU
FU
The VSP – 3 forms of Parallelism
Data Parallelism Add 1 or more SIMD units (Single Instruction Multiple Data) Wide Data paths eg 512 bit SIMD (Vector) widths eg 64 lanes - ie 64 MAC operations in 1 cycle Requires Algorithms to be expressed correctly to exploit vector
processing:
SIMD Unit
•Instruction Level Parallelism• VLIW – eg 256, 512 ... bits • Several ‘Functional Units’ work in parallel• Register and memory accesses/write-backs are pipelined• Pipeline is exposed to the Compiler• The Compiler analyses the control and data dependencies of the
whole program• The Compiler converts eg ‘C’ to an execution schedule by
reordering the program• Parallelising compilers are well understood and mature
Like a ‘Dragster’ – incredible quick in a
straight line
So can’t be interrupted –
run to completion
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The VSP – 3 forms of Parallelism
Task Level Parallelism Using multi-threaded cores Eg: Multiple VSP cores
Interconnected with dedicated pipes, shared memories etc A variety of topologies
Some form of high level sequencing mechanism High Level Tool support (or even new languages) required
FU
UFU UUF
U UUFU U
Interconnect
Multi-threaded Sequencer Unit
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SDR Scalable H/W architecture
Control processor
Programmable ‘soft’Timing unit
Rf if
ProgrammableSequencer
Power Control
VSP
scale
scale
Vsp interconnect
Co-proc
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The SDR Platform
3G
BT GPSLTE
Modem OSModem Domain Specific Model
Driven Development Tools
SDR Debug ToolsCommon compliance
methodologyControl processor
Programmable ‘soft’Timing unit Rf
if
Programmable
Scheduler
Power Control
VSP
scale
scale
Vsp interconnect
Co-proc
•Domain Specific OS• Factored out modem services• h/w platform abstraction• Common APIs
•Modems are Applications•Waveform/Modem lifecycle
•Dynamic Modem management• Sense• lookup
•Multi-mode resource management• Coordinated and uncoordinated modems
GalileoWfiLTE-TDD
20
An example Multi-Core methodology
Using UML
Activity Specifications eg HSDPA RRC Filter:
DownlinkRRCFilter
p_RawIQInput
p_RRCFilterParams
p_RRCFilterCommonParams
p_ConditionedIQOutput
bufferSizep_filterCoeffnumCoeff
IQBuffer ConditionedIQBuffer
void DownlinkRRCFilter( const CmplxVec_t * restrict p_RawIqInput, CmplxVec_t * restrict p_ConditionedIQOutput, const RRCFilterParams_t * p_RxRRCFilterParams, const RxRRCFilterCommonParams_t * p_RxRRCFilterCommonParams );
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UML Activity Diagrams
outputBuffer
p_Output0p_Input0
<<VSP>>FFT
inputBuffer
p_Output1p_Input1
<<VSP>>Filter
decisionParam
triggerSource
transferSize
destinationAddr<<HW_RFDMA>>Activity 2
source
size
[1]
[0]
destBuffer
ControlSignal
Start Node
Finish Node
Fork 2 activities
Conditional path Merge flows
Synchroniseflows
Buffer Allocated
Control Signal
Control Signal Input
Control Signal Output
Signal Proc Task running
on a VSP
H/W ‘Engine’
DMA transfer
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Conditional
Join
Fork
Synchronise
Invoke
Complete
Sequencer
VSP
DMA
Other Procs
SequencerInstructionset
The Sequencer: Instruction Set
24
A Real Platform
CDC Architecture
Protocol Stack Domain ARM Cortex R4 CPU for L2/3 Protocol S/W Interface Peripherals and Boot ROM
ARM Coresight Debug Combined Debug and Trace
DDR2 Interface 32bit, 200MHz
Ethernet Interface 1 Gbit/s
MCE Contains: Cortex R4 CPU 6 VSP Cores 2x Turbo Engine
RF Interface Up to 4RX + 2TX
Power Domains System Controller – 35 domains Supports Deep Sleep Power Down
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CDP-2 BoardFPGA Mezzanine Card (FMC) Interface
Main and Auxiliary FPGAs
Main PGA
AuxiliaryPGA
567pin PBGAH packageZIF Socket for Cognovo CDC
SMPS Modules
ARM® Trace-ICE Port
RJ45 Ethernet Connector Gigabit Ethernet chip Dot Matrix Display
16 LEDs
GPIO connectors
General Purpose Buttons
Serial to USB Module
14 Layers PCB
12V DC Power input
256MBytes DDR2 SDRAM
26.0MHz VXCO
27
Final Thoughts
SDR platforms will deliver our wireless future
BUT it is potentially disruptive: Who owns the Standards/waveforms – OEM, Google, Sky,
ETSI, Qualcomm, IP companies, new entrants? Separating the h/w and standardising it disrupts the Si supply
chain How is compliance tested – who is responsible now? How is Essential IPR paid/managed?
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