fyse420 digital electronics lecture 1users.jyu.fi/~loberg/fyse420slides/fyse420lecture1.pdf ·...

FYSE420 DIGITAL ELECTRONICS

Lecture 1Lecture 1

©Loberg

1

DIGITAL LOGIC

CIRCUIT ANALYSIS

& DESIGNNelson, Nagle, Irvin, Carrol

ISBN 0-13-463894-8

DIGITAL DESIGNMorris Mano

[1]

[2]Morris Mano

Fourth edition

ISBN 0-13-198924-3

Digital DesignPrinciples and Practices

Fourth edition

Wakerly John F.

ISBN 0-13-186389-4

[3]

2

Synchronous sequential logic Asynchronous sequential logic

Asynchronous Sequential Logic

INPUT

CLK

INPUT

Introduction

OUT A

OUT B

The change of internal state occurs

in response to the clock pulses.

Memory element : clocked filp-flops

OUT A

OUT B

The change of internal state occurs when

there is change in the input variables.

Memory element : unclocked filp-flops or

time-delay elements.

3©Loberg

Synchronous sequential logic Asynchronous sequential logic

Asynchronous Sequential Logic

A properly designed system

"No timing problems"

The design of asynchronous sequential

No clocked flip-flops

Timing problems

Feedback bath

Introduction

The design of asynchronous sequential

circuits is difficult

Used when speed of operation is important

Fast response to the change of input variable

Redused logic and power dissipation

No clock distribution

4©Loberg

Needs a clock distribution

Clock distribution takes a large

amount of power in large

VLSI chips

Asynchronous Sequential Logic

y

x1x2

xn

z2

z1

zm

m output variablesn input variables

Combinational

circuit

Block diagram of an asynchronous sequential circuit

Introduction

Delay

Delay

Delay

Y1Y2

Yk

y1

y2

yk

k secondary variables k exitation variables

(next state)(present state)

5©Loberg

Analysis of asynchronous sequential circuits

Because of delays in the wires and the gate circuits it is impossible to say which

variable changes its state first when two or more input variables change at

exactly same instant time.

To ensure proper operation, circuits must be allowed to attain a stable state before the

input is changed to a new value.

Asynchronous Sequential Logic

Fundamental mode

Input signals change one at a time and only when the circuit is in the stable state.

6©Loberg

Exitation functions

Analysis of asynchronous sequential circuits

yxxyY +=

Assumption: x xand has same timing

xY1

Y2

y1

y2

If not, we have two input variables x xand

If we use individual gates

this will be true.

Circuit example1

Asynchronous Sequential Logic

( Unrealistic assumption ! )

Propagation delay in the combinational

circuit provides a sufficient delay.

Secondary – and exitation variables (Y1 = y1 and Y2 = y2 ) are same in the steady-

state condition, but during transition they are not.

211 yxxyY +=

212 yxyxY +=Input variable : x

Exitation variables : Y1 and Y2

Secondary variables : y1 and y2

Outputs : Y1 and Y2

7©Loberg

Total states of sequential circuit consists of stable states and unstable states.

x y1 y2 Y1 Y20 0 0 0 0

00 0100

0 1x

y1y2Unstable state

Circuit example1

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

23=8 total states

Map for Y1 and Y2

0 0 00 000

101

1 1111

0 00

011

01

1

1

1

0

0

00

0

0

11

1

1 1 1 1 0

Transition table

00 01

11

11

10

01

10

00

00

01

11

10

Y1Y2

Stable state : y1y2 = Y1Y2

Unstable state

8©Loberg

x

Y1

Y2

xy1y2=000

Propagation delay

00 01

11

11

10

01

10

00

00

01

11

0 1x

y1y2

Circuit example1

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

Transition table

Stable state

Stable state

Stable state

Stable state

Unstable state

Unstable state

Unstable state

xy1y2=000

xy1y2=100

xy1y2=101

xy1y2=001

xy1y2=011

xy1y2=111

xy1y2=110

xy1y2=010

xy1y2=000

100010

Y1Y2

9©Loberg

Simulation example1

y1x

Circuit diagram

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

y2

x

Y1

Y2

10©Loberg

Simulation example1

unstable unstableunstableunstable

00 01

11

11

10

01

10

00

00

01

11

10

0 1x

y1y2

Y1Y2

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

Transition table

Y1

Y2

x

x

Y1Y2

Simulated output sequence 11©Loberg

Sometimes it is more convenient to name the states by letter symbols.

00 0100

0 1x

y1y2

a ba

0 1x

statea=00 , b=01 , c= 11 , d= 10

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

Transition table

Assign binary values to the states

Flow table

00 01

11

11

10

01

10

00

00

01

11

10

Y1Y2

a b

c

c

d

b

d

a

a

b

c

d

Next state

12©Loberg

Circuit example2

Assumption: We use inverter for the complement of x

Inverter has "large"

gate delay. xY1

Y2

y1

y2Stable state

0

0

0

0

0

0

0

0

1

0

1

0

0

0

0

k Y1l Y2y1 y2

0

0

0

We have two input variables x xand

k l211 lykyY ++++====

212 lyykY ++++====

x

x k

ltime

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

1

1

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

1

0

1

0

0

1

1

0

1

1

1

0

0

0

1

0

1

1

1

0

0

1

1

0

1

24=16 Total states

k ly1y2

00

00 01 11 10

01

11

10

Y1Y2

00 10

00 00

00

01

00

01

1011

11

1000

11

01

11

Transition table

13©Loberg

Simulation result of example2

k ly1y2

00

00 01 11 10

01

11

10 00 10

00 00

00

01

00

01

1011

11

1000

11

01

11

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

x

xk

l

1Y

2Y

Y1Y2

14©Loberg

Circuit diagram for simulation

of example2

k

l

1Y

2Y

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

2Y

Propagation delay

and

Inverter

15©Loberg

Convention for gate delays

in circuit diagrams

B

AY Y

A

B

10 ns10 ns10 ns

Only LOGICAL equality

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

B

AY Y

A

B

10 ns0 ns 10 ns

LOGICAL equality Equal TIMING

16©Loberg

Example

( )( )

212111

212212

211211

yyyyxZ

xxRxxS

xxRxxS

++=====

S

R

Q

Q

x1x2

x1x2

x1

Z1Y1S1

R1

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits SR latch in asynchronous sequential circuit

Boolean functions

( ) 212122

212111

yyyyxZ ++=

S

R

Q

Q

x2x1

x1x2

x2

Z2

Y2S2

R2

Example Circuit

17©Loberg

x1x2y1y2

00

00 01 11 10

01

11

00 00

01

01

01

01

1111

11

10

10

00

0 0 0 0 0 0 0 10 0 0 1 0 1 1 00 0 1 1 0 1 1 10 0 1 0 0 0 1 10 1 0 0 0 0 0 00 1 0 1 0 0 1 00 1 1 1 1 0 1 0

x1x2 y1y2 Y1Y2 z1z20 0 0 0 0 10 0 0 1 1 00 0 1 1 1 10 0 1 0 1 10 1 0 0 0 00 1 0 1 1 00 1 1 1 1 0

x1x2 y1y2 z1z2

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits SR latch in asynchronous sequential circuit

10

Y1Y2

00 111010

Transition table

0 1 1 0 1 0 1 11 1 0 0 1 0 0 01 1 0 1 1 1 0 01 1 1 1 1 1 1 01 1 1 0 1 0 0 11 0 0 0 0 1 0 11 0 0 1 0 1 0 01 0 1 1 1 1 1 11 0 1 0 1 1 0 1

Transition table

0 1 1 0 1 11 1 0 0 0 01 1 0 1 0 01 1 1 1 1 01 1 1 0 0 11 0 0 0 0 11 0 0 1 0 01 0 1 1 1 11 0 1 0 0 1

Total state table

How we find columns Y1 and Y2 ?

18©Loberg

212212211211 xxRxxSxxRxxS ====0 0 0 0 0 1 0 0 0 00 0 0 1 0 1 0 0 0 10 0 1 1 0 1 0 0 0 10 0 1 0 0 1 0 0 0 00 1 0 0 0 0 0 1 0 00 1 0 1 0 0 0 1 0 00 1 1 1 0 0 0 1 1 0

x1x2 y1y2 S1R1 S2R2 Y1Y2

x1x2y1y2

00

00 01 11 10

01

01,00

01,00 00,01

00,01

10,00

10,00

00,10

00,10

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits SR latch in asynchronous sequential circuit

Present state y1y2Next state Y1Y2

0 1 1 1 0 0 0 1 1 00 1 1 0 0 0 0 1 1 01 1 0 0 1 0 0 0 1 01 1 0 1 1 0 0 0 1 11 1 1 1 1 0 0 0 1 11 1 1 0 1 0 0 0 1 01 0 0 0 0 0 1 0 0 11 0 0 1 0 0 1 0 0 11 0 1 1 0 0 1 0 1 11 0 1 0 0 0 1 0 1 1

Latch exitation table with

exitation variables

01

11

10

01,00

01,00

01,00

00,01

00,01

00,01

10,00

10,00

10,00

00,10

00,10

00,10

Latch exitation table

S1R1,S2R2

19©Loberg

SR latch in asynchronous sequential circuit

y Y S R

0 0 0 X0 1 1 01 0 0 1

For example: transition from state 0 to state 0

SR=01 force to state 0

SR=00 use original state 0

transition from state 1 to state 0

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

Use latch exitation table to find states of exitation variables Y

1 0 0 11 1 X 0

1or0x ≡≡≡≡

SR=11 input state is forbidden

Note!

SR=01 force to state 1

transition from state 1 to state 1

SR=10 force to state 1

SR=00 use original state 1

20©Loberg

x1x2y1y2

00

00 01 11 10

01

11 10

00 00

00 00

0101

1111 10

1010

x1x200 01 11 10

a

b

c

s

a a

ab b

b

b

c c

c

d

d

a = y1y2 = 00

b = 01

c = 11

d = 10

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

( )( ) 212122

212111

yyyyxZ

yyyyxZ

++=++= Output table

Flow table

Time sequence

of outputs

10 01011111

z1z2

Output table Flow table

S

d a cd d

21©Loberg

x1x2y1y2

00

00 01 11 10

01

11 10

00 00

00 00

0101

1111 10

1010

x1x200 01 11 10

a

b

c

s

a a

ab b

b

b

c c

c

d

d

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

Flow tables10 01011111

Z1Z2 S

d a cd d

x1x2

a a d d d c b a a

y1

y2Z1

Z2

22©Loberg

Determine input variables xiDetermine all feedback loops

Determine secondary variables yiDetermine exitation variables Yi

Circuit diagram

Asynchronous Sequential Logic

Analysis of asynchronous sequential circuits

Derive Boolean functions of all exitation variables YiYi = Y( yi , xi )

Derive latch exitation table if necessary

Input sequence Output sequenceDerive transition table Output table

Flow table

23©Loberg

THE ENDTHE END

24©Loberg