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FD-SOI: how material & design
innovations enable new market
opportunities
Manuel SELLIER
Digital Electronics BU - Product Marketing Manager
IP-SoC 2018, December the 5th 2018, Grenoble
Introduction to Soitec
Nov. 2018
We design and deliver
innovative substrates
and solutions to enable
our customers'
products shaping
everyday life
“”
IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 2
› Number 1 – Largest manufacturer of engineered substrates
› Global presence – 1,100 employees worldwide
› Serving 4 high-volume markets – Smartphones, automotive,
cloud & infrastructure, IoT
› Multi-site industrial footprint – France, Singapore, China
› Industry standard – RF-SOI is in 100% of smartphones
End Product
Choosing the right base for your product
SubstrateSoil Properties
Pinot Noir, Burgundy, Cabernet Sauvignon…
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 3
Nov. 2018
Soitec’s full range of engineered substrates
across multiple segments and applications
IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 4
RF
Front-End Module
RF-SOIFor high efficient mobile
communication
Power
Power-SOIFor seamless high voltage
device isolation
Processor &
connectivity SoC
FD-SOIFor power-efficient &
flexible digital computing
with easy
analog/RF integration
Piezo on insulator
POINew engineered substrates
for filters
Photonics
Photonics-SOITo integrate high
performance photonics
devices into silicon
Imagers
Imager-SOIFor improved imager
performance in NIR
Nov. 2018
Soitec’s full range of engineered substrates
across multiple segments and applications
IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 5
Processor &
connectivity SoC
FD-SOIFor power-efficient &
flexible digital computing
with easy
analog/RF integration
AI is about transforming data into meaningful information
Nov. 2018
f ( data ) = information
f ( ) = « apple »Picture
f ( ) = « maintenance needed »Motion
Analyze
IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 6
Collect
Sensor
Act
AP
f ( ) = « Hello! »Sound
AI is increasingly sophisticated
Nov. 2018
Source: Mary Meeker’s annual Internet Trends Report
IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 7
AI inference is moving to the edge Low-power solutions are required
Nov. 2018
CloudAlready developped
(More’s Moore driven)
EdgeEmerging
Multiple techno / standards
Very EdgeFuture
Empty space for now
Source: IMEC, ITF2018
AI Inference
Sensors
IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 8
Cost
Latency / reliability
Data privacy
Power consumption
4 drivers pushing AI at the edge
AIoT (AI + IoT) sparks a new semiconductor revolution
Nov. 2018
Source: NXP Investor Day 2018
IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 9
FD-SOI – powering the AIoT revolution
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 10
i.MX RT600 crossover processors unlocking the
potential of machine learning and artificial intelligence
at the edge, are based on FD-SOI
All trademarks are the property of their respective owners and are used for reference purposes only. Use of the trademarks does not indicate approval by or association with the party who owns the trademarks.
Next generation Human Machine Interfaces powered
by AI ambient computing based on FD-SOI
Source: Synaptics CEO, GTC, September 2018
The intelligence has to move to the edge [..].Our
vision requires a few things [..]. 22FDX has that
mix of performance and power and the ability to
aggregate functions such as RF or non-volatile
memory that we are looking towards. We need
also extremely low power so the ability to do
active body biasing is very important to us.
“
”
Next generation always-on FPGA low power
machine learning inferencing (from 1mW to 1W)
based on FD-SOI
Designers need silicon that allows them to build
compact high-performance AI devices that
deliver excellent performance without violating
footprint or thermal management constraints.
Cost is also a crucial factor.
Source: Lattice white paper, May 2018
“”
Source: GF, GTC2017
Ne
utr
on
-SE
Rin
FT
/Mb
28
nm
FD
-SO
I
ST65nm
Bulk
Vendor A45nm
Bulk
ST45nm
Bulk
Vendor A28nm
Bulk
ST28nm
Bulk
ST28nm
FD-SOI
Source: ST, Shanghai FDSOI forum, 2015
FD-SOI unique features
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 11
mmWave RF-CMOSReliability
Best CMOS mmWave with
similar performance to
SiGe radios
20x Soft Error Rate
improvement vs. bulk
Source: Sugii ,Low Power El. Appl. 2014
Ultra Low Voltage Body Bias
Operation at minimum
energy point (<0.4V)
Up to 7X energy
efficiency gains at ULV
Energy efficiency needs dynamic power/ leakage
optimization techniques
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 12
Ultra Low Power
Energy Efficiency
Dynamic Power/ Leakage needs to
be optimized real time
BestTypical
Worst
Improved Energy Efficiency
Pow
er
Frequency
Variations need to be mitigated for
optimized energy efficiency
Energy efficiency needs dynamic power/ leakage
optimization techniques
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 13
Ultra Low Power
Energy Efficiency
Dynamic Power/ Leakage needs to
be optimized real time
BestTypical
Worst
Improved Energy Efficiency
Pow
er
Frequency
Variations need to be mitigated for
optimized energy efficiency
Variations impact energy efficiency
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 14
Power
Frequency
Best
Typical
Worst
Higher Energy Efficiency
Actual chip spec
Variations impact energy efficiency
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 15
Power
Frequency
BestTypical
Worst
Improved Energy Efficiency
Compensation techniques are key
to boost energy efficiency
Static AVS is commonly used in advanced technology
nodes but faces severe drawbacks
Performance and power towards TT corner
Nov. 2018 16
Power
SS_Vmax
FF_Vmin
TT_Vnom
+10% speed
-20%
power
Process Voltage Vfloor Speed Power Aging
Slow High High Typical Typical High
Typical Typical Typical Typical Typical Typical
Fast Low Low Typical Typical Low
ST, ITC 2017 – Mhira and Huard, Best Paper award
Aging is degraded
Vfloor is increased (less room for overdrive)
Temperature compensation is very difficult
(too sensitive). Vdd not the right lever.
More complex voltage regulators required
IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec
Energy efficiency needs dynamic power/ leakage
optimization techniques
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 17
Ultra Low Power
Energy Efficiency
Dynamic Power/ Leakage needs to
be optimized real time
BestTypical
Worst
Improved Energy Efficiency
Pow
er
Frequency
Variations need to be mitigated for
optimized energy efficiency
Low Power design techniques principles
Dynamic Power : ~W.Vdd² .F
Leakage Power : ~(Vdd/L).e-Vth/S
Speed : ~W/L (Vdd-Vth)²
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 18
Enlarged LOriginal L Lgate PB 28FD
Lmin PB0 1
+4nm PB4 x4
+10nm PB10 x10
+16nm PB16 x30
ST, S3S 2017
Leakage
reduction
Multi gate lengths
Multi drive libs
Ori
gin
al W
Mo
du
late
d W
Dynamic and
Leakage reduction
SLVT LVT
Multi-Vth libs
Source: GF seminar
Clock GatingAvoid systematic toggling of Flipflops CLK pins Put logic in ClockTree to reduce active power
Power Gating
Define multi-Vdd domainsHigh Vdd only on-demandLow Vdd for low performance
Switch off unused domains
DVFS
Dynamic Voltage Frequency ScalingBenefit from V2 power savings
Landscape of low power techniques
Source Parameter Static Optimization Dynamic Optimization Static Optimization Dynamic Optimization
Dynamic
Power
W Multi-drive lib - Multi-drive lib -
Vdd Multi-Vdd lib DVS Multi-Vdd lib DVS
Vdd/Vth Multi-Vdd/Vth lib Multi-Vdd/Vth/BB lib DVBS
F Clock Gating DFS Clock Gating DFS
Leakage
Power
L Multi-L lib - Multi-L lib -
Vth Multi-Vth lib Multi-Vth/BB lib Dynamic ABB
Switch off (Vdd) - Power gating - Power gating
Variations
Consumer (Vdd) Static AVS Static AVS -
Consumer &
Auto (Vth)Static ABB Dynamic ABB
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 19
BULK (Vdd only) FD-SOI (Vdd + Vbb)
ABB boost
ABB boost
ABB static
ABB dynamic
ABB/AVS Hybrid
ABB dynamic
Body-bias: a unique solution to fully control threshold
voltage dynamically
20Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec
Landscape of low power techniques
Source Parameter Static Optimization Dynamic Optimization Static Optimization Dynamic Optimization
Dynamic
Power
W Multi-drive lib - Multi-drive lib -
Vdd Multi-Vdd lib DVS Multi-Vdd lib DVS
Vdd/Vth Multi-Vdd/Vth lib Multi-Vdd/Vth/BB lib DVBS
F Clock Gating DFS Clock Gating DFS
Leakage
Power
L Multi-L lib - Multi-L lib -
Vth Multi-Vth lib Multi-Vth/BB lib Dynamic ABB
Switch off (Vdd) - Power gating - Power gating
Variations
Consumer (Vdd) Static AVS Static AVS -
Consumer &
Auto (Vth)Static ABB (P) Dynamic ABB (T+A)
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 21
BULK (Vdd only) FD-SOI (Vdd + Vbb)
This is very unique!!
Adaptive optimization of body-bias and Vdd
› Adaptive body-bias is demonstrated on system running real SW
› Body-Bias enables dynamic power reduction thanks to supply voltage reduction
Nov. 2018 22
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
OFF 100 200 300 400 500 600FBB (mV)
CPU @ 1.2Ghz
CPU @ 1.5Ghz
-80 mV
-70 mVS
up
ply
Vo
ltag
e (
V)
HDMI1.44Kp30
Compositor
Decode4Kp30HEVC
3DGFX1080p30
Texture
ST, IRPS 2018 – Huard et al., Best Paper preselected
IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec
Combining compensation and leakage optimization
power mode
An optimum body bias / Vdd exists for
each temperature
This optimum energy point cannot be
accessed by bulk technologies
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec
-40
0
40
80120
Vdd increase & Vb decrease
Pow
er (
W)
Tem
pera
ture
(°C
)
10% activity CPU
optimum
28FDSOI Dual-Core
Application Processor
23
w/o BB
with BB
N.B. : Experimental results, ST IRPS 2016
24
Source: Dolphin Integration, 2018
> 1.5Ghz ~1Ghz 200Mhz < 50Mhz
Body Bias
Body-bias impact (AVS, ABB) on energy efficiency
En
erg
y e
ffic
ien
cy g
ain
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec
FD-SOI can increase energy efficiency
gains by 7 by leveraging
its unique body-bias capability
Typical AIoT power range
1.2X
2X
4X
7X
Body-bias enablement status in the industry
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 25
BB Type Market
Static / Boost Mobile, Consumer, Computing
Static / CompensationIoT, Automotive, Mobile, Consumer,
Computing , A&D
Dynamic / CompensationIoT, Automotive, Mobile, Consumer,
Computing , A&D
Dynamic / Boost + CompensationIoT, Automotive, Mobile, Consumer,
Computing , A&D
Partial Not Started
Key features
› Wide range of IP offering
› Standardized IPs for streamlined SoC integration
› Scalable according to SoC complexity
› Workable with third-party silicon IPs
› Built-in safety features to prevent SoC failures
› Based on silicon proven IP architectures
A complete power management IP plateform…
Power
Island#1
Power
Island#2
IOsPower
Island#3
Voltage
Regulators(LDO/DC-DC)
Po
we
r
Ga
ting
Po
we
r
Ga
ting
Po
we
r
Ga
ting
Po
we
r
Ga
ting
PMU/ACU
monitor monitor
monitor monitor
Up to 5.5 V
input
voltage Down to
0.6 V
SoC
Current Dolphin Integration Solution :
Enablement of advanced SoC power architecture to bridge the complexity gap
Vdd modulation
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 26
… to make body-biasing easy
FD-SOI project – going-on :
Enablement of Adaptive Body Biasing as turnkey solution for best Energy Efficiency without risks
Vdd + Vbb modulation
Power
Island#1
Power
Island#2
IOsPower
Island#3
Voltage
Regulators(LDO/DC-DC)
Po
we
r
Ga
ting
Po
we
r
Ga
ting
Po
we
r
Ga
ting
Po
we
r
Ga
ting
monitor monitor
monitor monitor
Up to 5.5 V
input
voltageDown to
0.4 V
SoC
BB g
en
BB g
en
BB g
en
BB g
en
Nov. 2018 IP-SoC Grenoble 2018 Soitec Proprietary Copyright @ 2018 Soitec 27
PMU/ACU
Key evolutions
› Enhanced Power Management IP Platform Vdd+Vbb
› Fully integrated Power Management IP platform
› Automatic reach of Optimum Energy Point
› Regulation loop for P, V, T & A compensation
› Workable with any standard-cell library & memory
› Design methodology & support
Enabling our customers’ products shaping everyday life
with engineered substrates
Nov. 2018
› SOITEC is innovating through substrate technologies
bringing solutions to tomorrow technology disruptions
› AI and AIoT will be at the heart of the next human
revolution and is moving closer to the edge
› FD-SOI offers unique power efficiency advantages though
body bias technologies
› FD-SOI adoption in AIoT is ongoing and will play an
increasing role in enabling this new technology disruption
Global CEO Summit Soitec Proprietary Copyright @ 2018 Soitec28
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