adsp 2181 architecture and pin diagram - alok kumar basic system figure on the next slide shows a...
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Computational Units: Every processor in the ADSP-2100 family contains three independent, full function computational units: an arithmetic/logic unit (ALU), a multiplier/accumulator (MAC) and a barrel shifter.
Address Generators & Program Sequencer:Two dedicated data address generators and a powerful program sequencer ensure efficient use of the computational units.
Buses:The processors have five internal buses.
On-chip Peripherals :
Serial Ports:Most ADSP-21xx processors have two bi-directional, double-buffered serial ports (SPORTs) for serial communications.
Timer:The programmable interval timer provides periodic interrupt generation.
21XX CORE
Host Interface Port (ADSP-2111, ADSP-2171, ADSP-21msp5x):The host interface port (HIP) is a parallel I/O port that allows for an easy connection to a host processor.
DMA Ports (ADSP-2181):The ADSP-2181 contains two DMA ports, and Internal DMA Port and a Byte DMA Port.
ALU Input/Output Registers
The sources of ALU input and output registers are shown below.
MR0, MR1 and MR2 are multiplier/accumulator result registers; SR0 and SR1 are shifter result registers.
MAC Operations
Standard Functions
The functions performed by the MAC are:
MAC Input/Output Registers
The sources of MAC input and output are:
BARREL SHIFTERThe shifter provides
a complete set of
shifting functions for
16-bit inputs,yielding
a 32-bit output.
ADSP 2181 FEATURES
Performance
25 ns Instruction Cycle Time from 20 MHz Crystal
@ 5.0 Volts
40 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle
Multifunction Instructions
Power-Down Mode
Integration
ADSP-2100 Family Code Compatible, with Instruction Set Extensions
80K Bytes of On-Chip RAM, Configured as 16K Words On-Chip Program memory RAM, 16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead Looping
Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
System Interface
16-Bit Internal DMA Port for High Speed Access to On-Chip Memory
4 MByte Memory Interface for Storage of Data Tables and Program Overlays
8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals
Programmable Wait State Generation
Two Double-Buffered Serial Ports
Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System Signaling
ICE-Port™* Emulator Interface Supports Debugging in Final Systems
ADSP-2181 BASIC SYSTEM
Figure on the next slide shows a typical basic system configuration with the ADSP-2181, two serial devices, a byte-wide EPROM and optional external program and data overlay memories.
Programmable wait state generation allows the processor to interface easily to slow peripheral devices. The
ADSP-2181 also provides four external interrupts and two serial ports or six external interrupts and one serial port.
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