alan j. drake 1 , xiaobin yuan 2 , pawel owczarczyk 2 , marshall tiner 2
DESCRIPTION
Accurate Model-to-Hardware Simulation Methodology for Designing Critical Path Monitors over a Wide Voltage Range. Alan J. Drake 1 , Xiaobin Yuan 2 , Pawel Owczarczyk 2 , Marshall Tiner 2. 1 IBM Research 2 IBM System and Technology Group. Introduction. - PowerPoint PPT PresentationTRANSCRIPT
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DAC User Track June 6, 2013
Accurate Model-to-Hardware Simulation Methodology for Designing Critical Path Monitors over a Wide Voltage Range
Alan J. Drake1, Xiaobin Yuan2, Pawel Owczarczyk2, Marshall Tiner2
1IBM Research2IBM System and Technology Group
DAC User Track June 6, 2013
Introduction
DVFS control systems need real-timing timing margin information
Critical path monitors must provide accurate timing measurements across a wide voltage and frequency range– Accurate static timing to check for early and
late mode failures insufficient– High accuracy simulations of extracted netlists
are costly
Developed a method to design a CPM that meets operating ranges while minimizing simulation time.
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Delay Elements for Fine and Coarse Delay Control
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Critical Path Monitor Overview
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Multiple synthesispaths
to mimiccritical paths
Calibration delay
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Calibration Delay
Coarse delay block equal to sum of fine delay blocks
Muxes combine delay into continuous range
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Tuning Methodology
Hierarchical simulation– Fine delay lines only– Synthesis paths without
control
Multiple runs required– 4 paths– 2 guardband
frequencies– 3 operating points:
powersave, nominal, and turbo
– multiple process corners6
Design Data
Extraction
Simulation
Compare to target
=Update designy
n
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Extraction and Simulation Hierarchical
– Control: 10724 transistors– Custom synthesis block: 5257 transistors
Extraction– Full coupling for power and noise analysis– Reduced coupling for timing
Simulation– Spice
• Slow (6hrs, 34mins) but flexible for all possible corners• Accuracy dependent on extraction
– Static timing • Fast (50 minutes)• Very accurate at 2 points: early and late mode timing
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CPM0 Path1Low-Vt
CPM0 Path2
Low-Vt Wire
CPM0 Path3Mid-Vt
CPM0 Path4
High-Vt
More delay
Less delay
Calibration delay at multiple voltage and temperature points– 4 chips tested– 4 paths per CPM, 5
CPMs per core, up to 8 cores per chip
13 delay step spread
Heavy, steady-state workload
Dark blue: 0.9V, 50C
Magenta: 1.1V, 60C
Cyan: 1.3V, 60C
Yellow: 1.3V, 80C
HW1: Static Timing Only
Target delay
Occ
urr
en
ce
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0 3 6 9 12 15 18 210
1000
2000
3000
4000
5000
6000
7000
high-Vt inv mid-Vt invlow-Vt wire low-Vt inv
Calibration Delay Setting:Low Frequency Parts
Occu
rren
ce
Calibration delay at multiple voltages
More than 20 parts tested
High-Vt distribution shifts right and lines up with Low-Vt inverter
Low-Vt distributions shift left
Mid-Vt distribution shifted right
HW2: Static Timing Only After Adjusting for Path Offsets
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HW2: Bit-to-bit Calibration Delay Spreads All Operating Points
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-228%-162% -95% -28% 38% 105% 172% 238% 305% 372%0
50
100
150
200
250
0to1 1to2 2to3 3to4 4to5 5to6 6to77to8 8to9 9to10 10to11 11to12 12to13 13to1414to15 15to16 16to17 17to18 18to19 19to20 20to2121to22 22to23 23to24 24to25 25to26 26to27 27to2828to29 29to30 30to31
% Change From Nominal
Cou
nts Inverter Coarse
Delay
Interpolating Delay
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Simulated Range with More Detailed Extraction:Full Frequency Range
fmax2
0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.20.5
0.75
1
1.25
1.5
targetpath 1path 2path 3path 4ST
Minimum Insertion Delay
Normalized Voltage
No
rmal
ized
Fre
quen
cy
0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.20.5
0.75
1
1.25
1.5
targetpath 1path 2path 3path 4ST
Maximum Insertion Delay
Normalized Voltage
No
rmal
ized
Fre
quen
cy
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Simulated Tuning and Sampling Step Sizes
0.75 V 3s 1 V 3s
Coarse Interface 1.5% 1.3% 1.25% 0.4%
Fine 1.5% 0.5% 1.25% 0.2%
0.75 V 3s 1 V 3s
Bit-to-bit 1.18% 0.3% 1.29% 0.1%
Edge Detector
Tuning delay
• Normalized to nominal cycle time• Includes fine delay and interface
between course step and fine step
• Normalized to nominal cycle time
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Conclusion
Single tool simulation insufficient to guarantee accuracy required over process, corners, and guardband
Hierarchy needed to keep simulation times reasonable
Mix of extraction and simulation environments essential
Accurate capacitive coupling extractions necessary to accurately predict small frequency differences in delay elements
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