AIDA design reviewDavide Braga

Steve Thomas

ASIC Design Group

9 January 2008

9 January 2008 AIDA design review 2

Design status from September 2007

Analogue design progress:

Effect of limited front-end gain

Amplifier optimisation for

high gain

wide output swing

linearity

Next steps:

Final analogue design

Digital gate-level design

Top-level integration and layout

Overview

9 January 2008 AIDA design review 3

Top-level digital design implemented (based on ERD)

Provides control of

• power-on reset, reset of peak-hold/comparator

• peak-hold gating

• sparse read-out, address generation

Design needs to be extended for pre-amp, shaper and clamp reset.

Digital design currently on hold.

Status of digital design in September

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Status of analogue design in September:Analogue channel, with peak-hold and gating

• Functional blocks for pre-amp, shaper, peak-hold, comparator

• Blocks based on earlier designs, with some optimisation

• Original pre-amp design has relatively low open-loop gain (~5000). Low gain causes channel to channel coupling via parasitic capacitance.

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PreAmplifier

• High gain →

• Large output swing →small Cf →

• reduced input coupling effect• improved charge collection• improved linearity

• improved SNR:

• improved Slew Rate / timing performances

• small area

inf

s

in

s

VCC

Q

V

QSNR

det

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Vout=1V

Vin=-200V

A=-5000

Input coupling effect

Cable has high interstrip capacitance

Fluctuation of Vin causes coupling of charge between adjacent channels

Effect is worse than voltage step across AC coupling capacitor

A=-5000

Ccable2

CcoupCf

Cf

Vout= Vin*Ccable/Cf

Ccable1

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Input coupling effect

Response in adjacent channels to be < 0.25% FSR:

if FSR=1V, Ccoup=58pF

→ ΔV<38μV

→ AOL>35000

Input voltage for different preamplifier gain(Cf=1pF)

Two stage amplifier

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sOLf

nc QACC

CQ

)1(det

det

Charge Collection

Charge not collected from the detector:

Cdet

equivalentinput capacitance

Cf(AOL+1)QS

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Two Stage Amplifier + pMOS Source Follower

1st stage: pMOS folded cascode2nd stage: pMOS common sourceOutput stage: source follower, to provide high drive capability

•nMOS S.F.: affected by nonlinearity because of the body effect•pMOS S.F.: source connected to the bulk → good linearity

VinVref

Vout

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Corner Analysis

The amplifier’s performances must fulfil the specifications in the whole range of operating conditions:

Open loop gain: AOL>40000Stability: Phase Margin=φM>55°

Temperature: -20° <T° <+85°Supply Voltage: 3V<Vdd<3.6VProcess parameter: 45 cases

405 corner simulations,each one must present:

Example of corner analysis

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Corner Analysis

Stability issue solved by making compensation independent of process and temperature

Good stability but poor output swing, due to the big variation in the threshold voltage for some of the corners:

1.3V<Vout<1.78V

biasSF

biasCS

biasRC

inCS

inSF

fromcurrent

reference

9 January 2008 AIDA design review 12

Two Stage Amplifier + nMOS Source Follower

The output stage has intrinsic nonlinearity but, being inside the feedback loop, its effect is mitigated by the high open loop gain

Sensitivity of the overall gain to the open loop gain’s variation:

OLOLCL

OL

OL

CLAA AAA

A

A

AS CL

OL

1~1

1

nMOS Source Follower non linearity(W.Sansen: Analog Design Essentials)

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Biasing circuit

The biasing circuit doesn’t require any setting or trimmer

The same preamplifier can work with both polarities, depending only on the value of the reference input voltage Vref.

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Positive polarityVref=0.1V

62450 <AOL< 252500

AOL_ typical=162700

55.9° <φM< 78.1°φM_typical=67.4°

Negative PolarityVref=1.6V

62250 <AOL< 212600AOL_typical=130700

61.1° <φM< 77.5°φM_typical=71.5°

Results

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Vref=0.1V Results Vref=1.6V

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Results

Between the two extreme operating points (Vref=0.1V and Vref=1.6V), the preamplifier has better performances

→good stability

DC gain

Phase MarginFor instance, for the middle range value:

Vref=0.85V

79700 <AOL< 263500AOL_typical=167500

59.4° <φM< 79.1°φM_typical=71°

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Feedback Capacitor

Output swing: from 0.1V to 1.6V → ΔVoutMAX=1.5V

pF6.05.1

C108.8 13

VV

QC

C

QV

f

f

C108.8C106.1V6.3

MeV20 1319 Q

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Linearity

The linearity of the preamplifier (loaded by an ideal shaper) has been measured sweeping the value of the input current

Input Current Amplifier Output

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Linearity (Vref=0.1V)

The highlighted event is a simulation inaccuracy due to error propagation.

Nevertheless, the integral non linearity is <0.04% over a wide range of 1.5V

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Linearity (Vref=1.6V)

The highlighted event is a simulation inaccuracy due to error propagation.

Nevertheless, the integral non linearity is <0.09% over a wide range of 1.5V

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Input Voltage Step

The high open loop gain limits the voltage step on the input node, anyway a voltage spike is always present because of the finite bandwidth of the amplifier.

Its magnitude is strongly dependant on the collection time of the detector.

Collection time=410ns Collection time=110ns

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Next steps:

• Amplifier optimisation based on measured detector response (plasma model for detector)

• Investigation of polarity switching

• Top-level control circuit design

• Physical layout

• Target of April for design submission?