advanced digital logic design – eecs...

Advanced Digital Logic Design – EECS 303

http://ziyang.eecs.northwestern.edu/eecs303/

Teacher: Robert DickOffice: L477 TechEmail: [email protected]: 847–467–2298

http://ziyang.eecs.northwestern.edu/eecs303/

Combinational testingSequential testing

YieldFault modelsCombinational test generation

Outline

1. Combinational testing

2. Sequential testing

2 Robert Dick Advanced Digital Logic Design



Introduction to testing

After fabrication, some circuits don’t work correctly

Determining which circuits contain faults requires testing

Testing some types of circuits is easy, testing others is difficult

One can use automation to help solve this problem




Introduction to testing

Determining the best way to test large circuits requiresautomation

Building large circuits that are easy to test also requiresautomation

Testing it spans all design, from system to physical level

Today, I’ll introduce some classical ideas at the logic level




Section outline

1. Combinational testingYieldFault modelsCombinational test generation




Yield

Yield, y , is the fraction of fault-free products

Test fault coverage, c , is the fraction of faults that the set ofapplied tests detects

Low-yield is expensive because fabrication capacity is wasted

Defect level, d , is the fraction of parts containing undetectedfaults

d = 1− y1−c

A high defect level is extremely expensive because it meanscircuits make their way into products, or worse, to consumers,before faults are discovered




Defect level

Example acceptable defect level: ∼ 0.0002

Either yield must be very high or fault coverage must be very high

d × 10-6

0.5 0.6 0.7 0.8 0.9 1

y

99 99.2 99.4 99.6 99.8

100

c (%)

0 100 200 300 400




Section outline





Faults and failures

A fault is a physical defect in a circuit

A failure is the deviation of a circuit from its specified behavior

Faults can cause failures but they don’t always cause failures




Functional testing

No assumptions about types of fault

No assumptions about structure or properties of Circuit UnderTest (CUT)

The CUT is a black box that is checked to determine whether itresponds to all (or most) input (sequences) as specified

However, ignoring structural information makes testingunnecessarily slow




Structural testing

Use information about the specific CUT

Types of faults that are likely to occurStructure of circuit




Fault models

zb

a

VDD

za

b

VDD

VSS




Fault models

bridgingfault

zb

a

VDD

za

b

VDD

VSS




Fault models

zb

a

VDD

za

b

VDD

VSS




Fault models

stuck−openfault

zb

a

VDD

za

b

VDD

VSS




Fault models

zb

a

VDD

za

b

VDD

VSS




Fault models

stuck−at

fault

zb

a

VDD

za

b

VDD

VSS




Fault models

zb

a

VDD

za

b

VDD

VSS




Singe stuck-at faults

One of the simplest and most common fault models

S-a-0: Stuck-at 0S-a-1: Stuck-at 1

Relies on digital reinforcement

0.8 · VDD is 1 · VDD one logic stage laterS-a-0.8 ≈ s-a-1

For two-level logic, exhaustive test set for single stuck-at faultswill detect all multiple stuck-at faults, too

Doesn’t hold for multi-level logic




Single stuck-at faults

Consider a NAND3 gate

Inputs faultz

A B C freea b c z

0 1 0 1 0 1 0 1

0 0 0 1 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 0 10 1 0 1 1 1 1 1 1 1 0 10 1 1 1 1 0 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 0 11 0 1 1 1 1 1 0 1 1 0 11 1 0 1 1 1 1 1 1 0 0 11 1 1 0 1 0 1 0 1 0 0 1






Inputs faultz

A B C freea b c z

0 1 0 1 0 1 0 1

0 0 0 1 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 0 10 1 0 1 1 1 1 1 1 1 0 10 1 1 1 1 0 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 0 11 0 1 1 1 1 1 0 1 1 0 11 1 0 1 1 1 1 1 1 0 0 11 1 1 0 1 0 1 0 1 0 0 1

Too expensive to use 2n inputs (23 = 8 in this case)






Inputs faultz

A B C freea b c z

0 1 0 1 0 1 0 1

0 0 0 1 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 0 10 1 0 1 1 1 1 1 1 1 0 10 1 1 1 1 0 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 0 11 0 1 1 1 1 1 0 1 1 0 11 1 0 1 1 1 1 1 1 0 0 11 1 1 0 1 0 1 0 1 0 0 1

Unate covering again




Fault coverage

A test of all possible inputs for a NANDn gate will require 2n

tests

Applying all possible tests (or sequences of tests) for complexcircuits isn’t practical

However, for all NANDn gates, all single stuck-at faults (andimplicitly multiple stuck-at faults) can be tested using only n + 1tests




Fault equivalence

The function of the circuit is identical in the presence of eitherfault

E.g., any input of a NAND gate being s-a-0 or the output beings-a-1 → output of 1

In general, identifying equivalent faults, or fault collapsing isdifficult

However, can use knowledge about gates, and connectivities, tofind most equivalent faults




Fault equivalence


Inputs faultz

A B C freea b c z

0 1 0 1 0 1 0 1

0 0 0 1 1 1 1 1 1 1 0 10 0 1 1 1 1 1 1 1 1 0 10 1 0 1 1 1 1 1 1 1 0 10 1 1 1 1 0 1 1 1 1 0 11 0 0 1 1 1 1 1 1 1 0 11 0 1 1 1 1 1 0 1 1 0 11 1 0 1 1 1 1 1 1 0 0 11 1 1 0 1 0 1 0 1 0 0 1

Equivalent faults




Other fault models

∼ 2/3 CMOS faults are not stuck-at faults

Luckily, stuck-at fault tests often detect them

More advanced faults models

Allow higher theoretical coverageAre more complicated

In this lecture, we only have time to cover stuck-at-faults




Section outline





Test generation

Can use algorithms to automatically generate a test for a specificfault

Problem: Identify some test, t, such that the output of thecircuit will deviate from its specified value if a particular fault, f ,is present

Excitation: Need to propagate a value to stuck-at fault that iscontrary to the fault value

Sensitization: Need to propagate the faulty value to an output ofthe circuit




Excitation and sensitization

s−a−0

s−a−0

111

excitation

s−a−0

0

1

0

111

sensitization

s−a−0

0

1

0

111

sensitization

s−a−0

0

1

0

111

sensitization

0




Excitation and sensitization

s−a−0s−a−0

111

excitation

s−a−0

0

1

0

111

sensitization

s−a−0

0

1

0

111

sensitization

s−a−0

0

1

0

111

sensitization

0




Backtracking

111

s−a−0

not sensitized

0

1

0

1

1

1

s−a−0

111

s−a−0

01

0

sensitized

111

s−a−0

01

0

sensitized




Automatic Test Pattern Generation (ATPG)

Can automatically determine test for a particular fault

Boolean difference

Generally considered too slow for use on large circuitsEasy to understand

Excitation/sensitization based methods (D-algorithm)




Boolean difference

i1i2

i3z

In the presence of the fault, function is i3XOR faulty and specified functions




Boolean difference

s−a−0i1i2

i3z

In the presence of the fault, function is i3

XOR faulty and specified functions




Boolean difference

δ

i1i2

i3

In the presence of the fault, function is i3

XOR faulty and specified functions




Boolean difference

If the resulting function is 0, the fault can not be identified

If the resulting function is 1, the fault can be identified

Use a test that satisfies (sets to 1) the function




Boolean difference

0

1

00 01 11 10

1

1

1

1

00

0 0

0

1

00 01 11 10

0 0

00 11

1 0

0

1

00 01 11 10

1

1

1

1

00

0 0

0

1

00 01 11 10

0 0

00 11

1 0

0

1

00 01 11 10

1

1

1

1

00

0 0

0

1

00 01 11 10

1

00

0

0

0

0

0

0

1

00 01 11 10

0 0

00 11

1 0

0

1

00 01 11 10

1

1

1

1

00

0 0

0

1

00 01 11 10

1

00

0

0

0

0

0

0

1

00 01 11 10

0 0

00 11

1 0




D-algorithm

We have seen that, in order to test for a particular fault, we must

Excite the faultSensitize a path from the fault to the output

The D-algorithm is an automated method of finding a test thatexcites a fault and sensitizes a path to the circuit output

J.P. Roth, IBM, 1966




Roth’s extension to Boolean algebra

α/β

α is the fault-free valueβ is the value in the presence of the fault

0/0 = 0

1/1 = 1

1/0 = D0/1 = DX/X = X




(N)AND D-cubes of failure

detection D-cube of failuregate input z

a b a b z

AND 1 1 s-a-0 1 1 D0 X s-a-1 0 X DX 0 s-a-1 X 0 D

NAND 1 1 s-a-1 1 1 D0 X s-a-0 0 X DX 0 s-a-0 X 0 D




(N)OR D-cubes of failure


a b a b z

OR 0 0 s-a-1 0 0 D1 X s-a-0 1 X DX 1 s-a-0 X 1 D

NOR 0 0 s-a-0 0 0 D1 X s-a-1 1 X DX 1 s-a-1 X 1 D




(N)AND D-cubes of propagation

input AND NANDa b z z

1 D D D1 D D DD 1 D DD 1 D DD D D DD D D D




(N)OR D-cubes of propagation

input OR NORa b z z

0 D D D0 D D DD 0 D DD 0 D DD D D DD D D D




D-algorithm

1 Initially, all the lines in the circuit are X (Don’t Care)

Left blank in example

2 A gate with an input of D or D and an output of X belongs tothe frontier

3 An element whose assigned inputs do not imply the output isunjustified

4 We want to drive the frontier to a circuit output (sensitize). . .

5 . . . and justify the gate inputs (excite)




D-algorithm overview

no

done

yes

choose D-cubeof failure toexcite fault

sensitize pathto output

justify gates

conflicts? Backtrack


D-algorithm

Select a D-cube of failure to excite the faultwhile frontier has not yet reached an output do

Perform the implications of the most recent assignmentif the frontier is empty then

Backtrackend ifChoose a signal, s, s.t. s can’t reached from the faultAssign s to a value in order to propagate the fault forward

end whilefor each unjustified line, l do

if l can be justified thenJustify l

elseBacktrack

end ifend forA test has been found



D-algorithm notes

There are a few details not explained in the pseudocode

Signals should be selected in order to drive the frontier forward

Backtracking is the action of backing up and taking the closestpreviously unexplored branch in the decision tree




D-algorithm example

i1i2i3

i4

i5

z




D-algorithm example

s−a−1

i1i2i3

i4

i5

z




D-algorithm example

i1i2i3

i4

i5 0/1 = D

z




D-algorithm example

D

i1i2i3

i4

i5

z




D-algorithm example

0

1

D

i1i2i3

i4

i5

z




D-algorithm example

0

1

D

1

i1i2i3

i4

i5

D

z




D-algorithm example

0

1

D

1

0

i1i2i3

i4

i5

D

Dz




D-algorithm example

Conflict!

0

1

D

1

0

i1i2i3

i4

i5

D

Dz




D-algorithm example

0

1

D

1

0

i1i2i3

i4

i5

D

Dz




D-algorithm example

0

1

D

1

i1i2i3

i4

i5

D

z




D-algorithm example

0

1

D

i1i2i3

i4

i5

z




D-algorithm example

D

i1i2i3

i4

i5

z




D-algorithm example

D

1

0

i1i2i3

i4

i5

z




D-algorithm example

D

1

1

0

i1i2i3

i4

i5

D

z




D-algorithm example

D

1

0

1

0

i1i2i3

i4

i5

D

Dz




D-algorithm example

D

1

0

1

0

10

i1i2i3

i4

i5

D

Dz




D-algorithm example

D

1

0

1

0

10

1

i1i2i3

i4

i5

D

Dz




NOR D-cubes of failure


a b a b z

NOR 0 0 s-a-0 0 0 D0 1 s-a-1 0 1 D1 0 s-a-1 1 0 D1 1 s-a-1 1 1 D




AND D-cubes of propagation

input ANDa b z

1 D D1 D DD 1 DD 1 DD D DD D D




NOR D-cubes of propagation

input NORa b z

0 D D0 D DD 0 DD 0 DD D DD D D




NOR D-cubes of failure


a b a b z

NOR 0 0 s-a-0 0 0 D0 1 s-a-1 0 1 D1 0 s-a-1 1 0 D1 1 s-a-1 1 1 D




D-algorithm summary

If a test for a fault exists, guaranteed to generate it

Full backtracking

However, much faster than Boolean difference




Caveats

This lecture has only introduced some topics in testing

If you intend to do research in this area, take a few courses ontesting

Single stuck-at fault model is becoming obsolete




Caveats

D-algorithm is actually more complicatedAvoiding backtracking is important for performance

ImplicationsHeuristics to make best decisions first

Should understand derivation of D-cubes for arbitrary fault models




D-algorithm reference

Stanley Hurst. VLSI Testing: Digital and Mixed Analogue/DigitalTechniques. Institution of Electrical Engineers, U.K., 1998

This is one of the better references in the library

Beware: The D-algorithm examples contain small errors




CAD survey reference

Melvin A. Breuer, Majid Sarrafzadeh, and Fabio Somenzi.Fundamental CAD algorithms. IEEE Trans. Computer-Aided Design ofIntegrated Circuits and Systems, 18(12):1449–1475, December 2000

Recommended by a student

Introduces a number of important logic-level and physical-levelCAD algorithms

A useful supplement to the material in Hachtel and Somenzi’s,and Sherwani’s books

Introduces the D-algorithm



D-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability

Outline

1. Combinational testing

2. Sequential testing




Section outline

2. Sequential testingD-algorithm reviewRedundancy eliminationSequential testingDesign/synthesis for testability




D-algorithm review

Given a fault, the D-algorithm will generate a test for that fault

Selects a D-cube of failure to excite the fault

Propagates a D value to the circuit outputs be selection D-cubesof propagation for gates

Justifies gate inputs

Uses full backtracking on D-cubes of failure and gate justification




Fault simulator

Fault simulation is the process of determining which faults a testdetects

Test generation is complicated and time-consuming

Fault simulation is quick




Test sequence generation

The D-algorithm gives us a way to generate a test for a given faultHowever, we need a sequence of tests for all (or most) faults

Determine all stuck-at faults for the circuitEliminate equivalent faultswhile untested faults remain do

Pick a fault and use an ATPG to generate a testAppend the test to a listUse a fault simulator to determine all faults the test detectsEliminate detected faults

end while





However, this approach can still be too expensive

Recall

Fault simulation is fastATPG is slow

Take advantage of fault simulator





while fault coverage is less than 90% doGenerate a random pattern – extremely fastUse a fault simulator to determine if new faults are detectedif so then

Append pattern to a listEliminate detected faults

end ifend whilewhile fault coverage is less than 99.5% do

Pick a fault and use an ATPG to generate a testAppend the test to a listUse a fault simulator to determine all faults the test detectsEliminate detected faults

end while




Section outline





Redundancies

Sometimes a s-at-0 fault can’t be detected

Implication: Given any set of inputs to the circuit, that node canbe set to 0 and the output will match the specifications

Converse for s-a-1 faults

Even if a portion of the circuit is not able the switch, the samefunction is realized

The presence of an undetectable fault implies redundancy

How can the D-algorithm can be used to simplify logic?




Redundancies

Logic terminating in the location of the stuck-at fault can be removedfrom the circuit and the same function will be realized

Conventional wisdom suggests removal

Simplify logicMake circuit more fully testable




Redundancy example

a

b

z




Redundancy example

s-a-0a

b

z




Redundancy example

s-a-0

Excite: a 6= b

a

b

z




Redundancy example

s-a-0

Excite: a 6= bSensitize: a = b = 0

a

b

z




Redundancy example

s-a-0


a

b

z

Can’t excite and propegate faulty value to z!




Redundancy example

s-a-0


Replace s-a-0 logic with 0

0

a

b

z





Redundancy example

s-a-0



Eliminate unused logic

0

a

b

z





Redundancy example



Simplify logic

Eliminate unused logic

a

b

z





ATPG for logic simplification

Can use ATPG algorithm to simplify logic

1 Find a fault that is untestable due to redundancy

2 Remove the redundant logic

3 Repeat




Redundancy removal not always safe

Logical equivalence may not imply true equivalence

What happens if redundancy is intentional?

To reduce power consumptionTo ensure signal stability for use in asynchronous circuits

Removal can

Increase powerIntroduce races




Section outline





Sequential testing

Can convert to a version of combinational testing

Iterative array expansion

Simulation-based





Make a copy of the combinational logic for each time step

However, now the problem converts ATPG for multiple faults

Iterative array expansion increases the size of the combinationalproblem

More importantly, changes the required fault model

Requires ATPG for multiple faults





D Q

QC

i4

i1

i3

i2

z

c





s−a−0

D Q

QC

i4

i1

i3

i2

z

c





1

s−a−0

D Q

QC

i4

i1

i3

i2

z

c

i04

i01

i03

i02

z0





1

s−a−0

s−a−0

D Q

QC

i4

i1

i3

i2

z

c

i14

i11

i13

i12

z1

i04

i01

i03

i02

z0




Modified D-algorithm for iterative array

Propagate D-frontier forward

Generate new time frames as necessary

Propagate gate justification backward

Generate new time frames as necessary

However, this algorithm is not certain to find a test if one exists

Roth’s algebra not suited to sequential circuits




Muth’s 9-valued logic

D-algorithm can’t adequately model the possible states insequential circuits

Repeated effect of fault can’t be modeled

Roth’s values

0/0, 0/1 (D ), 1/0 (D), 1/1, X/X

Muth’s values

0/0, 0/1, 0/X, 1/0, 1/1, 1/X, X/0, X/1, X/X




Simulation-based sequential testing

Generate a vector

Determine whether that vector brought the circuit state nearer toor farther from fault excitation and sensitization

If the state moved near to detection, append the pattern to a list

Many of the probabilistic optimization algorithms in the thirdlecture can be applied for simulation-based testing





abc





s−a−1

abc





s−a−1

abc

What if a, b, and c are state variables?





0

10

1

0

0

00

1

1

s−a−1

000 101

111001

110

abc






0

10

1

0

0

00

1

1

011?

s−a−1

000 101

111001

110

abc






10

0

10

1

0

0

00

1

1

s−a−1

011000 101

111001

110

abc





Sequential test generation problems

Sequential test generation intractable for large circuits

Some continue to work on improving test generation

Others modify circuit structure to make test generation easier. . .




Section outline





Scan-based design for test (DFT)

If testability is considered during design or synthesis, can bemade easy

Instead of forcing ATPG to deal with synchronous testing, inserta scan chain

Chain together (all) flip-flops and scan through an input if andonly if a testing input is activated




Scan D flip-flop

C

Q

DQ




Scan D flip-flop

TD

S




Scan D flip-flop

C

Q

TD Q

S




Scan D flip-flop

to next flip−flopfrom previous flip−flopC

Q

TD




Scan D flip-flop

testing logic overhead

to next flip−flopfrom previous flip−flopC

Q

TD




Scan D flip-flop

testing logic overhead

testing routing overhead

to next flip−flop

testing routing overhead

from previous flip−flopC

Q

TD




Full scan

Greatly simplifies testing

Converts sequential testing to combinational testing

Testing can be slow if I/O pins limited

Significantly increases chip area and price

More complicated flip-flopsMore complicated routingI/O requirements, especially if speed required




Scan chain

serial scan input

test mode

clock

combinational logic

serial scan outputQ

C

D

T

S

Q

C

D

T

S

Q

C

D

T

S

Q

C

D

T

S




Level-sensitive scan design (LSSD)

Less delay than scan-path during normal operation

Used commercially, especially within IBM

Pre-processing step replaces all latches with LSSD latches

Other companies have related testing approaches

Scan path – NECScan/set – Sperry UnivacRandom access scan – Fujitsu




LSSD

TCtest1

Ctest2

D

Cnormal

L1

L1

L2

L2




LSSD

TCtest1

Ctest2

D

Cnormal

L1

L1

L2

L2

level sensitive D flip-flop




LSSD

TCtest1

Ctest2

D

Cnormal

L1

L1

L2

L2






LSSD

TCtest1

Ctest2

D

Cnormal

L1

L1

L2

L2



modecontrol




LSSD

Ctest1

Ctest2

D

Cnormal

L1

L1

L2



modecontrol




Full scan disadvantages

Increased area

5%–15%

Increased delay

Depends on critical path average combinational logic depth

Slow when implemented serially

Need to serially clock through every register in IC

High pin requirements to speed up




Partial scan

Instead of scanning all latches, scan a subset

Need to carefully select scanned latches based on

Test coverage effectsTesting speed




Advanced DFT/SFT techniques

Testing core-based systems-on-chip (SoC)

Related to board-level boundary-scan

Fault injection

Reliability evaluationInsert fault into system and determine reaction

RTL synthesis for testability

Software fault modeling and testing

Extremely difficult problem




Personal observations on testing

Despite continued research on advanced testing techniques,industry continues to use full-scan

In order for industry to accept a more complicated testingtechnique, the advantages must be tremendousCompanies don’t like complexity

Testing is a fairly mature field

Some people in academia have shifted their interest away fromtesting

It remains a huge practical problem for industry




Personal observations on testing

Companies don’t want increased complexity

Researchers want to see their ideas used

Therefore, reduction in interest in testing among researchers

Therefore, reduction in interest in testing among companies

However, companies still have huge testing problems

Therefore, high demand for MS and Ph.D. graduates with testingexperience

One option: target a research problems involving testing and anotherarea, e.g., synthesis




Testing summary

Low defect rate requires high test coverage

Functional testing requires too many patterns

Use structural testing based on a fault model, e.g., single stuck-at

Can use fault equivalence to reduce patterns

Can automatically generate a test for a specific fault

Combine ATPG with fault simulator to generate a set of testswith high coverage




Testing summary

Can use ATPG for logic simplification – redundancy

Sequential testing difficult for large circuits

Use DFT to make testing easier

Use design automation to make DFT easier




Sequential testing references

Sujit Dey, Anand Raghunathan, and Rabindra K. Roy.Considering testability during high-level design. In Proc. Asia &South Pacific Design Automation Conf., February 1998

Survey on high-level design/synthesis for test techniques

Kwang-Ting Cheng. Gate-level test generation for sequentialcircuits. ACM Trans. Design Automation Electronic Systems,1(4):405–442, October 1996

Survey on sequential test generation


advanced digital logic design – eecs...

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