advanced digital design
DESCRIPTION
Reconfigurable Logic. Advanced Digital Design. by A. Steininger and M. Delvai Vienna University of Technology. Outline. Introduction Reconfigurable Logic Issues Conclusion Research plans. … in the `40s. Problem: How can we use the same hardware platform for different applications ? - PowerPoint PPT PresentationTRANSCRIPT
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Advanced Digital DesignAdvanced Digital DesignReconfigurable LogicReconfigurable Logic
by A. Steininger and M. DelvaiVienna University of Technology
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OutlineOutline
Introduction Introduction
Reconfigurable Logic IssuesReconfigurable Logic Issues
ConclusionConclusion
Research plansResearch plans
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… … in the `40s in the `40s
Problem: Problem: How can we use the same hardware How can we use the same hardware platform for different applications ?platform for different applications ?
Answer: Answer: Microcontroller concept: Map each Microcontroller concept: Map each application to the same instruction set application to the same instruction set
This is an extremly flexible, but also This is an extremly flexible, but also an ineffiecient approach an ineffiecient approach
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A New Paradigm A New Paradigm
Reconfigurable hardware allows to Reconfigurable hardware allows to tailor the same hardware to individual tailor the same hardware to individual applications „on the fly“: applications „on the fly“:
TechniquesTechniques used for software used for software development can be applied to development can be applied to hardwarehardware
Problem specific circuits allows highly Problem specific circuits allows highly efficient computationsefficient computations
Key technology Key technology FPGA FPGA
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FPGA (1)FPGA (1)
Programmable logic elementsProgrammable logic elements
Programmable interconnectsProgrammable interconnects
LE LE LE
LE LE LEprogrammable switch matrix
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Configuration memory
FPGA (2)FPGA (2)
ResultingResulting circuit circuit
LE
LE LE
LELE
LE
Inpu
ts
Outpu
ts
Configuration memory is SRAM based: „fast“ reconfiguration multiple reconfigurations possible ( > 100.000)
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Reconfigurable Logic IssuesReconfigurable Logic Issues
What
WhyWho
When
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Reconfigurable Logic IssuesReconfigurable Logic Issues
When What
Who Why
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Reconfigurable Logic IssuesReconfigurable Logic Issues
When does the reconfiguration take place ?
Once (at start-up)
Run-time reconfiguration reconfiguration is performed during normal operation
During operation
Offline reconfiguration operation stops new configuration is loaded operation continues
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Reconfigurable Logic IssuesReconfigurable Logic Issues
WhatWhen
Who Why
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WhatWhat is reconfigured is reconfigured
Configuration memory
Configuration memory
LE
LE LE
LELE
LEcfg dataLE
LE LE
LELE
LE
1) Entire FPGA
Configuration memory
Configuration memory
cfg dataLE
LE LE
LELE
LE
2) Parts of the FPGALE
LE LE
LELE
LE
3) Multi-context reconfiguration
Configuration memory
LE
LE LE
LELE
LEcfg dataConfiguration
memory
LE
LE LE
LELE
LE
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Reconfigurable Logic IssuesReconfigurable Logic Issues
Who
When What
Why
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Who reconfiguresWho reconfigures
One central controllerOne central controller ExternalExternal
New configuration can be „downloaded“ from New configuration can be „downloaded“ from outsideoutside
Internal Internal Internal controller calculates and executes the Internal controller calculates and executes the
configuration configuration
Distributed „controller“Distributed „controller“ IntelligentIntelligent
Each part of the system can decide on the need Each part of the system can decide on the need for rearrangement. for rearrangement.
Unintelligent Unintelligent Reconfiguration takes place according predifined Reconfiguration takes place according predifined
rule in response to external eventsrule in response to external events
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Reconfigurable Logic IssuesReconfigurable Logic Issues
Why
When What
Who
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Rapid Prototyping
Why ReconfigurationWhy Reconfiguration
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Rapid Prototyping (1) Rapid Prototyping (1)
First transistor (1947) Discrete devices (Mailüfterl,1958) TTL circuits -> 7400 Series (197x) Programmable Logic Devices (PLD)
PLA, PAL, CPLD
=> Antifuse, (E)EPROM
Gate Arrays -> customization only in the last fabrication step
Field Programmable Gate Arrays (FPGAs)
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Rapid Prototyping (2)Rapid Prototyping (2)
Advantage of FPGA: Short design cycles Reduce costs Design space exploration Valuable prototypes Suitable for small number of pieces Hardcopy …
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Rapid Prototyping
Save Logic Elements
Why ReconfigurationWhy Reconfiguration
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Save Logic Elements (1)Save Logic Elements (1)
Time sharing: Programmable logic Time sharing: Programmable logic can be used to implement different can be used to implement different modules in a devicemodules in a device Example: Mobile phone Example: Mobile phone
Virtualization: Programmable logic is Virtualization: Programmable logic is used to „provide“ an infinite amount used to „provide“ an infinite amount of logicof logic Compare: Physical and virtual memoryCompare: Physical and virtual memory
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Virtual Hardware: Virtual Hardware: The PipeRench Example (1)The PipeRench Example (1)
11 55443322 Virtual Circuit
Cycle 1 2 3 4 5 6 7
Stage1
Stage2
Stage3
cfg1cfg2
cfg3
exe1 exe1exe2
Mapping: 5 → 3 Pipestages
Stage1
?? ???? Physical CircuitStage2 Stage3
cfg4cfg5
cfg1
cfg2exe4
exe3
exe4
exe3
exe2 exe5 exe5
exe1
Principle:
cfg … configuration exe … execution
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Virtual Hardware: Virtual Hardware: The PipeRench Example(2)The PipeRench Example(2)
Advantages: Advantages: • Implementation of large virtual circuit in Implementation of large virtual circuit in
small physical devices small physical devices • Scalable performanceScalable performance
Limitations: Limitations: • Cycle dependency must fit in one Cycle dependency must fit in one
pipeline stagepipeline stage• Configuration must be performed in one Configuration must be performed in one
clock cycleclock cycle
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Rapid PrototypingRapid Prototyping
Save Logic ElementsSave Logic Elements
Improve PerformanceImprove Performance
Why ReconfigurationWhy Reconfiguration
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Improve PerformanceImprove Performance
Application specifics circuitsApplication specifics circuits Data driven computationData driven computation
Partial reconfigurationPartial reconfiguration
(Soft)-CPUCI
1) (Soft)-CPU + Configurable Instructions2) (Soft)-CPU + Configurable CoProcessor
C-CoP
Hardware Contex SwitchHardware Contex Switch
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Configuration Memory
Configuration Memory
Severalconfigurations in the config memory
Hardware Context SwitchHardware Context Switch
Task A
Configuration Memory
LE
LE LE
LELE
LE
Inpu
ts
Outpu
ts
Static
Task A.1 Task A.2 Task A.3CSW CSWContextswitching
time
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Rapid prototyping
Save logic elements
Improve performance
Increase fault tolerance / self
healing circuits
Why ReconfigurationWhy Reconfiguration
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Increase fault tolerance (1) Increase fault tolerance (1)
Spare programmable logic replace Spare programmable logic replace faulty compomentsfaulty compoments
RequirementsRequirements
• Error detectionError detection
• DiagnosisDiagnosis
• Replacement strategyReplacement strategy
• RecoveryRecovery
Parameters:Parameters:
• Block sizeBlock size
• Detection delayDetection delay
• Recovery timeRecovery time
• Overhead Overhead
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Increase fault tolerance (2) Increase fault tolerance (2)
Examples: Examples: FPGA based TMR FPGA based TMR Column based precompiled configuration Column based precompiled configuration
techniquetechnique
Func
tion
A
Col1
Func
tion
B
Col2
Func
tion
C
Col3
Func
tion
D
Col4
Unu
sed
Col5
Func
tion
A
Col1Fu
ncti
on B
Col2
Func
tion
C
Col4
Func
tion
D
Col5
Unu
sed
Col3
Limited changes simple rerouting
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Increase fault tolerance (3) Increase fault tolerance (3)
Example: Example: FPGA based TMR FPGA based TMR Coloum based precompiled configuration Coloum based precompiled configuration
techniquetechnique Fine-grained self healing hardwareFine-grained self healing hardware
Inpu
ts
LUTk
k
k
k
k
k
LUT
LUT
LUT
LUT
LUT
Out
putsLUT
k
k
k
k
k
k
k
XOR Fault Flag
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Global Challenges in Global Challenges in Reconfigurable ComputingReconfigurable Computing
Time required for reconfigurationTime required for reconfiguration Overhead for reconfigurabilityOverhead for reconfigurability Block sizeBlock size Configuration data: Configuration data:
Precompiled modules -> memory Precompiled modules -> memory overhead overhead
Run time generated modules–> Run time generated modules–> additional (intelligent) controlleradditional (intelligent) controller
Software toolsSoftware tools
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ConclusionConclusion
ReconfigurableReconfigurable logic changes the logic changes the traditional way to implement digital traditional way to implement digital systems:systems: Hardware is becoming flexible as Hardware is becoming flexible as
software software Arbitrarily combination of methodes Arbitrarily combination of methodes
presented in section „When, What, Who, presented in section „When, What, Who, Why“Why“
……
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Our Research Activities Our Research Activities
Asynchronous logicAsynchronous logic Optimization wrt: Optimization wrt:
Power ConsumptionPower Consumption Area OverheadArea Overhead Performance Performance
Reconfigurable logicReconfigurable logic Fault Tolerance / Self healing circuitsFault Tolerance / Self healing circuits
Combination of both research Combination of both research domainsdomains