Adder (electronics)

In electronics, an adder or summer is a digital circuit thatperforms addition of numbers. In many computers andother kinds of processors, adders are used not only in thearithmetic logic units, but also in other parts of the pro-cessor, where they are used to calculate addresses, tableindices, increment and decrement operators, and similaroperations.Although adders can be constructed for many numericalrepresentations, such as binary-coded decimal or excess-3, the most common adders operate on binary numbers.In cases where twos complement or ones complement isbeing used to represent negative numbers, it is trivial tomodify an adder into an addersubtractor. Other signednumber representations require a more complex adder.

1 Half adder

AB S

C

Half adder logic diagram

The half adder adds two single binary digits A and B. Ithas two outputs, sum (S) and carry (C). The carry signalrepresents an overow into the next digit of a multi-digitaddition. The value of the sum is 2C + S. The simplesthalf-adder design, pictured on the right, incorporates anXOR gate for S and an AND gate for C. With the additionof an OR gate to combine their carry outputs, two halfadders can be combined to make a full adder.[1]

The half adder adds two input bits and generates a carryand sum, which are the two outputs of a half adder. Theinput variables of a half adder are called the augend andaddend bits. The output variables are the sum and carry.The truth table for the half adder is:

1-bitFull

Adder

A B

CinCout

SSchematic symbol for a 1-bit full adder withCin and Cout drawnon sides of block to emphasize their use in a multi-bit adder

2 Full adderA full adder adds binary numbers and accounts for valuescarried in as well as out. A one-bit full adder adds threeone-bit numbers, often written as A, B, and C; A andB are the operands, and C is a bit carried in from theprevious less signicant stage.[2] The full adder is usuallya component in a cascade of adders, which add 8, 16, 32,etc. bit binary numbers. The circuit produces a two-bitoutput, output carry and sum typically represented by thesignals C and S, where sum = 2 Cout + S . Theone-bit full adders truth table is:

ABCin

S

Cout

Carry-block

Tc

Full-adder logic diagram

A full adder can be implemented in many dierent wayssuch as with a custom transistor-level circuit or composedof other gates. One example implementation is with S =AB Cin and Cout = (A B) + (Cin (AB)) .In this implementation, the nal OR gate before thecarry-out output may be replaced by an XOR gate with-

1

2 3 MORE COMPLEX ADDERS

out altering the resulting logic. Using only two types ofgates is convenient if the circuit is being implemented us-ing simple IC chips which contain only one gate type perchip.A full adder can be constructed from two half adders byconnecting A and B to the input of one half adder, con-necting the sum from that to an input to the second adder,connectingCi to the other input andOR the two carry out-puts. The critical path of a full adder runs through bothXOR-gates and ends at the sum bit s . Assumed that anXOR-gate takes 3 delays to complete, the delay imposedby the critical path of a full adder is equal to

TFA = 2 TXOR = 2 3D = 6D

The carry-block subcomponent consists of 2 gates andtherefore has a delay of

Tc = 2D

3 More complex adders

3.1 Ripple-carry adder

1-bitFull

Adder

1-bitFull

Adder

1-bitFull

Adder

1-bitFull

AdderC3 C2 C1 C0C4

A3 B3 A2 B2 A1 B1 A0 B0

S3 S2 S1 S0

4-bit adder with logic gates shown

It is possible to create a logical circuit using multiple fulladders to add N-bit numbers. Each full adder inputs aCin, which is the Cout of the previous adder. This kindof adder is called a ripple-carry adder, since each carrybit ripples to the next full adder. Note that the rst (andonly the rst) full adder may be replaced by a half adder(under the assumption that Cin = 0).The layout of a ripple-carry adder is simple, which al-lows for fast design time; however, the ripple-carry adderis relatively slow, since each full adder must wait for thecarry bit to be calculated from the previous full adder.The gate delay can easily be calculated by inspection ofthe full adder circuit. Each full adder requires three levelsof logic. In a 32-bit ripple-carry adder, there are 32 fulladders, so the critical path (worst case) delay is 2 (frominput to carry in rst adder) + 31 * 3 (for carry propaga-tion in later adders) = 95 gate delays. The general equa-tion for the worst-case delay for a n-bit carry-ripple adderis

TCRA(n) = THA+(n1)Tc+Ts = TFA+(n1)Tc = 6D+(n1)2D = (n+2)2DThe delay from bit position 0 to the carry-out is a littledierent:

TCRA[0:cout] = THA + n Tc = 3D + n 2DThe carry-in must travel through n carry-generator blocksto have an eect on the carry-out

TCRA[c0:cn](n) = n Tc = n 2DA design with alternating carry polarities and optimizedAND-OR-Invert gates can be about twice as fast.[3]

1-bitFull

Adder

1-bitFull

Adder

1-bitFull

Adder

1-bitFull

AdderC0

C4

A3 B3 A2 B2 A1 B1 A0 B0

S3 S2 S1 S0

4-bit Carry Look AheadC3 C2 C1 p0 g0

PG GGp1 g1p2 g2p3 g3

4-bit adder with carry lookahead

To reduce the computation time, engineers devised fasterways to add two binary numbers by using carry-lookaheadadders. They work by creating two signals (P and G) foreach bit position, based on whether a carry is propagatedthrough from a less signicant bit position (at least oneinput is a '1'), generated in that bit position (both inputsare '1'), or killed in that bit position (both inputs are '0').In most cases, P is simply the sum output of a half adderand G is the carry output of the same adder. After Pand G are generated the carries for every bit position arecreated. Some advanced carry-lookahead architecturesare the Manchester carry chain, BrentKung adder, andthe KoggeStone adder.Some other multi-bit adder architectures break the adderinto blocks. It is possible to vary the length of theseblocks based on the propagation delay of the circuits tooptimize computation time. These block based addersinclude the carry-skip (or carry-bypass) adder which willdetermine P and G values for each block rather than eachbit, and the carry select adder which pre-generates thesum and carry values for either possible carry input (0 or1) to the block, using multiplexers to select the appropri-ate result when the carry bit is known.Other adder designs include the carry-select adder,conditional sum adder, carry-skip adder, and carry-complete adder.

33.2 Lookahead carry unit

16-bitLCU

Adder

16-bitLCU

Adder

16-bitLCU

Adder

16-bitLCU

AdderC0

C64

A48..63 B48..63 A32..47 B32..47 A16.31 B16..31 A0..15 B0..15

S48..63 S32..47 S16..31 S0..15

64-bit Lookahead Carry UnitC48 C32 C16 p0 g0

PG GGp16 g16p32 g32p48 g48

A 64-bit adder

By combining multiple carry lookahead adders evenlarger adders can be created. This can be used at multiplelevels to make even larger adders. For example, the fol-lowing adder is a 64-bit adder that uses four 16-bit CLAswith two levels of LCUs.

3.3 Carry-save addersMain article: Carry-save adder

If an adding circuit is to compute the sum of three ormorenumbers it can be advantageous to not propagate the carryresult. Instead, three input adders are used, generatingtwo results: a sum and a carry. The sum and the carrymaybe fed into two inputs of the subsequent 3-number adderwithout having to wait for propagation of a carry signal.After all stages of addition, however, a conventional adder(such as the ripple carry or the lookahead) must be usedto combine the nal sum and carry results.

4 3:2 compressorsWe can view a full adder as a 3:2 lossy compressor: itsums three one-bit inputs, and returns the result as a singletwo-bit number; that is, it maps 8 input values to 4 outputvalues. Thus, for example, a binary input of 101 resultsin an output of 1+0+1=10 (decimal number '2'). Thecarry-out represents bit one of the result, while the sumrepresents bit zero. Likewise, a half adder can be used asa 2:2 lossy compressor, compressing four possible inputsinto three possible outputs.Such compressors can be used to speed up the summa-tion of three or more addends. If the addends are ex-actly three, the layout is known as the carry-save adder.If the addends are four or more, more than one layer ofcompressors is necessary and there are various possibledesign for the circuit: the most common are Dadda andWallace trees. This kind of circuit is most notably usedin multipliers, which is why these circuits are also knownas Dadda and Wallace multipliers.

5 References[1] Georey A. Lancaster (2004). Excel HSC Software De-

sign and Development. Pascal Press. p. 180. ISBN9781741251753.

[2] M. Morris Mano, Digital Logic and Computer Design,Prentice-Hall 1979, 0-13-214510-3 pp.119-123

[3] Burgess, N. (2011). Fast Ripple-Carry Adders inStandard-Cell CMOS VLSI (PDF). 20th IEEE Symposiumon Computer Arithmetic. pp. 103111.

6 External links Binary adder with visual results, A tool which visu-

ally explains how to add two binary numbers sub-mitted by user. Helpful for beginners.

Hardware algorithms for arithmetic modules, in-cludes description of several adder layouts with g-ures.

8-bit Full Adder and Subtractor, a demonstration ofan interactive Full Adder built in JavaScript solelyfor learning purposes.

Interactive Full Adder Simulation, Interactive FullAdder circuit constructed with Teahlabs online cir-cuit simulator.

Interactive Half Adder Simulation, Half Adder cir-cuit built with Teahlabs circuit simulator.

4-bit Full Adder Simulation built in Verilog, and theaccompanying Ripple Carry Full Adder Video Tu-torial

4 7 TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES

7 Text and image sources, contributors, and licenses7.1 Text

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Half adderFull adderMore complex addersRipple-carry adderLookahead carry unitCarry-save adders

3:2 compressorsReferencesExternal linksText and image sources, contributors, and licensesTextImagesContent license