adc front-end design considerations for telecommunication satellite applications presented by dr....
TRANSCRIPT
ADC Front-End Design Considerations for Telecommunication Satellite Applications
presented by
Dr. Rajan Bedi
UK EXPORT CONTROL TECHNOLOGY RATING:3A001.a.1.a, 3A001.a.2.a, 3C001.a, 3C001.b, 3E001, 4E001.a, 4A003.a, 5E001.b.1Rated By: P. Cornfield with reference to UK Export Control Lists (version INTR_B05.doc 30 July2006) which contains the following caveat: “The control texts reproduced in this guide are forinformation purposes only and have no force in law. Please note that where legal advice isrequired, exporters should make their own arrangements”.Export licence : Not required for EU countries. Community General Export authorisation EU001is valid for export to : Australia, Canada, Japan, New Zealand, Norway, Switzerland & USA.
AMICSA 08: Slide 2 of 28
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Agenda
Introduction
Balun and ADC Modelling
Simulation Results
Conclusion & Future Work
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. Differential ADCs
Digital wideband telecommunication payloads use high-frequency differential ADCs.
System noise accumulates in signals as they travel across a PCB or through long cables.
Differential signals are highly immune to system noise due to the common-mode rejection of a differential ADC.
System noise such as that induced from switching supplies, ground currents and EMI are reduced due to the common-mode rejection of a differential ADC.
Differential signals cancel even-order harmonics providing better distortion performance than single-ended signals.
A differential input doubles the ADC’s useful dynamic range.
AMICSA 08: Slide 4 of 28
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. Single-Ended to Differential Conversion
Prior to digitization, we need to convert the single-ended, down-converted baseband output to a differential signal.
The conversion from single-ended to differential, transmission line effects and package parasitics, adversely affect the integrity of the analogue input to the ADC.
These combined effects impact the maximum dynamic performance that can be achieved from the ADC.
AMICSA 08: Slide 5 of 28
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. Single-Ended to Differential Conversion
There are a number of conversion options: Single-ended to differential amplifier RF Transformer
There were no wideband space-grade differential amplifiers that had the required bandwidth and dynamic range.
AMICSA 08: Slide 6 of 28
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Balun Transformer
A balun transformer is to be used to convert the single-ended, down-converted baseband output to a differential signal.
The balun also provides the necessary impedance matching between the single-ended input and the differential input resistance of the ADC.
A centre-tapped secondary winding provides the freedom to set the common-mode level arbitrarily.
The voltage gain provided by a step-up balun transformer introduces no non-linear, amplification noise.
AMICSA 08: Slide 7 of 28
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. Simplified Ideal Balun Specification
The balun converts the 50 ohm single-ended baseband input into a differential signal driving the100 ohm differential ADC input resistance.
Impedance Ratio Z = Secondary Impedance / Primary Impedance = 2
Turns Ratio N = Secondary Turns / Primary Turns = √Z = √2 = 1.414
L1 = 3.5 uH
L2 = 3.5 uH
L1 = 6.86 uH
R=100 OhmZ=50 Ohm
AMICSA 08: Slide 8 of 28
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. Balun Imperfections
Balun transformers are not perfect.
Intrinsic parasitics affect the amplitude and phase balance of the differential output which could potentially result in increased even-order distortion in the ADC output spectrum.
Baluns have a finite bandwidth and not always a flat amplitude response over the frequency range of interest.
Baluns introduce an in-circuit insertion loss as well as a return loss.
AMICSA 08: Slide 9 of 28
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. Balun Imperfections
Winding Resistance – both the primary and secondary windings have resistance (copper loss) which reduces the expected load voltage.
Magnetic Flux Leakage – both the primary and secondary windings have leakage inductance caused by incomplete mutual coupling between the windings.
Intra-Winding Capacitance – there is always some stray capacitance between adjacent turns of each winding – effective capacitance in parallel with each winding of the balun.
AMICSA 08: Slide 10 of 28
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. Balun Imperfections
Inter-Winding Capacitance - there is stray capacitance between windings.
Core Losses: Eddy current loss which increases with frequency Hystersis loss which increases with flux density Magnetising inductance core loss
Low-frequency behaviour of a balun transformer is influenced by the inductance of the primary winding.
High-frequency behaviour of a balun transformer is influenced by the windings capacitances and series inductances.
AMICSA 08: Slide 11 of 28
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Model of a Lossy Non-Ideal Balun
L=6
.86
uH
LSEC2L=3.5 uH
LSEC1L=3.5 uH
LPRI
C5
R3 L4
L3 R2
C4
C1
C2
C3
R4
R1
L2
L1
Primary and secondary leakage inductance: +IL and -RL at high freqs. Primary and secondary resistive winding loss: +IL at high freqs. Interwinding and Intrawinding capacitances: +IL at high freqs. Core losses: +IL and -RL at low freqs.
AMICSA 08: Slide 12 of 28
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. Simulation Environment
A simulation environment has been developed to model the analogue front end which includes:
A VHDL-AMS behavioural model of a differential ADC which accounts for offset and gain error, DNL and INL.
A SPICE model of a lossy balun transformer model which includes real balun parasitics.
Transmission line interconnect effects between these components.
AMICSA 08: Slide 13 of 28
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. Simulation Environment
The simulation environment is allowing us to investigate how the balun parasitics affect the output from the ADC.
Sinusoidal and NPR analysis within this simulation environment.
AMICSA 08: Slide 14 of 28
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. ADC Simulation Results8-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
• Single tone testing, Fin = 47.5 MHz at – 1 dBFS
• SFDR = 52.5 dBc, SINAD = 43.2 dB, SNR = 43.9 dB & ENOB = 7 bits
-80
-60
-40
-20
0
0 50 100 150 200 250 300 350
Frequency (MHz)
Am
pli
tud
e (d
B)
AMICSA 08: Slide 15 of 28
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. ADC Simulation Results8-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
49.5
50
50.5
51
51.5
52
52.5
53
0 10 20 30 40 50
Phase Imbalance (degrees)
SF
DR
(d
Bc)
There is only 2.5 dB variation in SFDR as a function of phase imbalance due to a slight increase in H2.
AMICSA 08: Slide 16 of 28
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ADC Simulation Results8-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
41.5
42
42.5
43
43.5
44
44.5
0 10 20 30 40 50
Phase Imbalance (degrees)
SIN
AD
(d
B)
• SINAD decreases by 2.5 dB as a function of phase imbalance
AMICSA 08: Slide 17 of 28
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ADC Simulation Results8-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
42.5
43
43.5
44
44.5
45
45.5
46
0 10 20 30 40 50
Phase Imbalance (degrees)
SN
R (
dB
)
• SNR decreases by 2.5 dB as a function of phase imbalance
AMICSA 08: Slide 18 of 28
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. ADC Simulation Results8-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
6.8
6.85
6.9
6.95
7
7.05
7.1
7.15
7.2
7.25
7.3
0 10 20 30 40 50
Phase Imbalance (degrees)
EN
OB
(b
its)
• ENOB decreases by 0.41 bits as a function of phase imbalance
AMICSA 08: Slide 19 of 28
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ADC Simulation Results8-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
There is 3.7 dB variation in SFDR as a function of amplitude imbalance.
0
10
20
30
40
50
60
-3 -2 -1 0 1 2 3
Amplitude Imbalance (dB)
SF
DR
(d
Bc
)
AMICSA 08: Slide 20 of 28
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ADC Simulation Results8-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
0
5
10
15
20
25
30
35
40
45
50
-3 -2 -1 0 1 2 3
Amplitude Imbalance (dB)
SIN
AD
(d
B)
Negligible variation in SINAD as a function of amplitude imbalance.
AMICSA 08: Slide 21 of 28
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ADC Simulation Results8-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
37
38
39
40
41
42
43
44
45
-3 -2 -1 0 1 2 3
Amplitude Imbalance (dB)
SN
R (
dB
)
Minor variation in SNR as a function of amplitude imbalance.
AMICSA 08: Slide 22 of 28
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ADC Simulation Results10-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 50 100 150 200 250 300 350
Frequency (MHz)
Am
pli
tud
e (d
B)
• Single tone testing, Fin = 45.625 MHz at – 1 dBFS
• SFDR = 67.3 dBc, SINAD = 54.9 dB, SNR = 55.5 dB & ENOB = 8.92 bits
AMICSA 08: Slide 23 of 28
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ADC Simulation Results10-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
65
65.5
66
66.5
67
67.5
68
68.5
69
0 10 20 30 40 50
Phase Imbalance (degrees)
SF
DR
(d
Bc)
There is only 1.7 dB variation in SFDR as a function of phase imbalance, not due to H2.
AMICSA 08: Slide 24 of 28
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ADC Simulation Results10-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
53
53.5
54
54.5
55
55.5
56
0 10 20 30 40 50
Phase Imbalance (degrees)
SIN
AD
(d
B)
• SINAD decreases by only 0.8 dB as a function of phase imbalance
AMICSA 08: Slide 25 of 28
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ADC Simulation Results10-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
54
54.5
55
55.5
56
56.5
57
0 10 20 30 40 50
Phase Imbalance (degrees)
SN
R (
dB
)
• SNR decreases by only 1.2 dB as a function of phase imbalance
AMICSA 08: Slide 26 of 28
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ADC Simulation Results10-bit ADC model: DNL = ± 0.5 lsb, INL = ± 1 lsb
8.65
8.7
8.75
8.8
8.85
8.9
8.95
0 10 20 30 40 50
Phase Imbalance (degrees)
EN
OB
(b
its)
• ENOB decreases by only 0.19 bits as a function of phase imbalance
AMICSA 08: Slide 27 of 28
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. Conclusion
A simulation environment has been developed that allows the analogue front-end of a digital payload to be modelled.
Simulation results suggest that actual device amplitude and phase imbalances from standard product COTS baluns have limited impact on the dynamic performance of an ADC.
Parameters such as 3dB bandwidth and flatness over the frequency range of interest maybe more important from a Systems/Payload perspective.
AMICSA 08: Slide 28 of 28
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. Future Work
We are about to characterise a selection of COTS baluns using a VNA to measure the amplitude and phase imbalance …..
These will then be used to convert a single-ended signal to a differential ADC input to correlate the measured data from actual hardware with simulation results.