accelerate energy efficient soc designs - dolphin design - faster … · 2019. 9. 11. · dolphin...

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DOLPHIN INTEGRATION

CONFIDENTIAL

Equipe Harmonie / Emblem Dolphin Integration IP-SoC Grenoble 05 Dec 2012

Faster and safer design for integration of power-optimized SoCs

-Part 2-

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Construction of low-power SoC Abstract

The construction of low-power islets through:

!  The optimization of the power management network, early in the design flow (i.e. before RTL design), through simulation with behavioral models using rough power consumption estimations.

!  .. And all along the low-power design flow.

!  The implementation of power islets with specific innovative cell and automatic script to handle the additional tasks required in a traditional flow.

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Construction of low-power SoC Targeted SoCs

1.  Multi-voltage islets 2.  Multi-mode power islets

(retention/extinction) 3.  Pure logic 4.  Mixed signal SoCs with analog

islets sensitive to noise on power supply

5.  With PMNet (external or embedded)

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Construction of low-power SoC Low Power SoC construction issues solved!

1.  Ensure Power consumption saving ⇒  Sizing of the PMNet ⇒  Select the relevant power modes according the application ⇒  Assess the power saving along the design flow 2.  Fasten Time to GDSII ⇒  Mastery of the different steps of the design flow ⇒  Automatic construction of retention/extinction islet 3.  Secure Low-Power SoC functionality ⇒  Functionality check of the pair regulator/power islets ⇒  The overall SoC functionality check with different power islets ⇒  Mode Transition Checks

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Construction of low-power SoC Benchmark Description Hawaii Basic

ACU ISLET 1 1.2 V /off

75mA max

ISLET 2 1.2 V /off + ret

25mA max REGULATOR

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Construction of low-power SoC Hawaï – Power State Table

2 Islets with 2 states !  Islet 1 : Ret / On !  Islet 2 : Off / On

Modes M1 M2 M3 M4

Islet 1 Ret On Ret On

Islet 2 Off Off On On

Islets Functioning modes Voltages Complexity Consumption

Islet 1

ON (2 % of the lifetime) 1.2 V +/- 10 % 1 Mgates 30 mW

RET (98 %) 1.2 V +/- 10 % 30 reg of 32 bits 1 memory (4 kbits) 800 µW

Islet 2

ON (1 % of the lifetime) 1.2 V +/- 10 % 500 kgates

90 mW

OFF (99 %) 1.2 V +/- 10 % < 100 µW

ACU ON 1.2 V +/- 10 % 5 kgates 20 µW

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Construction of low-power SoC Haiwaï – Mode Change Description

Islet 1 ret

Islet 1 on

Islet 2 off

Islet 2 on

M1 M2

M3 M4

Mc-3

Mc-1

Mc-2 Mc-4

Mc-5

Mode change 1 : from 0 ms to 1 ms Mode change 2 : from 1 ms to 2 ms Mode change 3 : from 2 ms to 3 ms Mode change 4 : from 3 ms to 4 ms Mode change 5 : from 4 ms to 5 ms

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Construction of low-power SoC Hawaï – Power Synoptics

PMIC

SoC

Source 1.62 – 3.63 V

ACU

I/Os

20 µW

C

PMIC

20 mW (ON)

7.3 mW (CK off) Block 1

Block 2 90 mW (ON)

C

L NV

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Construction of low-power SoC Hawaii – Power Synoptics

Basic-Ret

ePMNET

SoC

Source 1.62 – 3.63 V

ACU

NV

I/Os

eSR-‐Bu

20 µW

PS-TRC Islet 1 RET

C

L

90 mW (ON)

< 100 µW (OFF)

30 mW (ON)

800 µW (Ret.)

PS-TRC Islet 2 EXT

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Construction of low-power SoC Hawaii – Expected Gains @ SoC Architecture Step

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Construction of low-power SoC

Relevant concepts Relevant concepts

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Construction of low-power SoC IR Drop Basics

!  IR drop is a basic application of Ohm's law (that's why it is called I*R drop !) : U = I * R

!  IR drop normally refers to drop of the power supply. By extension, in this presentation, it also includes voltage bounces above the nominal power supply value.

!  It is a normal phenomenon that only becomes a problem if the voltage drop falls below/above a critical threshold fixed by the std cells or memory characterization.

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Construction of low-power SoC IR Drop Basics

?

time

time

I

V

!  The behavior of the PMnet at lower frequencies, taking into account the external component such as the regulator, the bonding or the tank capacitor, must be analyzed too...

!  Classic IR-drop analysis tools allow verifying IR-drop inside each islet using accurate power analysis results at clock frequency.

!  Internal capacitors of the islet help in limiting this IR-drop, but they are too small to manage big transitions in average power consumption

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Construction of low-power SoC LF and HF IR Drop

2 distinct IR drop analysis have to be performed:

1. Low-Frequency IR-drop analysis deals with power mode changes 2. High-Frequency IR-drop analysis deals with clock-edge changes

⇒ At architecture step, simulation with behavioral power models for regulator, power grid network, and islets, enables to early define the IR drop budgets and to size the PMNet.

⇒ At layout level, using IR-drop analysis tool, the HF IR-Drop is evaluated without taking into account regulator, package and bonding models to simplify the analysis

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Construction of low-power SoC Mode Transition Check (MTC)

What is Mode Transition Check?

1. An analysis to assess the Low-Frequency IR-drop. 2. A check to verify that all changes in SoC power modes required by the

application are correctly handled by the PMNet ⇒ It well complements the traditional IR Drop analysis performed at layout level

which only deals with high-frequency IR-drop

Examples of power mode transition : -  Power-up/power-down of a power islet -  Retention/On of a power islet -  Change of frequency inside one islet

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Construction of low-power SoC Mode Transition Check (MTC)

The Dolphin MTC verification: !  is an electrical simulation (transient simulation) that can be

performed by logic designers! !  uses power models for the different elements (regulator, bonding,

BoM, islet, power grid…) provided by the ViC/Library designers !  Electrical behavioral models in spice, verilog-A

!  Performed at relevant steps in the integration flow !  Starting with basic consumption metrics (power consumption as a

function of an islet of a given size) at architectural level !  Using extractions with accuracy relative to the project progress (after

synthesis, after floorplan, after place and route)

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Construction of low-power SoC Low-Power SoC Construction Design Flow

SoC Architecture

Islet Partitioning

PMNet synoptics

& architecture

Step1 PMNet Sizing

Step2: SoC

RTL Design

Step3: SoC

Synthesis

Step5: SoC

Place and Route

Step7 SoC

Sign-Off (DRC,LVS,STA)

Step6: SoC

Sign-Off (MTC)

Step3-bis PMNet Sizing


Low-Power SoC

Right on first Pass!

Step4: SoC

Floorplan

Step4-bis: PMNet Sizing

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Step1- SoC/PMNet Setting Step1 & co - PMNet Sizing

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Construction of low-power SoC Step1- Objectives

Context: The SoC Integrator has a first version of the Power Management Network (PMNet) and a rough idea of the complexity of the different islets

1.  Perform simulation to size the regulator to the predefined islet(s) 2.  Perform simulation to size the islet /define the possible islets

modes according to the selected regulator (the reverse) 3.  Perform simulation to assess the LF & HF IR-Drop budgets at

circuit level ⇒  With High Level Behavioral Models called EPLAM Model

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Construction of low-power SoC Step1- EPLAM Definition and Parameters

!  EPLAM = Electrical Performance Logic and Analog Model => Remember: this is an Electrical Behavioral Power Model! !  EPLAM for Regulator includes

–  Transfer functions –  VINSD, PSRR, Zout, CBTF

!  EPLAM for composite logic islets includes: –  Such Parameters as:

–  power switch resistance when the islet is active –  Power grid resistance –  Internal Capacitance –  Thresholds for characterization range –  Nominal/retention (if different) voltage values –  Ratio between nominal voltage and IR Drop HF inside the islet (%)

Rsw Rgrid/2

Cint

Rgrid/2

Imode

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Construction of low-power SoC Step1- Inputs/Outputs

!  Inputs: –  EPLAM model for regulator –  EPLAM model for islets –  EPLAM model for bonding+external components

!  Outputs: –  IR Drop Budget (LF and HF) –  Validation of the regulator choice –  Sizing of the required external components (BoM) –  Assessment of the Power Distribution Network

–  decoupling external capacitance requirements, –  bonding, –  intrinsic capacitance of the power islet, –  load transient at the output of the regulator

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Construction of low-power SoC Step1- Description

!  Create the schematics top !  Perform the acceptance of the EPLAM models !  Launch simulation by PMNet branch !  Adapt the parameters inside the PMNet until the input of the different islets !  Define the best set of parameters per branch !  Deduce the IR Drop budgets

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Construction of low-power SoC Step1- Top Schematics with EPLAM Models

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Construction of low-power SoC Step1- Benefits

!  Get rough of magnitude for the rest of the implementation !  Simulation environment ready for the IR Drop Low Frequency check for any

possible and defined combination of the transition modes.

Mc-1 Mc-2 Mc-3 Mc-4 Mc-5

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Construction of low-power SoC Step1- Play with PMNet Parameters

With C on-chip = 100 pF Retention Errors on Islet 1

Logic supply Errors on Islet 1

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Construction of low-power SoC Step1- Play with PMNet Parameters

With C on-chip = 1 nF

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!  Islet sizes for a given regulator with output current of 100mA: •  VDDAO when Islet-1 need 75 mA and Islet-2 115 mA

Step1- Play with PMNet Parameters

Retention Errors on Islet 1

Logic supply Errors

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!  Islet sizes for a given regulator with output current of 100mA: •  VDDAO when Islet-1 need 25 mA and Islet-2 75 mA

Step1- Play with PMNet Parameters

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Construction of low-power SoC Haiwaï- Power Saving @ PMNet Sizing Step1

Normal mode: all islets in ON mode Retention mode: Islet1 " Retention; Islet2 " OFF

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Construction of low-power SoC Haiwaii – Step 1 Outputs

IR Drop Budgets : ⇒ Total budget : 10 % (value from Standard cell characterisation)

!  Regulator Precision : 3 % (IR-Drop BF) !  Mode changing : 3 % (IR-Drop BF) !  Clock edges inside power islet : 4 % (IR-Drop HF)

BoM : !  Output inductor : 47 µH !  Output capacitor : 4,7 µF !  Number of pads to supply islets : 6 (35 mA /pads) !  On chip capacitor : 1 nF

Power Islets: !  Islet consumption per mode (Computed values from power models) !  Islet capacitance and resistance (Estimated values)

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Construction of low-power SoC PMNet Sizing Step EPLAM Parameters Evolution

Regulator External Capacitor

Bonding On-Chip Capacitor

Islet Cap & Resistance

Islet power consumption / mode

Islet HF IR-Drop / mode

Step1 Selected in PMnet architecture

Default value Default model used

Default value Cap Computed from islet area Res. Estimated from typical power grid

Computed from technology and complexity informations

Estimated from previous experience

Step3-bis After Synthesis

- Can be tuned in range of 100nF

Can be tuned with package information

Can be tuned Cap from SC can be extracted Estimated Cap for routing

First power simulation results Accuracy 20-30%

Updated with power simulation results

Step4-bis After Floorplan


Pinout fixed Updated model

Compromise capacitor versus area To be assessed

Extracted Resistance for the power grid

- -

Step5-bis After P&R


- Extracted capacitance value

Extracted capacitance value

Power simulation performed Max Accuracy

Updated with Dynamic IR Drop analysis

Step6 - Fixed value with tolerance

Fixed parasitics with tolerance

Fixed value Extracted values

Simulation results

Dynam IR Drop results

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Construction of low-power SoC PMNet Sizing Step in the low-power SoC design flow

For the SoC Architecture assessment

Step1

After Synthesis

Step3-bis

After Floorplan

Step4-bis

After P&R (inc. Clock Tree)

Step5-bis

Set-up the simulation environment with coarse estimated models

Confirm the islet partitioning

Confirm the power pad placement

Confirm the PMNet parameters

Estimate the IR Drop budgets (HF and LF)

Estimate the decoupling Confirm the HF IR Drop Budget

Confirm the decoupling

Assess the performance of the PMNet

Confirm the performance of the PMNet

Assess the PMNet feasibility

Monitor the consistency among regulators and islets

Confirm the consistency among regulators and islets

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SoC Architecture

Islet Partitioning

PMNet synoptics

& architecture

Step1 PMNet Sizing

Step2: SoC

RTL Design

Step3: SoC

Synthesis

Step5: SoC

Place and Route

Step7 SoC


Step6: SoC

Sign-Off (MTC)



Low-Power SoC


Step4: SoC

Floorplan


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Step1- SoC/PMNet Setting Step2- SoC RTL Code

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!  Structure the RTL code to have one hierarchy per power domain !  Insert in the RTL the required functions for low-power !  Create the first power description file (UPF)

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Construction of low-power SoC Step2 – RTL hierarchy

TOP

IORING

CORE

ACU

ISLETS

VIDEO_LIKE

MP3_LIKE REGULATOR

!  Power scenarios must be defined: use-cases of the circuit and related power state for each functionalities.

!  Islet hierarchy: Functionalities having the same power states must be put in the same hierarchy (islet)

!  Different kinds of islet: •  Voltage islet •  Extinction islet •  Retention islet

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Construction of low-power SoC Step2 – Introduction to TRC Cell

TRC cell is a specific standard cell developed by Dolphin Integration to manage the power switch transition mode (on->off; off->on) for an islet:

!  Automatic limitation of the inrush current to have a smooth powering-up of the islet: !  Value of the maximum inrush current is specified thanks to configuration pin. !  Configuration can be dynamically changed to fit to the different chip power

states. !  Complex Inrush current analysis is not required anymore.

!  Management of the retention and isolation signals. !  Direct insertion in the ring of power switches to avoid extra area !  Automatic script provided for power switch insertion and default TRC

configuration (see Step4 SoC Floorplan)

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Construction of low-power SoC Step2 – TRC cells insertion

TOP

IORING

CORE

ACU

ISLETS

VIDEO_LIKE

MP3_LIKE REGULATOR

TRC TRC

!  TRC = Transition Ramp Cell

!  A TRC cell must be added for each extinction and retention islet (also called power islet)

!  These TRC cells manage the power-up and power-down of the islet. They are controlled by the ACU (Activity Control Unit)

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TOP

IORING

CORE

ACU

ISLETS

VIDEO_LIKE

MP3_LIKE REGULATOR

Step2 – UPF specification

PD_TOP PD_REG

PD_VIDEO

PD_MP3

TRC TRC

create_power_domain PD_TOP create_power_domain PD_REG

-elements {...} create_power_domain PD_MP3

-elements {...} create_power_domain PD_VIDEO

-elements {...}

Definition in the UPF of the different power domains according to the different islets specified.

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TOP

IORING

CORE

ACU

ISLETS

VIDEO_LIKE

MP3_LIKE REGULATOR

Step2 – UPF specification

PD_TOP PD_REG

PD_VIDEO

PD_MP3

TRC TRC

ISO

ISO

ISO

RET

create_supply_net … connect_supply_net … set_domain_supply_net … set_isolation ... set_isolation_control ... set_retention ... set_retention_control ... map_retention_cell … create_power_switch …

Definition in the UPF of all the power management cells and supply nets. Connection of the TRC cells.

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Construction of low-power SoC Step2 – UPF specification

VDD_TOP VDD_REG VDD_MP3 VDD_VIDEO VSS

OFF 1.2 off off off 0.0 IDLE 1.2 1.2 off off 0.0 MP3 1.2 1.2 1.2 off 0.0

VIDEO 1.2 1.2 off 1.2 0.0 FULL 1.2 1.2 1.2 1.2 0.0

add_port_state … create_pst ... add_pst_state ...

Power State Table (PST)

Definition in the UPF of the Power State Table.

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SoC Architecture

Islet Partitioning

PMNet synoptics

& architecture

Step1 PMNet Sizing

Step2: SoC

RTL Design

Step3: SoC

Synthesis

Step5: SoC

Place and Route

Step7 SoC


Step6: SoC

Sign-Off (MTC)



Low-Power SoC


Step4: SoC

Floorplan


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Step1- SoC/PMNet Setting Step3- SoC Synthesis

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!  Run synthesis with UPF file description => No additional task to the traditional ones !

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SoC Architecture

Islet Partitioning

PMNet synoptics

& architecture

Step1 PMNet Sizing

Step2: SoC

RTL Design

Step3: SoC

Synthesis

Step5: SoC

Place and Route

Step7 SoC


Step6: SoC

Sign-Off (MTC)



Low-Power SoC


Step4: SoC

Floorplan


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Step1- SoC/PMNet Setting Step4 - SoC Floorplan

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Construction of low-power SoC Step4 - Objectives

1.  Placement of Power Regulators, power pads 1.  Power Regulation Point

2.  Placement of power domains 1.  Creation of Power Switch Ring for power islets

3.  Placement of macro cells respecting the power domain hierarchisation

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Construction of low-power SoC Step4 – Power Switch Ring creation

- Inputs : •  The islet where to insert the power switches •  Current limit when powering-up the islet •  The targeted static IR-drop •  The average power consumption of the islet •  The estimated islet capacitance

- Outputs : •  Number of power switches inserted •  The default TRC configuration and it associated

current limit

•  A table giving the current limit depending on the TRC configuration

•  The computed wake-up time

A script has been built to create power switch ring automatically:

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Step1- SoC/PMNet Setting Step5 - SoC Place and Route

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Construction of low-power SoC Step5 – Power Switch ring optimization

It allows to refine the TRC configuration and the ring sizing late in the P&R flow:

–  Decrease the ring total resistance to lower the IR-drop

–  Increase the ring total resistance to lower the leakage current when off

The same script used for the power switch ring , is used for the optimization:

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SoC Architecture

Islet Partitioning

PMNet synoptics

& architecture

Step1 PMNet Sizing

Step2: SoC

RTL Design

Step3: SoC

Synthesis

Step5: SoC

Place and Route

Step7 SoC


Step6: SoC

Sign-Off (MTC)



Low-Power SoC


Step4: SoC

Floorplan


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Step1- SoC/PMNet Setting Step6 - SoC Sign-Off - MTC

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Construction of low-power SoC Step6 – MTC Sign-Off

DRC

ERC

LVS

STA

MTC

Mode Transition Checks

Equiv Check

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Step1- SoC/PMNet Setting To summarize …

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Construction of low-power SoC To be retained!

1.  Use of EPLAM to set-up a simulation environment focused on power consumption and IR-Drops

1.  to select best solution at the architecture level (islet partitioning and regulator selection) in order to guarantee the power saving of your SoC

2.  to measure the performance of the PMNet 3.  to assess the LF & HF IR Drop budget and monitor those budgets at

each step 4.  to optimize the BoM

2.  Concept of TRC cell to limit the in-rush current with the automatic script to perform the power switch insertion and optimization in ring

3.  MTC as a sign-off verification for the functionality safety of a low-power SoC 4.  Case Study Tutorial Product (CTP) delivered by Dolphin to help the customer ⇒  Next shuttle using this methodology for low-power SoC : March 2013

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THANK YOU !

accelerate energy efficient soc designs - dolphin design - faster … · 2019. 9. 11. · dolphin...

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