Code No. A0611 R

JAWAHARLAL NEHRU TECHNOLOGY UNIVERSITY, HYDM.Tech. I Semester Regular Examinations, March –

LOW POWER VLSI DESIGN (Common to Digital Systems & Computer Electronics and Wir

Communications) Time: 3 hours Max

Answer any Five questions All questions carry equal marks

--- 1.a) What are the implications of Device Technology on IC design?

b) Discuss about the various problems associated with low vdesign? Explain.

2.a) Draw the structure of optimized twin-well BiCMOS structur

buried layers and explain the same. b) How graded drain structure can be produced? What are the

same? 3.a) Draw the structure of Bipolar with double poly silicon emitt

significance of the same. b) Explain about LOCOS Isolation method bringing out its signif 4. Draw the structure of poly silicon Emitter high performance

and explain the same. Give the process flow for the same. 5.a) Explain about the features of high performance LVLP; CMOST b) Give the process sequence of SOI lateral BJT and give th

Device parameters. 6.a) Explain about SPICE level 3 model of MOSFET, with necessar b) Explain about EKV model and capacitance models of MOSFET 7.a) Derive the Rigorous expression for turn-off or Rise time; con

for a CMOS Inverter Logic Gate. b) Draw the circuits and explain about the Two-types of Feed

Digital circuits. 8. Write notes on any two: a) ESD free BICMOS circuit b) Low power Flip-Flops c) Negative edge Triggered C2 MOS FF.

*****

N

ERABAD

2009

eless and Mobile

. Marks.60

Explain. oltage VLSI circuit

e with self aligned

advantages of the

er and explain the

icance.

BICMOS structure

device. e typical values of

y equations. S.

sidering body effect

back type BICMOS