low power at different levels of vlsi design
TRANSCRIPT
LOW POWER AT DIFFERENT LEVELS OF VLSI DESIGN
AND CLOCK DISRIBUTION SCHEMES
Chetan Sharma
(M. Tech-VLSI Department, JSS Academy of Technical Education, Noida)
Abstract- Low power chip requirement
in the VLSI industry is main considerable
field due to the reduction of chip
dimension day by day and environmental
factors. In this paper various low power
techniques at Gate level, Architecture
level and different tradeoffs between
different clock distribution schemes like
as single driver clock scheme and
distributed buffers clock scheme are
reviewed. Here it is also tried to showing
various effects of particular clock
distribution scheme such as clock skew,
clock jitter etc.
Keywords: Algorithm level techniques,
Circuit Level Aspects, Local restructing,
Clock jitter, Clock skew.
INTRODUCTION: Intel co-founder
Moore’s low describe the growth of VLSI
Industries that is double of number of
transistors in every eighteen
month.Althougy after few year VLSI
industry will reach to its saturation
condition i.e. growth rate of density of
component will not increase as recent
years but demands of portable, long
durable, lighter battery will never
decrease. Specific weight (stored energy
per unit weight) of batteries barely
double in several years.Besides
technological issues, further increase in
specific weight will soon draw safety
concern because the energy density is
approaching that of explosive chemicals.
So battery technology alone will not
solve the low power problem in near
future.
CMOS digital systems are approaching
to gigahertz frequency range. It is the
result of submicron technology. The
total power dissipation consists of two
components: (a)The static power
dissipation, which is due to a leakage
current of transistors during steady state.
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Fig (a)-Power dissipation in 80C51
(b)The dynamic power dissipation,
which has two components: short circuit
and charge/discharge of capacitance
power dissipation. The short circuit
power dissipation is a function of the
slew rate of the input voltage; the sharper
the clock edge, the lower the short circuit
power dissipation.
Short circuit power is result when both p-
transistor and n-transistor is on for short
duration of time. Mathematicall,
Vdd < |Vtp | + Vtn …………… (1)
Where: Vtp and Vtn are threshold
voltages for PMOS and NMOS
transistors, respectively. Threshold
voltage is a voltage at which channel
formation occurs in a metal–oxide–
semiconductor field- effect transistor
(MOSFET).
Power dissipation is given by
P=α.CV2f…………. (2)
Where: V yields to supply voltage and
Voltage swing. It is tried to reduce both
supply voltage and Voltage swing
because voltage have highest impact on
total power dissipation as show in
equation (2). α is switching activity, C is
capacitance and f is operating frequency.
Fig (b)-Switching energy
However, one major drawback
associated with clock networks is their
power dissipation. Studies have shown
that the clock network can dissipate 20-
50% of the total power on a chip. In the
context of the growing importance of
low power designs for portable
electronics, it is necessary to develop
strategies to significantly reduce the
Chetan Sharma, Int. J. Comp. Tech. Appl., Vol 2 (1), 88-93 ISSN : 2229-6093
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power dissipation of the clock network,
since this will lead to a major reduction in
the overall power dissipation of the chip.
The power is reduced at different levels
of VLSI design. Levels of optimization
are shown in fig(c).
Fig(c)-Power optimization at different
level of design.
Here we see that as the level of design
goes lower level to upper level as layout
level to system level number of counted
error increase means power saving
possibilities are more at higher levels.
1. Algorithm level reduction:
Power consumption at algorithm level
related to properties of that particular
algorithm techniques. So it should
carefully selected for lowering the power
consumption. For lowering the power,
algorithm should be such that it should
minimum number of switching
requirements. That algorithm is more
useful which have minimum number of
operation because it will require less
hardware. By increasing concurrency we
can increase efficiency of that device.
2. Architectural Level Techniques:
The basic building block at this level are
registers, busses multipliers, memories,
state machine etc.Each block perform
high level function. At architectural level
it is important to power analysis because
now a days chips become complex & it
is not easy to analyses each and every
gate. The architectural level is the design
entry point for the large majority of
digital designs and design decisions at
this level can have dramatic impact on
the power budget design.
Power is as the function of their
operating frequency and number of bits
of components. For example power in
the adder is given by
P= (n.k1+k2).f ……………. (4)
(a) Power and performance
management:
Firstly power management is done by
different saving modes such as DOZE,
NAP and SLEEP modes by deactivating
different levels, function levels. At Doze
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mode cache memory is active except it all
are off. Thus coherency is made by cache
memory. In Nap mode processor walks
up after some interval of time or by
external interrupt. In sleep mode all thing
is done by reset.
Secondly performance management is
done by adaptive technique by sensing
the load of input.
(c) Parallel and pipelined architecture is
another aspect which is also taken into
consideration. In parallel architecture
frequency is scaled down by factor n,
number of blocks. In parallel architecture
area required is more but operation is
become faster. In pipelining mode
frequency remain same but voltage is
scaled down.
Fig (d)-Comparison between parallel and
pipelined architectures
3.3. Gate level techniques:
(a) Local restructing: In this technique we
modified the group of gates based on
different operation such as Combine Gates,
Decomposition of gate, Delete wire, Add
wire, Duplicate a gate etc.
( (b) Signal gating: By using the controller we
can avoid extra switching activity which
directly impact on power dissipation.
(c)(c) Logic Encoding: In the place of binary
code if gray code is use then switching
activity is reduced by one on changing one
to another using the property of gray code
which changes only one bit transition on
changing in sequence.
(d) Bus Inverter Encoding: By comprising the
previous and present input it is decided to
minimum number of toggling in inverting
code and available code. If there is minimum
number bit toggling in without inverting then
it is directly uses otherwise inverting code is
used. The two inverting machine uses,one at
sending port and other one at receiving port.
According to output of parity, logic inverting
of code is done. At the sending side if
inverting of code is used then at the same way
inverting also will be use at receiving side for
converting code into its original form that’s
why same parity signal is gone to sending and
receiving side.
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Fig (e)-Bus Inverter Encoding
4. Clock schemes:
For providing synchronization of the
digital system one or more reference
clocks are used. Fully synchronization is
done by using common clock. By a single
clock all parts of digital system is clocked
for different operations. Clock tree used
for globally distribution the clock signal
to all modules. There are two types of
clock schemes: Single driver clock
scheme and Distributed buffers clock
scheme. Dynamic power dissipation by
switching of clock is given by:
Pclk = V2
dd.f.(CL +CD)……………(1)
Where CL is Total load capacitance on
clock.
There are two problems in clock generation
(a) clock skew: This is the variation in
delay from clock source to clock
destination in different clocks. (b)Clock
jitter: It is defined as temporal variation of
clock with respect to reference edge. It is
of two type long jitter and cycle to cycle
jitter.
Single buffer scheme: If the
interconnect resistance of the buffer at the
clock source is small as compared to the
buffer output resistance, it is called as
single driver clock scheme. The single
driver scheme has the advantage of
avoiding the adjustment of intermediate
buffer delay as in distributed buffer
schemes.
Distributed buffer scheme: This is the
most common and general approach to
equi-potential clock distribution scheme.
It leads to an asymmetric structure. In
single driver scheme, short circuit power
dissipation is more than distributed buffer
scheme due to the reason of small buffer
used in distributed buffer scheme.
Fig (f) - Distributed buffer scheme
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CONCLUSION:
Here we reviewed the different low power
techniques at each level of VLSI Design.
Different techniques have different
tradeoffs. We use particular techniques
according to specification. Here clock skew
and clock jitter problem are also reviewed
and these are eliminated by using
appropriate clock distribution schemes.
.
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Websitecurrently available online at
www.eas.asu.edu/~ptm.
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