1

A scalable control system for a superconductingadiabatic quantum optimization processor

M. W. Johnson†, P. Bunyk†, F. Maibaum‡, E. Tolkacheva†, A. J. Berkley†, E. M. Chapple†, R. Harris†,J. Johansson†, T. Lanting†, I. Perminov†, E. Ladizinsky†, T. Oh†, G. Rose†

Abstract— We have designed, fabricated and operated a scal-able system for applying independently programmable time-independent, and limited time-dependent flux biases to controlsuperconducting devices in an integrated circuit. Here we reporton the operation of a system designed to supply 64 flux biases todevices in a circuit designed to be a unit cell for a superconductingadiabatic quantum optimization system. The system requires sixdigital address lines, two power lines, and a handful of globalanalog lines.

I. INTRODUCTION

Several proposals for how one might implement a quantumcomputer now exist. One of these is based on enablingadiabatic quantum optimization algorithms in networks ofsuperconducting flux qubits connected via tunable couplingdevices [1]. Flux qubits can be manipulated by applyingmagnetic flux via currents along inductively coupled controllines. This can be accomplished with one analog control lineper device driven by room temperature current sources androuted, through appropriate filtering, down to the target deviceon chip.

Beyond the scale of a few dozens of such qubits theone analog line per device approach becomes impractical.Hundreds of qubits could require thousands of wires, eachsubject to filtering, cross-talk, and thermal requirements so asto minimize disturbance of the thermal and electromagneticenvironment of the targeted qubits, which are operated atmilliKelvin temperatures. We require an approach that doesnot use so many wires.

One advantage of using superconductor based qubits is theexistence of a compatible classical digital and mixed signalelectronics technology based on the manipulation of single-flux-quanta (SFQ) [2]. The ability to manufacture classicalcontrol circuitry [3] on the same chip, with the same fab-rication technology as is used in construction of the qubits,addresses many of the thermal and electromagnetic compati-bility requirements faced in integrating control circuitry withsuch a processor.

We present here a description of a functioning system ofon-chip Programmable Control Circuitry (PCC) designed tomanipulate the parameters and state of superconducting fluxqubits and tunable couplers, in such a way as to overcomethe scalability limitations of the one analog line per deviceparadigm. This system comprises three key parts.

† D-Wave Systems Inc., 100-4401 Still Creek Dr., Burnaby, BC V5C 6G9Canada (mwjohnson@dwavesys.com).‡ Physikalisch Technische Bundesanstalt, Bundesallee 100, 38116 Braun-

schweig, Germany

FINE

CRSE

FINE

CRSE

FINE

CRSE

FINE

CRSE

FINE

CRSE

FINE

CRSE

addr 0

addr 1

addr 2

addr 3

addr 4

addr 5

FLUX DAC

1:2 DEMUX

SFQ-GEN

32 DACs

Fig. 1. A 1:32 demultiplexer tree terminating in two-stage multiple fluxquantum DACs. The last address selects between the COARSE and FINEstages within a DAC. Two such trees were implemented for the 64 DACcircuit reported here.

The first of these is a single flux quantum (SFQ) demul-tiplexer used as an addressing system. It is constructed as abinary tree of 2N−1 1:2 SFQ demultiplexer gates as shown inFig. 1. For the specific design discussed here, the number ofaddress lines N is 6. As discussed below, this demultiplexerallows many devices to be addressed using only a few addresslines.

The second part is a set of digital to analog converters(DACs), located at the leaves of the address tree. These DACscomprise storage inductors that can hold an integer number ofsingle magnetic flux quanta (Φ0 = h/2e). Their digital inputare single flux quanta, and their analog output are the storedflux which can be coupled into a target device. The magnitudeof this output flux is proportional to the number of stored fluxquanta. Each DAC has two such storage inductors, a COARSEstage, and a FINE stage, named for the relative strength withwhich their output flux is coupled to the target device. In ourarchitecture, the output of these DACs is static.

The third part is a method for converting the static outputof a DAC to a time-dependent signal. This is achieved bycoupling the output of the DAC into a variable gain element,equivalent to the tunable coupler described elsewhere [4]. Ananalog line carrying a time-dependent current is coupled tothe target device via the variable gain element. This approachis useful in the types of circuits of interest here because single

arX

iv:0

907.

3757

v1 [

quan

t-ph

] 2

2 Ju

l 200

9

2

Fig. 2. FIB cut SEM cross-section for the process used to fabricate thecircuits described here. The top layer dielectric of this particular sample wasnot planarized, whereas in the process used to produce the circuits reportedupon, all dielectric layers were planarized.

analog lines can be shared among large numbers of devicesthat need the same functional dependence on time, but mayrequire individual tunability of the gain and offset.

We designed, fabricated and operated an integrated circuitcomprising this type of control system architecture. The cir-cuit includes eight superconducting rf-SQUID flux qubits asdescribed by Reference [5], each of which has inductive portscoupled to five different DACs, and 24 compound Josephsonjunction (CJJ) rf-SQUID couplers [4], each of which is cou-pled to a single DAC. Thus, this circuit required 8×5+24 = 64DACs. The particular control circuit described here comprisestwo 1:32 demultiplexers with six shared address lines and twoseparate power lines. This circuit included 1,538 junctionsranging in size from a minimum of 0.6 µm diameter (32 ofthem) to a maximum of 4 µm in diameter.

The paper is organized as follows: Requirements on controlcircuitry derived from the devices, architecture and operatingprocedures in superconducting adiabatic quantum optimizationsystems are discussed in section II. The specific controlcircuitry architecture is discussed in section III. Data demon-strating the performance relative to requirements is presentedin section IV. Conclusions are presented in section V.

The measurements reported in section IV were performedon two different chips fabricated in a four Nb layer supercon-ducting process employing a standard Nb/AlOx/Nb trilayer,a TiPt resistor layer, and planarized PECVD SiO2 dielectriclayers. Design rules included 0.25 µm lines and spaces forwiring layers and a minimum junction diameter of 0.6 µm.A sample process cross section, with all but the top dielectricplanarized, is shown in Fig. 2.

II. CONTROL CIRCUITRY REQUIREMENTS

Our intent is to embody a specific quantum algorithmin hardware. This algorithm, known as adiabatic quantumoptimization (AQO), is a novel approach for solving combi-natorial optimization problems. Unlike the incumbent tech-niques for such problems, such as simulated annealing orgenetic algorithms, AQO algorithms include procedures thatare explicitly quantum mechanical. The requirement to providethe quantum mechanical resources necessary for running thisalgorithm places unusual constraints on processor systems andcomponents.

Algorithm 1: The AQO algorithm.Data: A run-time tf ; an allowed edge set E; an N

dimensional vector ~h and an upper diagonalN ×N matrix K̂ with hj ,Kij ∈ R and Kij ∈ E.

Result: A set {s∗j}, sj ∈ {−1,+1}, that minimizesE(s1, ..., sN ) =

∑Nj=1 hjsj +

∑i,j∈E Kijsisj .

Set tf = 1 µs;1

Load ~h and K̂ values into hardware;2

Wait 1 ms for hardware to cool down;3

while solution not satisfactory do4

Run annealing algorithm;5

Read out qubits to generate trial solution {s∗j};6

if {s∗j} satisfactory then7

exit;8

else9

tf → 2tf ;10

end11

end12

Algorithm 2: The annealing algorithm.Data: A run-time tf ; a set of qubits with Hamiltonian

H(s) = A(s)HI +B(s)HF , where s = t/tf ,0 ≤ s ≤ 1, HI =

∑Nj=1 σx,j ,

HF =∑N

j=1 hjσz,j +∑

i,j∈E Kijσz,iσz,j ,where σx,j and σz,j are the Pauli σx and σz matrices forqubit j respectively, and A(s) and B(s) are envelopefunctions with units of energy such that A(0)/B(0)� 1and A(1)/B(1)� 1.Result: Evolution of H(s) from H(0) to H(1).Set s = 0;1

Wait 1 ms for hardware to reach ground state of H(0);2

Ramp currents on global analog lines to drive evolution3

s→ 1

Quantum computation intimately ties the physics of theunderlying hardware to its intended algorithmic use. Primarilymotivated by this observation, the approach we have taken todesign hardware is a top-down one. For the circuits consideredhere, the requirements are driven by what is required to runthe AQO algorithm. To provide context for the material in thissection we first provide an overview of the algorithm itself.

Consider the following discrete optimization problem:Given a vector ~h and upper diagonal matrix K̂, where theelements of both are real numbers, find the set {s∗i } thatminimizes the objective function

E(s1, ..., sN ) =N∑

j=1

hjsj +∑

i,j∈E

Kijsisj (1)

where si = {−1,+1}, and E is an set of (i, j) pairs whereKij is allowed to be non-zero. We call E the allowed edge set.The necessity for explicitly defining the set E arises becauseultimately we will connect this term in the objective functionto physical couplings between pairs of qubits, and for a varietyof reasons the number of elements in E will generally be much

3

Fig. 3. Top: Schematic showing two eight-qubit unit cells tiled together. Thequbits are schematically shown as the extended black loops, similar to the waythese devices are physically implemented. The couplers (shown as blue andred squares) are local to the intersections of qubits. Bottom: Photograph ofa standalone eight qubit unit cell occupying a 700µm× 700µm square on a3 mm × 7 mm chip.

less than the total number of possible pairs N(N − 1)/2. Adesign constraint on processor architecture is that qubits mustbe connected in such a way so that finding the minimum of Eq.(1) is NP-hard. Even with this constraint, it is straightforwardto find realizable sets E for which this holds, and we willfocus exclusively on these cases.

An AQO algorithm exists for solving this problem. Theapproach is outlined in Algs. 1 and 2. The control systemreported on here enters into these in step 2 of Alg. 1. Step6 of Alg. 1 is performed by a readout system reported on byBerkley et al. [6].

A. Processor Interconnect Architecture

There are many possibilities for how one might try to builda hardware system capable of running Algs. 1 and 2. Here wefocus on a unit cell consisting of eight qubits and 24 couplers.See Fig. 3 for a schematic and optical photograph showing theinterconnect pattern. Larger systems are designed by tiling theplane with increasing numbers of unit cells, as indicated in thetop of Fig. 3. This choice of unit cell fixes the allowed edgeset E, and satisfies the constraint that minimizing Eq. 1 beNP-hard.

B. Number of DACs

The total number of DACs required for circuits of increasingcomplexity is shown in Table I. Here we provide a briefoverview of how these numbers arise, and refer the readerto [4], [5] for further details.

1) One DAC per Coupler: A tunable compound Josephsonjunction rf-SQUID coupler inductively coupled to qubits i andj is used to set each desired value of Kij[4]. One such physical

TABLE IPARTS COUNT VS. NUMBER OF UNIT CELLS.

Unit Cells Qubits Couplers DACS JJs1 8 16 56 15004 32 72 232 6000

16 128 328 968 2400064 512 1416 3976 96000

256 2048 5896 16136 384000

device is required per element of the allowed edge set E.Couplers are controlled using a static dc flux bias applied totheir compound junction–no time dependence in this signal isrequired. For this design, the flux bias is provided by the DACshown in red in Fig. 4.

2) Five DACs per Qubit: The potential energy of an idealcompound Josephson junction rf-SQUID qubit is [7]

U = −ΦoIc

2πcos(

2πΦq

Φo

)cos(πΦCJJ

Φo

)+

(Φq − Φxq )2

2 Lq+

(ΦCJJ − ΦxCJJ)

2

2 Lcjj(2)

where Ic is the sum of Josephson critical currents in thecompound junction, Lq and Lcjj are the inductance in the qubitand compound junction loop, respectively. Likewise Φq, Φx

q ,and ΦCJJ, Φx

CJJ are the internal and applied flux for the qubitand CJJ loop respectively.

Eq. 2 is only applicable when the two junctions making upthe compound junction are identical. Junction critical currentIcs of identically drawn Josephson junctions in superconductorfabrication processes are reported to have a normal distributionwith a standard deviation of anywhere from 1% to 5% [8].Thus, we expect real compound junctions to be naturallyimbalanced. This causes difficulties in running the annealingalgorithm Alg. 2 [5]. To overcome this junction imbalanceproblem we use a more complex structure which we call acompound compound Josephson junction (CCJJ). This pro-vides two additional degrees of control freedom per qubit,which can be used to correct for reasonable junction imbalance(∼ 5% Ic difference). We access these structures via the blueCCJJ minor DACs in Fig. 4.

As inter-qubit coupling strength is adjusted, the susceptibil-ity of the coupler, and the extent to which it inductively loadsthe qubit, will change [4]. This causes the qubit inductanceLq in Eq. 2 to be dependent upon the choice of {Kij}. Toovercome the resulting problem-dependent inter-qubit imbal-ance, we add an additional compound junction, comprisingmuch larger junctions, in series with the qubit inductance. Wecall this structure an L-tuner [5]. The Josephson inductance ofthis compound junction is modified with application of a fluxbias applied through an on-chip flux DAC, shown in green inFig. 4.

As discussed in Reference [9], care must be taken duringannealing to ensure that the final Hamiltonian HF , the oneencoding the problem we wish to solve, is that which wasintended. Using a compound junction to modify the relativeweights of HI and HF causes ~h and K̂ to change during theannealing algorithm, both in an absolute sense, and relative toeach other. This arises because although energy scales ~h and K̂

4

Flux-biasDAC

   -comp.DAC

CCJJ minorDAC

CCJJ minorDAC

   -tunerDAC

CouplerDAC

Fig. 4. Single qubit schematic. The five main parts of this qubit design:the qubit main loop (black) with flux-bias DAC providing the flux-bias Φq ,the CCJJ (blue) with cjj-bias Φcjj in the major lobe and two DACs biasingthe minor lobes, the L-Tuner (green) with DAC, and Ip-compensator (pink)with DAC. Also shown is a coupler (red) with coupler DAC. The two globaltime dependent control lines (Icjj and IIp) used for running the annealingalgorithm are also shown.

are both functions of the persistent currents in the qubits (Ip),they have different functional dependencies. Qubit Ip changesduring annealing, distorting HF .

To keep the relative scale constant, the value of the appliedflux used to implement ~h must change during the annealing,but Φq(t) will be different for each qubit, depending on theintended value of ~h for that problem. This is accomplished bygiving each qubit another tunable coupler, coupled to both thequbit and a shared external analog flux bias line. We call thisan Ip-compensator. Each such coupler is used as a variablegain element, programmed with its own DAC (the pink DACin Fig. 4), and used to scale a global controlled signal to thelocally required hj .

Finally, each qubit has a DAC that can apply a small dcflux bias to its main loop (the black DAC in Fig. 4).

C. Precision and Range Requirements

Requirements on precision and range of flux from the DACsultimately depend on the precision to which the elements of~h and K̂ are to be specified. The system described here wasdesigned to be able to attain four effective bits of precisionon parameters hj and Kij ; in other words, the elements hj

and Kij can be selected from 16 different allowed values.This does not mean that the DACs need only four bits ofprecision. The DAC requirements are derived from those onHamiltonian parameters ~h and K̂, based on what aspect ofa qubit or coupler is being controlled. In our case, requiringfour bits of precision in ~h and K̂ typically translates into arequirement of about eight bits of precision in each of theDACs.

The primary design parameters for each DAC is its dynamicrange: how much flux is it necessary for the DAC to provide,and how fine a control of that flux is needed. All of the DACswere designed to cover their respective ranges in subdivisionsof either 300 or 400 steps. However, they differ in the total

amount of flux coupled at maximum range from around 25mΦ0 for the qubit flux bias DAC to as much as 0.9 Φ0 from thecoupler DAC. A summary of desired flux ranges and minimalflux steps is shown in Table II.

TABLE IIDESIGNED FLUX RANGES AND MINIMAL FLUX STEPS BY DAC TYPE

Max # Φo COARSE/FINE

DAC Type Span min ∆Φ COARSE FINE RatioQubit Flux 25.5 mΦ0 0.1 mΦ0 17 17 14.1

CJJ Balance 66.1 mΦ0 0.4 mΦ0 17 17 14.1L-Tuner 0.465 Φ0 1.1 mΦ0 40 10 10.7Coupler 0.968 Φ0 2.2 mΦ0 40 10 10.6

D. Programming Constraints

In the design discussed here, there are five DACs perqubit and one per coupler that need to be programmed toimplement a specific problem instance. While the DACs arebeing programmed, power is applied to the SFQ circuits in theaddress tree, and the chip will heat. The amount of time wemust wait for it to cool afterwards (step 3 in Alg. 1) dependson the peak temperatures reached by the various portionsof the circuitry, and the relaxation mechanisms mechanismsenabling their return to equilibrium [10]. Minimizing overallprogramming time, including that required to cool, is animportant design constraint, and must be considered whencomparing control circuitry architectures.

Given the block architecture described above, the numberof DACs we must program increases with processor sizeas shown in Table I. While not every DAC will need tobe programmed for each unique configuration of hj andKij in practice, in what follows the assumption will bethat all are. In our multiple flux quantum based encodingscheme, the programming time will depend on the valueprogrammed. To estimate the basic scaling with number ofdevices, it is probably reasonable to assume that each timethe processor is programmed for a new problem, each DACstage must receive on average half of its designed capacityin pulses. For example, the coupler DAC would receive about20(COARSE) + 5(FINE) = 25Φo, the qubit flux bias DACabout 9(COARSE)+9(FINE) = 18Φo, or roughly 20 Φo perDAC in either case.

Programming speed can then be bought at the expense ofadditional input lines and more parallelization - using more,shallower address trees each with its own separate input.

However, with or without parallelization, one must be ableto load all the pulses without errors. The more DACs beingprogrammed, the more pulses there are that must be routedthrough the address tree with fidelity, and the smaller theacceptable error probability per pulse. For example, per Ta-ble I, with 2048 qubits, we require 16,136 DACs. An averageproblem would require loading ∼ 3.2× 105 flux quanta ontothe chip. If we want 95% confidence that we can programproblems correctly 99 times out of 100, the probability thatany flux quanta makes an error should not be greater than10−9. With 128 qubits, 10−8 is sufficient.

Bit error probability in SFQ circuits has been extensivelystudied [11]. Satisfying these and even more demanding error

5

RESET

IN - FINE

IN - COARSE

FLUXTRANSFORMER

TARGETDEVICETARGETDEVICE

Fig. 5. A two stage DAC made of a pair of separately addressable storageinductors (distinguished by an extra line under the inductor schematic symbol).The flux from each inductor is scaled and summed in a flux transformer intothe target output.

rate requirements at sub-Kelvin temperatures is straightfor-ward, but needs to be confirmed for any particular implemen-tation.

III. CONTROL CIRCUITRY ARCHITECTURE

A. Two Stage Multiple Flux Quantum DAC with Reset

The design of the resettable DAC stage is discussed in moredetail in Reference [12]. The DACs were made of two stages.Each stage comprises a large storage inductor in series witha two-junction reset SQUID, and an input junction, as shownin Fig. 5. Each stage was designed with β ≡ 2πLIc/Φo in therange 75 to 300, depending on their function, and thus ableto hold in the range of 10 to 40 flux quanta of either polarity.Here L is the stage inductance, and Ic is the effective criticalcurrent of the two junction reset SQUID.

The two-junction reset SQUID is used to empty the DACstage of stored flux. This is accomplished by applying Φ0/2flux to the reset loop, so that its effective critical current2Ireset

c cos(πΦx/Φo), and thus DAC stage β, is diminished tobelow the level required to store flux. For this reset functionto be effective, it must be possible to suppress the effectivecritical current of the reset SQUID to less than that requiredto store one Φo in the storage inductor. This requirementplaces an upper bound on the DAC stage β. It also placesa requirement on how closely matched the Ics of the twojunctions in the reset SQUID must be to each other. This isbecause the minimum effective critical current will not be lessthan the difference in the Ics of the two reset junctions. Thusgiven a particular fabrication process, with its feature size,penetration depths, and characteristic junction Ic spread, therewill be some maximum number of Φo that can be stored in aDAC that can be reliably reset to an empty state. This limitsthe dynamic range of an individual DAC stage.

We can achieve a dynamic range greater than that of anindividual DAC stage, and shorten programming times, byconnecting two or more stages together, as indicated in Fig. 5.The intervening transformer couples the different stages intothe target circuit with different weights. The flux transformercan be thought of as playing the role of an R-2R ladder, suchas is frequently used in construction of semiconductor DACs.One important difference is that successive stages of this DAC

differ from each other not by factors of two, but more typicallyby a factor of ten, depending on the requirements set by thetarget device. The other difference is that we are transformingand dividing flux rather than voltage.

The flux coupled out of this DAC can be summarized bythe expression:

ΦOUT = k ·(

NCOARSEΦ0 +1γ·NFINEΦ0

)(3)

where NCOARSE,FINE represent the integer number of fluxquanta that are stored within the respective DAC stages, kthe coupling constant describing the amount of flux from theCOARSE stage into the output device, and γ, the divisionratio between COARSE and FINE, which is typically 10 forthe devices discussed here.

B. Programmable time-dependent signals

As discussed in section II-B.2, we require the ability to sup-ply time dependent signals to each of the qubits to compensatefor the fact that the qubit persistent current changes duringthe annealing process. These time dependent signals need tohave the same temporal shape but with different magnitudes.The DACs discussed above can hold static flux, and are notsuited to provide real-time signals. This is because they donot include a sample-and-hold stage to protect the output fromtransients during programming. Moreover, real-time updatingof the DACs would raise the temperature of the chip to anunacceptable level.

Rather, time dependent signals can be customized using thetunable coupler discussed in Reference [4] as a variable orprogrammable gain element. A global analog bias line holdinga master copy of the desired time dependent signal is coupledto each qubit on the chip through its own programmablegain element, as indicated in Fig. 6. Each programmable gainelement is controlled by its own DAC. In conjunction with anadditional DAC (not shown) to provide a flux offset to eachtarget device, the master copy of the signal can be uniquelytransformed for each target in the following manner:

Φi(t) = ai + giΦglobal(t) (4)

where ai and gi are programmable on a per device basis. Thisis not as flexible as having independent arbitrary waveformgenerators for each device, but it is flexible enough to satisfythe requirements of the IP compensator.

Fig. 6. A time dependent current on a global analog bias line can be uniquelyscaled into each of several target devices by using independent programmablegain elements (blue), each controlled with its own DAC (green).

6

J1

J3

J4 J5J6 J7

J2

in

out_l out_r

addr_in addr_out

L1

L2

L3 L4L5 L6

L7 L8

I1

I2 I3I4 I5

Fig. 7. 1:2 demultiplexer gate used to construct the address tree. All junctionsare explicitly shunted with TiPt resistors (not shown in schematic). Largearrows represent bias current that is supplied through bias resistors from acommon voltage rail.

C. Demultiplexer Tree

The DACs discussed above were loaded with SFQ pulsesrouted through a binary tree demultiplexer circuit shown inFig. 1. Each address tree is fed SFQ pulses originating inan SFQ generator circuit, namely a flux biased dc-SQUID.Each node of the tree is made of a 1:2 SFQ demultiplexercircuit, as shown in Fig. 7, and discussed in more detail inReference [12]. The 1:2 demultiplexer circuit is addressedwith a magnetically coupled flux bias line which steers anincoming SFQ pulse to one of its outputs based on the signand magnitude of current on that address line.

Reversing the polarity of the bias current allows flux quantaof opposite polarity to be routed, though the sign of theaddress current must also be reversed to get this negative fluxto the same output port. This makes use of a symmetry notcommonly exploited in SFQ circuits. Here it allows the DACstages to store flux of either sign, and allows the state of eachstage to be both incremented and decremented. This in turnallows DAC programming to be performed incrementally -starting from the previously programmed state without firstresetting to the empty (no stored flux) state.

Address lines are shared for all demultiplexer nodes at aparticular depth of the tree. The final address line in the treechooses between COARSE and FINE stages of each DAC. The64 DACs mentioned above are served by two separate trees,each addressing 32 DACs. These trees require five addresslines to address a particular DAC, plus a sixth line to choosebetween FINE and COARSE, giving a total of six addresslines to service the circuit block.

IV. DEMONSTRATION OF CONTROL CIRCUITFUNCTIONALITY

For the circuit block discussed in this paper, the controlcircuitry in its entirety represents moderate complexity -certainly not the most complex or heterogeneous SFQ circuitdemonstrated to date, nor the one with the most junctions.The eight qubit circuit block reported here, including theattached control circuitry, contains just over 1,500 Josephsonjunctions and 2,000 resistors. Nevertheless, implementation ofa new design in a new foundry requires careful performance

Fig. 8. SEM image of a portion of the DAC and demultiplexer circuitryafter deposition and patterning of the resistor layer and the trilayer steps, butprior to applying the upper three dielectric and metal layers.

evaluation. We must determine that the circuit yielded, oper-ated as designed, and whether variances are due to design orfabrication issues. We must determine if it meets its designrequirements.

A scanning electron microscope (SEM) image of a portionof one of the DACs and demultiplexer cells equivalent tothose reported here is shown in Fig. 8. The image wastaken after patterning of the trilayer and subsequent junctiondefinition. Uncontacted junctions appear as circles and are stillvisible in the demultiplexer circuitry toward the right of theimage. Subsequent fabrication involves the deposition of threeplanarized dielectric layers and three additional metal (Nb)layers. Junctions in this circuit have critical currents in therange 10 − 20µA. Resistors are also visible and appear asrectangles contacted at each end. Bias resistors are long andthin while shunt resistors for this portion of the circuitry arerelatively wide. The coils visible on the left are portions ofthe two storage inductors for one of the L-Tuner DACs. Thecoils are patterned with 0.25µm lines and spaces. The DAC’sreset junctions are visible in the upper center of the image.To the right is one of the demultiplexer cells. The entire fieldof view is approximately 40 µm in width and 50µm top tobottom.

In the architecture described above, many of the DACs areembedded deeply within the circuit, with no convenient ordirect method to determine how much flux they actually applyto the target per Φo in the FINE and COARSE stages. Thisinconvenience is addressed in two ways: Each variant of DACis implemented in a separate stand-alone or break-out circuitin which it applies a flux bias directly to a two-junction dc-SQUID. The dc-SQUID Ic vs Φ modulation curve is thenmeasured vs. DAC state, and a precise calibration of FINE

7

and COARSE weights (k and γ) can be extracted. Data fromparameters extracted in this way is presented in Table III.Second, within the body of the circuit block, wherever a DACis used to apply a flux bias, an analog line is also used toflux bias that target device in parallel with that DAC. Thiscombination is indicated in the inset of Fig. 9. This singleanalog line is shared amongst all like control nodes for allqubits, so that only a handful of such lines are required toservice the entire chip. Of course, the shared analog line cannotbe used for independent control of all devices simultaneously,but it is nevertheless useful for testing individual devices. Forexample, each qubit is flux biased by its own DAC and a singleshared externally accessible analog line. The qubit degeneracypoint is easily measured [6]. If the DAC is then programmedwith, for example, +5Φo in its COARSE stage, one candetermine the change in current on that analog qubit flux biasline required to compensate for the shift in degeneracy point.This allows us to find the ratio of mutual inductance betweenthe analog line and the qubit to that between each DAC stage(COARSE & FINE) and the qubit. We can independentlymeasure the mutual inductance of the analog line into thequbit by noting the Φo periodicity in its response. We can thendetermine k and γ for that DAC, which are the parameters weneed to determine how much flux the DAC applies to its target.

This feedback measurement is applicable to determining kand γ for DACs used for various types of control, not justqubit flux bias. The only thing that differs is the nature ofthe measured quantity. For the qubit flux bias DAC, the qubitdegeneracy point was mentioned. For the L-Tuner DAC, ameasure of the qubit’s inductance, ultimately a measure ofits circulating current, can be used. For the CCJJ DACs, ameasure that quantifies the imbalance in the qubit’s compoundjunction is used. In all cases we use the measured quantity todetermine what analog signal is necessary to compensate fora change in the programmed DAC state. In this way we candetermine how much flux each DAC on chip applies to itstarget.

A. DAC Biasing a DC SQUID

The couplers shown in red in Fig. 3 are designed to couplequbits between different unit cells. For the eight qubit unitcell under study here these were not connected to qubits onboth ends. Instead, the inter-unit cell couplers were wired upin such a way that their compound junction, still biased byits own DAC, could be operated as a hysteretic dc-SQUID.This coupler’s DAC could thus be used to apply flux to a dc-SQUID, and so we traced out the Ic vs Φ threshold character-istics for this dc-SQUID as discussed in Reference [6]. The Icvs Φ curve shown in Fig. 9 was taken both with an analog fluxbias controlled directly from room temperature electronics ((a),blue dots) or using the DAC ((a), black circles). To make sucha plot, we have to know the coupling constant k between theCOARSE DAC stage and the dc-SQUID it biases, as well asthe mutual inductance between the analog bias line and the dc-SQUID. As mentioned earlier, the mutual inductance betweenanalog line and dc-SQUID is easily determined by observingthe periodicity of the modulation curve. Also discussed earlier,

−1.5 −1 −0.5 0 0.5 1 1.50

1

2

3

4

Applied Flux (Φ0)

I C(�

A)

−0.5 0 0.50

1

2

3

4

Applied Flux (Φ0)

I C(�

A)

0.26 0.28 0.3 0.322.3

2.4

2.5

2.6

2.7

2.8

2.9

Applied Flux (Φ0)

I C(�

A)

(c) = 14

 = 15

 = 16

COARSECOARSECOARSE

AnalogIn

DAC

(a)

(b)

Fig. 9. (a) Ic vs. applied flux modulation curve of a small β two junctionhysteric SQUID where flux was applied with (blue dots) external analog biascurrent and (black circles) a two-stage superconducting DAC with greater thanΦ0 total span. The black circles are plotted for integer units of Φ0 sent to theCOARSE DAC stage. (b) SQUID modulation curve with integral COARSEvalues along with that taken exercising the FINE DAC stage around COARSE= 14 (red), 15 (green), and 16 (blue). (c) Expansion of boxed region in (b).Schematic shown in inset.

the coupling constant k and division ratio γ are measuredseparately with a feedback procedure.

The two threshold curves shown in Fig. 9a begin to deviatefrom each other past about ±0.65Φ0. This corresponds towhere the COARSE stage of this DAC has reached its capacity,and fails to store additional flux. To be clear, the black circlesare plotted vs. flux programmed into the DAC COARSE stage,not flux actually applied by that DAC stage to the dc-SQUID.A plot of the latter would fall on top of the blue dots.

Fig. 9b shows the same threshold curve vs. flux programmedinto the COARSE stage (black dots), but in addition, atCOARSE values of +14Φ0, +15Φ0, and +16Φ0, flux rangingfrom −6Φ0 to +6Φ0 is programmed into the FINE DAC stageas well. This is shown in the boxed region in Fig. 9b, which inturn is expanded in Fig. 9c. In Fig. 9c, it is clear that there issufficient range in the FINE DAC stage to bridge the COARSEDAC steps.

To use the DAC, it is necessary for the reset functionto operate. A reset pulse, made by first increasing the fluxbias on the reset dc-SQUID shown in Fig. 5 from zero tobeyond Φo/2, and then reducing it back to zero, was usuallyadequate to reset the DAC. There were cases when the Ics ofreset junctions for a particular DAC stage differed from eachother by more than about 5%, where a single pulse was notsufficient, and the DAC would occasionally retain one or twoΦo. In these cases, the reset pulse had to be repeated severaltimes to consistently empty the DAC. While the correlationbetween junction spread, DAC stage β, and reset function isnot quantitatively understood by us, we expect the problem toworsen with increased junction Ic spread, and with increasedDAC stage storage capacity (β). We found that for the chipsreported upon here, it was always possible to reset all of theDAC stages.

8

CRSCRS

(a) (b)

Fig. 10. (a) Flux response vs. flux programed into the COARSE (blackcircles) qubit flux DAC. (b) Expanded scale of the boxed region in (a) showsresponse of the FINE DAC stage to flux exercised around COARSE = 10Φo

(blue +) and 11Φo (red x). Measurement uncertainty in flux is smaller thanthe plot symbols.

B. DAC applying flux bias to a qubit

Each qubit has a DAC that can apply a flux bias to itsbody. Fig. 10 shows the flux response relative to the COARSEand FINE for one of these DACs. The limits of the COARSEstage capacity are just visible at the extrema of the plot. Toadequately cover the range, the maximum span achievablewith the FINE stage must be enough to cover one step of theCOARSE stage. This coverage is clearly attained in Fig. 10.

C. DAC control of inter-qubit coupling

One of the most challenging cases to treat in the designof these DACs was the situation in which a large flux spanwas to be applied to a low inductance SQUID. This situationis most extreme in the case of the coupler DAC and the L-tuner DAC. In fact, the dc-SQUID threshold curve presented inFig. 9 above is an example of such a case - these dc-SQUIDsare patterned identically to the compound junction used in thecoupler and Ip-compensator.

We can also observe a DAC controlling inter-qubit coupling.Fig. 11 shows a plot of the effective coupling between twoqubits, via a tunable coupler, as a function of flux applied tocontrol the coupler by an analog control line (red points). Inter-qubit coupling using the DAC to control the same coupler isshown as blue circles in the same plot. More details about thetype of measurement used to obtain this plot are discussed in[4].

While presented as an inter-qubit coupler, a similar deviceis employed in customizing shared time-dependent signals, asdiscussed in section III-B. The key difference is that in Fig. 6,one of the qubit ports on the coupler is connected to a globalanalog bias line. We found it straight forward employing thisprogrammable coupler in the fashion described in section III-B.

D. Summary of DAC performance

Table III(a) summarizes design targets vs. achievedCOARSE and FINE step sizes for the various types of DACimplemented on the eight-qubit block. Data from Table III(a)are extracted from separate break-out versions of the circuit.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35−6

−4

−2

0

2

4

6

Co

up

led

 flu

x (m

Φ0)

Analog lineDAC

Programmed Coupler Flux Bias (mA)

1.3

2.6

-1.3

-2.6 Inte

r-q

ub

it C

ou

plin

g (

pH

)

0

DAC

TARGETDEVICE

COUPLER

Fig. 11. Effective mutual inductance of an inter-qubit coupler as a functionof flux applied by an analog control line (red). The same vs. flux applied bythe coupler DAC are shown in blue. Error bars on the plot are smaller thanthe symbols.

Uncertainties reported derive from the measurement uncer-tainty of that parameter for that individual device. Measuringthese parameters in-situ using the feedback technique de-scribed above shows device-to-device variation with a standarddeviation of around 2%. For example, the distribution of kvalues measured for the 16 CCJJ DACs on one chip, shownin Fig. 12, exhibits a relative standard deviation of 1.4%. Thisis consistent with observed variation in mutual inductance ofsimple microstrip transformers used in this circuit, such asmight occur with variations in dielectric thickness of the samescale. Table III(b) summarizes the maximum number of SFQand maximum coupled flux by each DAC type.

It is worth observing that we were able to confirm that allof the two stage DACs on the chips discussed here yielded.By yielded we mean that they behaved as expected, perTables IIIa and IIIb, and that variations in coupling betweenidentically designed DACs were of the order of 2%. Moreover,there were no significant differences in maximum storagecapacity between identically designed copies. This stronglysuggests that the DAC storage coils yielded. An inter- or intra-layer short in one of the coils would have compromised theperformance of that copy.

Deviations between design targets and achieved parametersfor this chip are as large as 30% for some of the couplings.This is primarily due to the challenge of performing suffi-ciently accurate 3D electromagnetic modeling of the super-conducting inductors and transformers used in creating thetwo-stage DACs.

E. Demonstration of Demultiplexer Functionality

Delivering pulses to the DAC requires that power currentand address signals be applied to the demultiplexer tree. Poweris shared for all demultiplexer circuits in a particular tree,and address is common for all demultiplexers at a particularlevel in the tree. The design and fabrication of the chip mustbe sufficiently uniform such that all cells work with commonlevels. It is also necessary that the operating margins are wide

9

TABLE IIIDESIGNED VS. ACHIEVED DAC PARAMETERS

COARSE Step (mΦ0) FINE Step (mΦ0)DAC Type Design Achieved Design AchievedQubit Flux 3.0 3.506(3) 0.21 0.268(3)

CCJJ 5.6 3.899(2) 0.40 0.296(3)L-Tuner 11.3 8.481(1) 1.1 1.061(1)Coupler 23.6 19.0221(2) 2.2 1.788(1)

(a) COARSE and FINE DAC step weights

MAX COARSE Φ0 Max Coupled Flux (Φ0)DAC Type Designed Achieved Designed AchievedQubit Flux 17 22 0.050 0.077

CCJJ 17 22 0.093 0.086L-Tuner 41 40 0.460 0.339Coupler 41 35 0.960 0.665

(b) Maximum storage capacity, maximum applied flux

1.84 1.86 1.88 1.9 1.92 1.940

1

2

3

4

5

mean = 1.875 x 10−3

std. dev. = 2.6 x 10−5

k for CCJJ DAC (10−3)

Fre

quen

cy

CCJJ DAC k distribution

Fig. 12. Distribution of DAC k values for 16 identically designed CCJJDACs on one of the chips tested. The relative standard deviation is 1.4%.

enough that a robust, low error rate operating point can beobtained.

On this chip there were several DACs attached to unusedboundary couplers wired up as dc-SQUIDs. Operating marginsrequired to address the FINE and COARSE DAC stages ofeach of these were obtained with respect to global power andlevel of address signal. These operating regions are shown inFig. 13. Routing an SFQ pulse to a particular DAC requiresthe successful navigation of six demultiplexer gates, each withits own address current. While the signs of these variousaddress levels may differ, their magnitude in flux was heldto a common value, and this common magnitude of addressflux is the address axis in Fig. 13.

As far as addressing these six DACs, there is clearlyadequate uniformity in this demultiplexer tree that they can allbe operated at a common power and address level. We havedetermined that all 64 DACs on the chip discussed here, aswell as those on another subsequently tested, were addressablewith chip-wide common power and address levels.

Fig. 13 shows the boundary outside of which the probabilityof failing to increment a DAC stage is of order 0.1 orhigher. As mentioned in section II, we require the error rateto be considerably less than this. The dependence of error

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.42

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

4

Address (Φ0)

Bia

s C

urre

nt (

mA

)

COARSEFINE

Fig. 13. Combined operating margins in global power current (for one addresstree) vs. the magnitude of common address level for six coupler DACs fromthe same eight qubit circuit block. Two of these are addressed by one of theaddress trees on the chip, the rest by the other.

Fig. 14. Dependence of demultiplexer error rate on power current nearnominal address levels. At the operating point, Perr was bounded to be lessthan 2.5× 10−7 with 95% confidence.

probability in SFQ circuits has been studied in some detailby a few different groups [11]. However, we are interestedin the aggregate error probability of the entire demultiplexertree. The probability that a pulse fails to be loaded into a DACwas measured as a function of demultiplexer power at nominaladdress level, and is shown in Fig. 14.

As expected, the margins decrease as the error probabilityrequirement decreases. There is a significant power rangewith Perror < 10−6. At the chosen operating point, noerrors were seen in over 15,000,000 operations, which placesan upper bound Perr < 2.5 × 10−7 with 95% confidence.Reference [12] reports error probability of less than 10−8 fora similar demultiplexer tree.

It is not sufficient that the address tree route pulses to theaddressed DAC. Rather, it must do so exclusively, and notroute pulses to any other DAC. Confirming that pulses arrivedat the intended location, a requirement to attain the data shownabove, is not sufficient to demonstrate exclusivity.

Indeed if significantly overpowered, with no address ap-plied, the demultiplexer tree is capable of operating in abroadcast mode, where pulses are duplicated rather than

10

routed at each 1:2 demultiplexer node. While this should nothappen under normal circumstances, failure to test for thiswould be an oversight.

Testing exclusivity was performed for most of the DACs onthis chip with the following protocol:

1) choose a particular DAC stage (COARSE or FINE of aparticular DAC)

2) verify that this DAC responds correctly when addressed3) Send pulses to every other DAC stage on that tree,

and confirm that the state of the particular DAC is notaffected.

This was repeated for many of the DACs on the chip at thenominal power and address levels and address tree exclusivitywas confirmed in each case.

V. CONCLUSION

We have presented a description of a functioning systemof on-chip programmable control circuitry designed to manip-ulate the parameters and state of rf-SQUID superconductingqubits for use in implementing AQO algorithms. The systemis inherently scalable, and in turn allows specialized AQOhardware to be scaled to very large numbers of devices.

Based on classical manipulation of single quanta of mag-netic flux, the system was implemented in a planarized foursuperconductor metal layer process with 0.6µm minimumjunction diameter and 0.25µm lines and spaces for wiring. Thecontrol system was fabricated on-chip, in the same process asthe qubits and inter-qubit couplers.

Both the two-stage flux DACs used to manipulate thevarious controls on the qubits, and the demultiplexer addresstree used to address those DACs were shown to work asintended. The address tree is shown to pass SFQ pulses withvery low error rate, and to address the DACs exclusively. Thetwo-stage DAC design was shown to be effective at providinga flux bias with a dynamic range in excess of eight bits ofprecision (at dc). The design targets on several variants of DACwere presented, and while the variations between designed andachieved flux coupled into target sometimes reached 30%, thisis close enough to satisfy our current requirements.

While the control system described here was designed tooperate an AQO processor, it is probable that the devicesdescribed - programmable flux DAC, programmable variablegain element, SFQ demultiplexer tree - can be used to controlother types of quantum information processors implementedwith superconductors.

REFERENCES

[1] W.M. Kaminsky, S. Lloyd and T.P. Orlando,arXiv:quant-ph/0403090v2.

[2] K. K. Likharev and V. K. Semenov, IEEE Trans. Appl. Supercond., 1, 3,(1991). J.P. Hurrell, D. C. Prodmore Brown, A. Silver, IEEE Transationson Electron Devices, October 1980, 1887-1896.

[3] L.A. Abelson and G.L. Kerber, ”Superconductor integrated circuit fab-rication technology,” Proc. IEEE, vol.92, pp. 1517–1533, Oct. 2004;A Silver, A Kleinsasser, G Kerber, Q Herr, M Dorojevets, P Bunykand L Abelson, “Development of superconductor electronics technologyfor high-end computing” Supercond. Sci. Technol. 16 1368–1374, 2003;http://www.hypres.com/pages/foundry/bfoundnio.htm

[4] R. Harris, T. Lanting, A. J. Berkley, J. Johansson, M. W. Johnson,P. Bunyk, E. Ladizinsky, N. Ladizinsky, T. Oh, and S. Han, “A CompoundJosephson Junction Coupler for Flux Qubits With Minimal Crosstalk”

[5] to be published - Description of Qubit Design[6] A. J. Berkley, M. W. Johnson, P. Bunyk, R. Harris, J. Johansson,

T. Lanting, E. Ladizinsky, E. Tolkacheva, M. H. S. Amin, G. Rose,“A scalable readout system for a superconducting adiabatic quantumoptimization system”, arXiv:0905.0891v1

[7] S. Han, J. Lapointe, and J. E. Lukens, “Thermal Activation in a Two-Dimensional Potential”, Phys. Rev. Lett., 63, 1712 (1989).

[8] L.A. Abelson, K. Daly, N. Martinez, and A.D. Smith, ”LTS Josephsonjunction critical current uniformities for FINE applications,” IEEE Trans.Appl. Supercond., Vol. 5, pp. 2727-2730, 1995; Nakada, D.; Berggren,K.K.; Macedo, E.; Liberman, V.; Orlando, T.P., ”Improved critical-current-density uniformity by using anodization” /em IEEE Trans. Appl.Supercond., Volume 13, Issue 2, June 2003 Page(s): 111 - 114

[9] R. Harris, A. J. Berkley, J. Johansson, M. W. Johnson, T. Lanting,P. Bunyk, E. Tolkacheva, E. Ladizinsky, B. Bumble, A. Fung, A. Kaul,A. Kleinsasser, and S. Han; “Implementation of a Quantum AnnealingAlgorithm Using a Superconducting Circuit”, arXiv:0903.3906v1, 23March 2009

[10] A. M. Savin, J. P. Pekola, D. V. Averin, V. K. Semenov, “Thermal budgetof superconducting digital circuits at sub-kelvin temperatures”, J. Appl.Phys. 99, 084501 (2006)

[11] Herr Q. P., Feldman M. J., Error rate of a superconducting circuit Appl.Phys. Lett. 69, 694 (1996); Herr Q. P., Johnson M. W., Feldman M.J., ”Temperature-dependent bit-error rate of a clocked superconductingdigital circuit”, IEEE Trans. Appl. Supercond.1999, vol. 9 (3), No. 2, pp.3594-3597; Satchell, J., “Limitations on HTS single flux quantum logic”IEEE Trans. Appl. Supercond. Volume 9, Issue 2, Jun 1999 Page(s):3841- 3844

[12] to be published - E. M. Chapple, M. W. Johnson, P. Bunyk, E.Tolkacheva, I. Perminov, A. B. Wilson, F. Maibaum, A. K. Fung, B.Bumble, A. Kaul, A. Kleinsasser “Design and test of an asynchronousSFQ demultiplexer for applying on-chip flux signals”