a modular all digital pll architecture enabling both 1-to-2 … · 1 a modular all digital pll...
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A Modular All Digital PLL Architecture Enabling Both 1-to-2 GHz and 24-to 32-GHz Operation in 65nm CMOS
A. V. Rylyakov1, J. A. Tierno1, D. Z. Turker2, J.-O. Plouchart1H. A. Ainspan1, D. J. Friedman1,1IBM T.J. Watson Research Center, Yorktown Heights, NY2Texas A&M University, College Station, TX
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Outline
• Introduction• DPLL architecture and digital design details • DCO designs• Measurement results• Conclusion
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Introduction/Motivation
• Modular DPLL architecture demonstrated – Realization in 2 GHz ring-based and 6 GHz,
11 GHz, and 32 GHz LC-DCO-based designs– Core loop elements common to all
• Custom elements per design restricted to– Fractional-N capability added to ring design– Extra dividers added to LC-DCO designs to
bring feedback clock within usable frequency range
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Modular Digital PLL Architecture
DCO
output ∆ΣM
3
inc/dec
coarse
with row/colcontrols
2
dither
• Common core digital components used in multiple designs
BB-PFD LF
1/N1/16
or 1/4
LC-DCO versions
early/latereference 8
clkg
∆ΣMring-DCO version
16 8
1/Mphold
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Loop FilterP = Proportional constantI = Integral constant
+I+P+I-P-I
-I
11
10
01
00
2
integral: 1 X 1 – z-11
proportional: (1 – z-1) X 1 – z-11
Realized Transfer Functions
8 8
IncDec
8Late
8FractionalFrequency
8-bit arithmetic realizedusing Kogge-Stone adder
Merging proportional, integral paths simplifies DPLL logic
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8-bit Parallel (Kogge-Stone) AdderCarry generation
Loop Filter Integrator
K K K K K K
K K K KC8 C7 C6 C5 C4 C3 C2 C1
Feedback Divider ∆Σ AccumulatorsUniversal block, used in:
A7 B7 A0 B0. . . . . . . . . . K Maps A, B to
generate (g), propagate (p) signals
K
gi,pi gj,pj
g,p
g = gi + gj pi
p = pi pj
Carry operator
(Brent-Kung)
K K K K KK K K
K K K KK K K
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Divider ∆ΣΜ vs DCO ∆ΣΜ• Requires explicit 8-bit adders• Requires signed arithmetic• Pipelining requires careful
latency matching for proper noise shaping
• Uses DCO as an adder• Generates DC offset (invisible
due to loop action)• Dithering outputs are applied
in parallel with matched delays
+ Z-1 +N+FN+(z-1-1)*e1 N+FN+(z-1-1)2*e2
N“+”DCO
+ Z-1 + Z-1
Z-1
e1
Z-1 Z-1
e2 + Z-1 + Z-1
Z-1
e1
Z-1 Z-1
e2
Z-1
FN
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DPLL Internal Clocking
+1
const
phold
clkg
• phold is a masking signal• divided clkg is compared with reference in PFD• const can be updated between phold rising edges
phold
output*clkg
divided clkg*6/11/32 GHz LC-VCO cases
Timing diagram
Multi-modulus dividerdivided clkg
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Modular DPLL Architecture: Annotated
BB-PFD LF
DCO
output reference∆ΣM
8 3
inc/decearly/late
coarse+ +-P-I +
+I+P+I
-I2
ditherwith
row/colcontrols
LC-DCO version
1/16 or 1/4
+
phold
output clkg
1/N clkg
∆ΣM
ring-DCO version
16 8
1/Mphold
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columns 1 to 40
row
s 1
to 8
2 top rows
8 coarse rows
shiftcontrol
inc/
dec
1 2 3 4 5 1main array
inv_oncoar
se <
1:8>
• Target frequency range: 1 to 2 GHz• Target KDCO < 10 MHz / inverter
row+1
row
col
5-Stage Ring DCOinc/dec dither <1:3> output
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32 GHz LC DCO Topology
VDDA
to 1/16 divider
CML
VDDA
dither <1:3>, inc/dec
cap_hi <1:24>
coarse <1:4>
shiftcontrol
row/column logic
inc/dec
<1:4> Circled elements differ between 32 and 6/11 GHz VCOs[as do L, C values]
<1:24>
Varactor: NFET<1:5>
output
IREF
output_b
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6, 11 GHz LC DCO Topology
VDDA
to 1/4 divider
CMOS
VDDA
dither <1:3>, inc/dec
cap_hi <1:48>
coarse <1:4>
shiftcontrol
row/column logic
inc/dec
<1:4> Circled elements differ between 32 and 6/11 GHz VCOs[as do L, C values]
<1:48>
Varactor: accumulation-mode<1:5>
output
IREF
output_b
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Ring DCO: Open Loop Tuning Curves
DCO Main Array Fill Factor*
Freq
uenc
y [G
Hz]
0 1/4 1/2
VDDA =1.2V
25°C100°C
4
3
2
1
0 1/4 1/2 3/4 1
VDDA = 0.8V
25°C100°C
1
0.5
2
1.5
3/4 1
• KDCO = 2.6 MHz/inverter at 0.8V, 100°C• KDCO = 6.1 MHz/inverter at 1.2V, 25°C
*Array Fill Factor = On-state inverters / Total number of inverters
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Ring-DPLL: Period Jitter Histogram
484 488480 492
Line
ar s
cale
Average period: 485.44 ps (2.06 GHz, N = 160) Jitter: 1.0 ps rms, 16.6 ps peak-to-peak (3.8 million cycles)
Time [ps]
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Measured period jitter at 2.06 GHz (1 million cycles)• N=80: 1.1 ps rms, 16.3 ps pk-to-pk• N=79.996, 1st order ∆ΣM: 1.2 ps rms, 21.7 ps pk-to-pk• N=79.996, 2nd order ∆ΣM: 1.5ps rms, 25.8 ps pk-to-pk
Reference clock: 25.75 MHzVDDA=VDD=1.1V, 15mA, 25°C
Fractional-N Period Jitter Histograms
Time [ps]476 496486
Num
ber o
f cou
nts
101
102
103
N =79.996, 2nd order ∆ΣMN =79.996, 1st order ∆ΣMN =80
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Ring-DPLL DynamicsTi
me
, 2 m
s sp
an
N = 97
N = 103
N jumps from 103 to 97
15 MHz referenceI = 2-8
Frequency: 1.5 GHz center, 110 MHz span
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Ring-DPLL Dynamics IITi
me
, 2 m
s sp
an
N = 97
N = 103
N jumps from 103 to 97
15 MHz referenceI = 2-6
increase in integration constantreduces relock time
Frequency: 1.5 GHz center, 110 MHz span
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Ring-DPLL Dynamics IIITi
me
, 1.8
ms
span
Frequency: 2.0 GHz center
One coarse row is switched off
DPLL relocks to the original frequency by populating an extra row in the main array
110 MHz span
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Ring-DPLL Dynamics IVTi
me
, 1.8
ms
span
Frequency: 1.9 GHz center
Same experiment repeatedat lower center frequency One coarse row is switched off
Frequency: 2.0 GHz center
110 MHz span 110 MHz span
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Ring-DPLL Dynamics VTi
me
, 2 m
s sp
an
Frequency: 1.5 GHz center, 110 MHz span
15 MHz referenceI = 2-8
One coarse rowis switched off and N jumps from 103 to 97
N = 103
N = 97
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32 GHz LC-DCO Tuning Curves
DCO Main Array Fill Factor0 1/4 1/2 3/4 1
Freq
uenc
y [G
Hz] 30
32
28
26
24 LC-DCO, 1.5V
25°C85°C
KDCO=76 MHzper varactor
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Pow
er [d
Bm
]-20
-40
-60
-80
-100
Spectrum of 32 GHz Output
32.0 32.1Frequency [GHz]
Span: 200MHz. Resolution bandwidth: 10kHz.
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LC-DPLL Phase Noise Plot at 32 GHz
-120
-110
-100
-90
-80
-70
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
Frequency Offset [Hz]
Pow
er [d
Bc/
Hz]
• measured at VDDA=1.5V (36mA), VDD=1.3V (12.2mA), 25°C, 2 GHz reference
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6 and 11 GHz DCO Tuning Curves
5.0
5.5
6.0
6.5
7.0
7.5
1
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
1
0 1/2 1 0 1/2 1
Freq
uenc
y [G
Hz]
1.2V, 100°C 1.3V, 25°C
5.0
7.5
6.0
7.0
11.0
9.0
KDCO=15.6 MHzKDCO=9.5 MHz
DCO Main Array Fill Factor
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6 and 11 GHz DPLL Phase Noise
10 GHz, 1.3V, 25°C4.8 GHz, 1.2V, 25°C
-130
-120
-110
-100
-90
-80
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Pow
er [d
Bc/
Hz]
-130
-120
-110
-100
-90
-80
-70
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08
Frequency Offset [Hz]
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32 GHz LC-DPLL Die Photograph
Digital CMOS Core
CML PrescalerOutput Driver
LC-DCO
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DPLL Performance Summary
-97 dBc/Hz at 32 GHz
-80 dBc/Hz at 2 GHz
-111 dBc/Hz at 4 GHz
Phase Noise3
24 GHz – 32 GHz0.5 GHz – 4.4 GHz0.5 GHz – 8 GHzTuning Range
15.9 mWat 32 GHz
8.3 mWat 2 GHz
15.6 mWat 4 GHz
Logic
54 mWat 32 GHz2
11.4 mWat 2 GHz
18.0 mWat 4 GHz
DCO
Power
240 µm X 350 µm180 µm X 270 µm200 µm X 150 µmArea
65nm bulk65nm bulk65nm SOI CMOS Technology
LC-tank DPLL5-stage ring DPLL3-stage ring DPLL1
1 ISSCC 2007, “A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS ADPLL in 65nm SOI”2 Including the 1/16 pre-scaler and the output driver 3 At 1 MHz offset
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Conclusion• Modular All-Digital PLL architecture demonstrated on 4
different design points: 2 GHz (ring-DCO) and 6,11 and 32 GHz (LC-DCO)
• Common core digital blocks shared between designs,easily mapped to different technologies
• Ring-DPLL tuning range and period jitter performance adequate for ASIC and microprocessor clocking applications
• LC-DPLL phase noise affected by limit cycle, typical of bang-bang digital PLLs