a low area overhead ieee-1500-compliant wrapper for ...ieee std 1500 serial links [6]-[10]. in [6],...

Abstract—Integrating numerous cores of different types into

an SOC, makes the test process a complex activity. The need for

a standard test infrastructure has led to the development of

IEEE Std 1500 which is a modular and scalable test interface,

enables test and diagnosis of embedded cores and interconnect.

Although this standard can drastically simplify test challenges

of SOCs, its hardware architecture, usually called wrapper,

may occupy a noticeable silicon area when used for memory

cores. In this paper, we present a specialized wrapper for

memory cores compatible with IEEE Std 1500 which support

parallel and at-speed testing of all memory cores with

reasonable area overhead. We specially focus on the design of

Wrapper Boundary Register which is mostly responsible for

this overhead. Simulation and synthesis results on a group of

embedded memory cores confirm that the proposed wrapper

has been effectively reduced the area overhead.

Index Terms—Embedded memory testing, system-on-chip

(SoC), built-in-self-test (BIST), IEEE Std 1500, wrapper

boundary register (WBR).

I. INTRODUCTION

Today, the fast innovation in VLSI technology enables

design of complex systems on a single chip. Although system

chips offer advantages such as higher performance, lower

power consumption and smaller volume and weight, the

recent methods of design like synchronous production of

different cores and using reusable and heterogeneous IP

cores, poses new test constraints to the test community [1].

On the other hand, since direct access to core ports is

virtually impossible, the basic features of testability like

controllability and observability are hard to achieve [1], [2].

All these issues have led to the development of IEEE Std

1500 for embedded core testing which defines a scalable

architecture for independent and modular test development,

and test application for embedded design blocks [3]. This

standard handles two main requirements i.e. easy integration

and interoperability on one hand, and flexibility and

scalability on the other hand. The second feature makes the

standard adjustable with any test method which depends on

the core types.

One of the core types which occupy a significant part of

the chip is memory cores. The high density of embedded

memory cores makes them more prone to manufacturing

defects than other types of on-chip circuitries. Since direct

access to memory ports is virtually impossible and at-speed

Manuscript received August 18, 2012; revised October 7, 2012.

M. Songhorzadeh is with the Department of Electrical Engineering at

Shahid Chamran University of Ahvaz, Iran (e-mail:

[email protected]).

R. Niaraki Asli is with the Electrical Engineering Department, University

of Guilan, Guilan, Iran (e-mail: [email protected])

testing is difficult to achieve, BIST is a more practical

method to test and diagnose embedded memories [4]. But a

serial BIST like BIST based on IEEE Std 1500, has a long

and unacceptable test and diagnosis time, because this

standard can’t implement a parallel test and manage multiple

cores concurrently [5]. On the other hand, the area overhead

of IEEE Std 1500 wrappers are high, which is mostly due to

Wrapper Boundary Register. Since most embedded memory

cores have wide data word, the number of wrapper boundary

cells increases significantly which directly influence the area

overhead of the wrapper.

Researchers have proposed several BIST schemes using

IEEE Std 1500 serial links [6]-[10]. In [6], a modular test

wrapper for small wide memories has been introduced. The

interfaces between the memories and BIST circuit are based

on IEEE Std 1500. This scheme can implement at-speed test

at low area overhead. In [7]-[9], a serial test interface based

on IEEE 1500 for small memories has been proposed. But the

area overhead of the IEEE Std 1500 wrappers is high. On the

other hand, testing multiple memories using a serial BIST

based on IEEE std 1500 requires a long and intolerable test

time. In [10], another wrapper based on IEEE Std 1500 is

introduced which is in complete accordance with the standard

but has no modification and optimization for memory testing,

so it can’t support at-speed and parallel test.

In our previous work, we presented a structure for an

IEEE Std 1500 wrapper optimized for Built-In-Self-Test of

embedded memory cores. This structure is capable of

implementing at-speed and parallel test of multiple memory

cores concurrently. Although the area overhead improved

compared to the existing schemes, its main drawback still

lain in the significant amount of occupied silicon area. So in

this paper, we mainly focus on the design of Wrapper

Boundary Register which is responsible for high area

overhead of IEEE 1500 wrappers. We design a new structure

for wrapper boundary cells with lower area overhead allows

for preserving previous functionalities.

The organization of this paper is as follows: Section 2

presents a brief explanation about the general specification of

the proposed IEEE Std 1500 wrapper. In Section 3, we

describe the structure of the proposed Wrapper Boundary

Register in detail and compare it with the previous one.

Section 4 is allocated to the results of simulation and

synthesis on a group of embedded memory cores that confirm

the proposed structure effectively reduces the area overhead.

The paper is concluded in Section 5.

II. EMBEDDED MEMORY WRAPPER (EMW) STRUCTURE

Fig. 1 shows a memory core surrounded by the proposed

IEEE-1500-compliant wrapper we called it EMW. This

A Low Area Overhead IEEE-1500-Compliant Wrapper for

Embedded Memories

M. Songhorzadeh and R. Niaraki Asli

International Journal of Computer Theory and Engineering, Vol. 4, No. 6, December 2012

944

structure is composed of a Wrapper Instruction Register

WIR

WBY

WDR

Memory

Core

W

B

R

W

B

R

WSPFrom BIST

controller

WSO

WIR

_W

SO

WBR_WSO

WDR_WSO

WB

Y_W

SO

WBR_WSI

WDR_WSI

WB

Y_W

SI

Fig. 1. The overall structure of the IEEE-1500-compliant wrapper (EMW).

(WIR) circuitry, a Wrapper Boundary Register (WBR), a

Wrapper Bypass register (WBY), a Wrapper Data Register

(WDR) and two multiplexers. All components of EMW are

specialized for memory core testing while adopting with

IEEE Std 1500. In the reminder of the section, we describe

EMW components in short detail.

One of the basic parts of the wrapper is WIR circuit which

receives Wrapper Serial Port (WSP) signals from a BIST

controller as an input. The main function of WIR circuit is to

generate control and input signals for other components of

the wrapper and gather test responses. Our proposed WIR

circuit is composed of three main parts which are WIR

Controller, WIR Register and WIR Selector. WIR controller

is used to generate control signals of the wrapper and

receives all WSP signals in addition to a signal for parallel

shift from the BIST controller. Initializing the modified WSP

through the BIST controller can produce different

instructions which are received by WIR register and set the

whole wrapper in each of the operational modes. When there

is no instruction to shift, this register shifts the current

operational mode data. The last part of WIR circuit is the

selector which set only one of the wrapper registers between

serial input and output signals of the wrapper based on IEEE

std 1500.

Another part of the wrapper is WBY which is a one bit

register and bypasses the wrapper in functional mode.

To support diagnosis capability, we add an optional

register called WDR to shift test results out. When the

memory is under test, this register is set between Wrapper

Serial Input and Wrapper Serial Output signal and shifts the

diagnosis information out.

Finally the last part of the wrapper is WBR which has the

responsibility of applying test and functional stimulus to the

core and receiving core responses. In our previous work, we

designed a WBR specialized for memory testing which was

capable of supporting at-speed and parallel test. Although

this proposed register had a lower area overhead compared to

the existing scheme, but in this paper we improve its area

overhead. In the next section, we describe the proposed

structure of this WBR and compare it with the new design.

III. WRAPPER BOUNDARY REGISTER (WBR)

A. Structure of Previous WBR

Fig. 2 shows the structure of the proposed WBR which is

specialized for Built-In Self-Test of embedded memory cores.

The main function of this register is to apply test and

functional stimulus to the core and receive the core responses

through input and output cells respectively. The operation of

the register is determined by the instruction shifted to WIR

register. This instruction initializes WBR control signals and

set it in each of the of the wrapper operational modes.

Input_1

Input_n

Input_2

Output_1

Output_n

Output_2

WFI_1

WFI_n

WFI_2

WPI_1

WPI_3

WPI_2

WPI_n

WFO_1

WFO_n

WFO_2

Memory

Core

0

0

0

0

1

1

1

1

WPO_1

WPO_n

WPO_2

WBR_S_shiftWBR_P_shift

WBR_WSI

WBR_WSO

CFO

CTO

CFI

CTI

CFO

CTO

CFI

CTI

CFO

CTO

CFI

CTI

CFO

CTO

CFI

CTI

CFO

CTO

CFI

CTI

CFO

CTO

CFI

CTI

Fig. 2. The proposed structure for previous WBR.

As seen in Fig. 2, the proposed WBR is composed of

several input and output cells, multiplexers and some glue

logics. Fig. 3 and 4 show the design of input and output cells,

respectively. These cells are designed to operate in each of

the three mandatory modes of IEEE 1500 Std which are

functional, internal test and external test.

Each cell has two input and output ports for shifting

functional and test data. CFI (Cell Functional Input) and CFO

(Cell Functional Output) ports are used to receive and

0

1

CFI

CTI

CFO

CTO

WBR_capture WRCK

WRSTN

D Q

R


Fig. 3. The proposed structure for WBR input cell.

0

1

CFI

CTI

CFO

CTO

WBR_capture

WRCK

WRSTN

D Q

R


Fig. 4. The proposed structure for WBR output cell.


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shift out the functional data, while CTI (Cell Test Input) and

CTO (Cell Test Output) ports are allocated to receive and

shift out the test data. The operation of the cells is controlled

through three control signals derived from the modified WSP.

WBR_s_shift and WBR_capture signals are derived from

shiftWR and captureWR signals of the modified WSP

respectively, while WBR_p_shift is resulted from an optional

signal called WPP_shift added to WSP for enabling parallel

shift of WBR cells. Table I shows the value of each control

signal in different operational modes.

TABLE I: THE VALUE OF THE PREVIOUS WBR CONTROL SIGNALS.

Mode WBR_S_shift

WBR_P_shift

WBR_capture

Functional 0 0 0

Internal Test 0 1 1

External Test 1 0 1

One of the most important points in memory testing is

at-speed test for detecting delay faults. Since IEEE std 1500

needs many clock cycles to shift in test commands, update

operation to the memory and capture and shift out memory

responses, BIST based on this standard have a long test time

and cannot test the memory at-speed.

In the proposed structure, due to parallel applying test

stimulus and receiving memory responses, test data can send

to memory in each clock cycle and the memory responses

compare in real time. In every rising edge of the clock cycle,

test data is set in the input cells and applied to the memory in

the falling edge of the clock. This is the same for output cells,

where memory responses is set in output cells in the rising

edge of the clock and shift out in the falling edge of the clock.

This time scheduling not only reduces test time, but also

applies valid data to memory in each clock cycle.

To realize this approach, a design like Fig. 2 is used. As

can be seen, a 2-to-1 multiplexer is set between two input

cells. One input of this multiplexer is used only for parallel

test and the other derives from CTO of the previous cell to

produce a scan chain. Similarly, some glue logics set between

output cells and implement the same operation.

B. Structure of New WBR

Although the proposed structure can effectively test the

memory cores in a parallel and at-speed way, but its high area

overhead is an important drawback. In a typical IEEE std

1500 wrapper structure, WBR has the most area overhead

compared to the other elements. This is due to the massive

number of input and output ports in a memory core which

needs a large number of WBR cells to form WBR. So if we

can compact WBR cells, the area overhead of WBR is

reduced effectively.

In our approach, per core terminal, a wrapper cell is added

to the wrapper which only depends on the direction (input,

output) of the core terminal. The functionality of the cells is

determined by the current operation mode which can set the

cells in each of the two types (functional only, test data) and

can be used for each of the memory core terminals (assuming

test control signals are always input to the cores).

Fig. 5 and 6 show the new design of WBR cells which are

composed of a less number of logic gates while preserve the

functionality in three operational modes. In table II, the value

of control signals in three different operational modes for

new WBR cells is shown.

These cells have three control signals like the previous

version and so can be imported in the previous wrapper

structure. This library of wrapper cells has the following

properties:

1) Access for functional mode, as well as core-internal and

core-external testing

2) Capability of implementing core-internal testing in a

parallel and at-speed form

3) Specially designed for memory core testing

4) Low area overhead compared to the previous design

The structure of the new WBR composed of new cells is

shown in Fig. 7.

0

1

CFI

CPTI

D Q

R

0

1

CTO

CFO

WBR_capture

WBR_S_shift

WBR_P_shift

CSTI

WRCKWRSTN

Fig. 5. The proposed structure for new WBR input cell.

WBR_captureD Q

R

WBR_P_shift

WBR_S_shift

0

1

CFICPTO

CSTI

CTO

CFO

WRCKWRSTN

Fig. 6. The proposed structure for new WBR output cell.

TABLE II: THE VALUE OF THE NEW WBR CONTROL SIGNALS.

Mode WBR_S_shift

WBR_P_shift

WBR_capture

Functional 0 X 0

Internal Test X 0 1

External Test 1 1 X

IV. SIMULATION AND SYNTHESIS RESULTS

In order to evaluate the proposed design, it has been

simulated and synthesized with Xilinx 11.1 for memories of

different configurations. It is synthesized using Xilinx 11.1

with 0.18 CMOS standard cell library. At first, we


946

synthesized the new wrapper for a 16K×16 SRAM to

evaluate test time. Table III shows the results of test time for

some march algorithms with different test time which is

dependent to the length of the algorithm. The proposed

structure guarantees an at-speed test with the 145.8MHz

clock frequency and it has an access time of 6.8 ns which are

resulted from the synthesis. These values are obtained

assuming at-speed test is implemented by the BIST structure.

Input_1

Input_n

Input_2

Output_1

Output_n

Output_2

Memory

Core

CFO

CTO

CFI

CSTI

CPTI

CFO

CTO

CFI

CSTI

CPTI

CFO

CTO

CFI

CSTI

CPTI

CFO

CSTI

CFI

CTO

CPTO

CFO

CSTI

CFI

CTO

CPTO

CFO

CSTI

CFI

CTO

CPTO

WBR_WSI WBR_WSO

WPI_1

WPI_2

WPI_n

WFI_1

WFI_2

WFI_n WFO_n

WPO_n

WFO_2

WPO_2

WFO_1

WPO_1

Fig. 7. The proposed structure for new WBR.

TABLE III: TEST TIME FOR THREE DIFFERENT ALGORITHM USING EMW ON

A 16×16K SRAM

Test Time March Algorithm

7.616 ms March RABL

4.787 ms March BDN

3.046 ms March LR

To study the area overhead of the new design, we

synthesized both structures with Xilinx 11.1 and compared

the results. As we explain before, the main drawback of the

previous structure was the area overhead which arose from

WBR. By designing new wrapper boundary cells with lower

area overhead, we overcome this problem. The new cells

preserve their functionality to operate in three IEEE Std 1500

mandatory modes and have three control signals like the

previous ones. So the new WBR can be imported into the

previous structure.

Table IV summarizes the results on area overhead for the

two proposed structures. These wrappers are both

synthesized for a 16K×16 SRAM and using 0.18 CMOS

standard cell library. The first column denotes the

components that constitute the whole wrapper. The second

and third columns denote the number of gates for the two

wrapper structures. The results show the area overhead of the

new wrapper is 8.4% improved compared to the previous

one.

Also to evaluate the area overhead of the proposed

wrapper for different memories, it is simulated and

synthesized using Xilinx 11.1 for memories with various size

and configurations. Table V summarizes the synthesis results

on area overhead of the proposed wrapper. The first column

of the table represents the memory configuration. The second

and third columns represent the area overhead of the wrapper

based on the number of gates and silicon area respectively.

Finally the last column shows the overhead relative to the

pure memory. The memories are high density embedded

SRAMs and the wrapper structure is synthesized using

0.18um CMOS standard cell library. In Table V, N×W

memory configuration denotes a memory with N words and

each word has W bits. As can be seen, by increasing the size

of the memory, the area overhead is significantly decreasing.

Because by changing the configuration of the memory, only

the number of the input and output cells of the WBR needs to

be changed and the rest of the structure is the same for

memories of different configuration. On the other hand, due

to the results of table IV, WBR has the most area overhead.

So by decreasing the number of cells compared to the

memory size, the area overhead reduced significantly.

TABLE IV: COMPARISON THE AREA OVERHEAD OF THE NEW WRAPPER

WITH THE PREVIOUS ONE.

# of gates in

new Wrapper

# of gates in

previous Wrapper Wrapper Components

16 16 WBY

50 50 WDR

750 864 WBR

426 426 WIR circuit

1242 1356 Total(Wrapper 16K×16)

TABLE V: WRAPPER AREA OVERHEAD FOR DIFFERENT MEMORY SIZES。

Area overhead area (mm2) # of gates Memory size

3.3% 0.0125 1212 4 K×16

0.84% 0.0128 1242 16 K×16

2.3% 0.0174 1692 4 K×32

0.58% 0.0177 1722 16 K×32

1.79% 0.0273 2652 4 K×64

0.45% 0.0276 2682 16 K×64

V. CONCLUSION

In our previous work, we proposed the structure of an

at-speed IEEE std 1500 wrapper which optimized for

memory core testing. The proposed wrapper has the

capability of implementing parallel test and handling

multiple cores concurrently. Although the structure had a low

area overhead compared to some existing schemes, but its

high area overhead was the main drawback. In this paper, we

compact WBR cells to reduce the overhead of WBR which is

responsible for this high area overhead. The new WBR

design has three control signals like the previous scheme and

preserves its previous functionalities to operate in three

mandatory modes of IEEE std 1500 and so can be imported in

our previous wrapper design.

REFERENCES

[1] B. H. Fang, Embedded Memory BIST for Systems-on-a-Chip, M.S.

thesis, McMaster University, Hamilton, Ontario, Canada, 2003.

[2] A. Larsson, Test Optimization for Core-Based System-on-Chip, Ph.D.

dissertation, Linköpings Univ, 2008.

[3] IEEE Standard Testability Method for Embedded Core-based

Integrated Circuits- IEEE Std 1500™-2005, IEEE Computer Society,

New York, 2005.


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[4] B. N. Dosite, S. M. I. Adham, and R. Abbott, “Improved core isolation

and access for hierarchical embedded test,” IEEE Computer Society

Press, vol. 26, no. 1, pp. 18-25, 2009.

[5] L. M. Denq, Y. T. Hsing, and C. W. Wu, “Hybrid BIST scheme for

multiple heterogeneous embedded memories,” in Proc. IEEE Design

and Test of Computers Conf., 2009, pp. 64-73.

[6] R. C. Aitken, “A modular wrapper enabling high speed BIST and repair

for small wide memories,” in Proc. Int’l Test Conf.(ITC04), IEEE CS

Press, 2004, pp. 997-1005.

[7] B. V. Dostie, A. Silburt, and V. K. Agarwal, “A serial interfacing

technique for external and built-in self-testing of embedded memories,”

IEEE Design and Test of Computers, vol. 7, no. 2, pp. 56-64, 1990 .

[8] W. B. Jone, D. C. Huang, S. C. Wu, and K. J. Lee, “An efficient bist

method for small buffers,” in Proc. IEEE VLSI Test Symp. (VTS), 1999,

pp. 246-251.

[9] D. C. Huang and W. B. Jone, “A parallel built-in self -diagnosis method

for embedded memory arrays,” IEEE Trans. On Computer-Aided

Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 449-465,

2002.

[10] G. Squillero and M. Rebaudengo, “Test Techniques for Systems-on-a-

Chip,” Politecnico di Torino, 2005.

Maryam Songhorzadeh received her B.S. degree in

Electronic Engineering from the University of Isfahan,

Iran, in 2006. She received her M.S. degree in

Electronic Engineering from the University of Guilan,

Rasht, Iran, in 2010. She is currently pursuing her

Ph.D. in Electronic Engineering at Shahid Chamran

University of Ahvaz, Iran. She is working as a research

assistant at Dideh Pardaz Saba Corporation, Isfahan,

Iran. Her research interests include design for

testability, embedded memory testing and diagnosis and statistical signal

processing.

Rahebe Niaraki Asli received her B.S. and M.S.

degrees in Electronic Engineering from the University

of Guilan, Rasht, Iran, in 1995 and 2000, respectively.

Also, she received Ph.D. degree in electrical

engineering from the Iran University of Science and

Technology, Tehran, Iran, in 2006. From 1995 to 2002

she has worked in electronic laboratories of the

Department of Electrical Engineering in the University

of Guilan. During 2002 to 2006, she was with design

circuit research group in the Iran University of Science and Technology

electronic research center (ERC) and CAD research group of Tehran

University. Since 2006, she has been an Assistant Professor in Department of

Electrical Engineering, Engineering faculty of Guilan University. Her

current research interests include design for testability, embedded memory

testing, diagnosis, and repair, VLSI CAD design, and soft errors.

Author’s formal

photo


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a low area overhead ieee-1500-compliant wrapper for ...ieee std 1500 serial links [6]-[10]. in [6],...

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