a data remanence based approach to generate 100%...
TRANSCRIPT
International Symposium on Low Power Electronics and Design
A Data Remanence based Approach to Generate 100% Stable Keys from
an SRAM Physical UnclonableFunction
Muqing Liu, Chen Zhou, Qianying Tang, Keshab K. Parhi and Chris H. Kim
University of Minnesota, Twin Cities
• Introduction and Motivation
• Proposed Data Remanence based Approach
• SRAM PUF Measurement Results
• Summary
2
Outline
• Introduction and Motivation
• Proposed Data Remanence based Approach
• SRAM PUF Measurement Results
• Summary
3
Outline
4
Key Storage: Flash Memory
• Concerns: Process overhead; vulnerable to invasive/semi-invasive attacks.
5
Key Generation: SRAM based PUF
• Strength: No process overhead, negligible implementation effort.
Power-up state Uncontrollable process variationWL
BL BLBStable ‘1’Stable ‘0’ Unstable
6
Key Generation: SRAM based PUFUnique keySRAM array
Column Circuit
Ro
w C
ircu
it
Ctrl.
Stable ‘1’
Unstable
Stable ‘0’
• Concerns: Intrinsic mismatch of a SRAM cell not always large enough to generate stable responses.
Temporal Majority Voting (TMV)
• TMV: Repetitively test the PUF responses and take the majority value as the final output.
• Cons: Costly and time consuming, hardware overhead, cannot find absolutely stable bits.
6
• Introduction and Motivation
• Proposed Data Remanence based Approach
• SRAM PUF Measurement Results
• Summary
8
Outline
9
Data Remanence based Approach
10
Data Remanence based Approach
0
10
20
30
40
50
60
70
80
-25 -15 -5 5 15 25
Tfl
ip (
a.u
.)
Vmismatch (mV)
65nm LP, 25oC, TT, simulation
Stronger ‘0’ Stronger ‘1’
WL
BL BLB
Q QB
Vmismatch
Tflip
VDD SRAM data flips
• The first few cells to flip after the brief power down period are the most strongly biased cells.
• PXI based data acquisition system: provides pulsed power supply and digital signals.
• Power supply: stress the chip.
• Off-the-shelf SRAM chips: 512 kbit from Microchip Technology.
11
Measurement Set Up
Flip Ratio vs. Power Down Period
12
Strongest ‘1’
5
10
15
20
25
30
5
10
15
20
25
30
5
10
15
20
25
30
5
10
15
20
25
30
5 10 15 20 25 30 5 10 15 20 25 30
5 10 15 20 25 30 5 10 15 20 25 30
Data ‘1’ Data ‘0’
PD=130ms
PD=150ms
PD=140ms
PD=160ms
Ro
w #
Ro
w #
Ro
w #
Ro
w #
Column # Column #
Column # Column #
13
Cell Flip Map for Writing ‘0’
• Strongest ‘1’ cell always flips.
14
Strongest ‘0’
5
10
15
20
25
30
5
10
15
20
25
30
5
10
15
20
25
30
5
10
15
20
25
30
5 10 15 20 25 30 5 10 15 20 25 30
5 10 15 20 25 30
Data ‘1’ Data ‘0’
5 10 15 20 25 30
PD=130ms
PD=150ms
PD=140ms
PD=160ms
Ro
w #
Ro
w #
Ro
w #
Ro
w #
Column # Column #
Column # Column #
Cell Flip Map for Writing ‘1’
• Strongest ‘0’ cell always flips.
15
• Bit index is sorted from strongest ‘0’ to strongest ‘1’.
SRAM Data Remanence for Data ‘1’
0.2k
0.4k
0.6k
0.8k
1.0k100 125 150 175 200 225
128 bits256 bits
512 bits
Target pulse width
Bit
in
de
x (
so
rted
by
rete
nti
on
tim
e)
Power Down Period (ms)
0.0k100k
200k
300k
400k
500k
Data ‘1’
Data ‘0’0k
225 350 475 600100
16
• Bit index is sorted from strongest ‘0’ to strongest ‘1’.
SRAM Data Remanence for Data ‘0’B
it i
nd
ex (
so
rted
by
rete
nti
on
tim
e)
Power Down Period (ms)
100k
200k
300k
400k
500k
0k
225 350 475 600100
100 125 150 175 200 225
523.5k
523.7k
523.9k
524.1k
524.3k128 bits
256 bits
512 bitsTarget pulse width
Data ‘0’
Data ‘1’
17
Data Remanence and PUF Test Flow
Turn off power, wait for Trequire
Turn on power,
read out data
Record flip locations
Response (Keys)
Write all ‘1’ or ‘0’
Store stable bit location
Stable bit location
Power on SRAMTurn off power,
wait for time T
Turn on power, read out data
Record flip
location(s)
Write all ‘1’ or ‘0’
Data Remanence
Test
Trequire = T
SRAM PUF Operation
Enrollment Key Generation
Tmin < T < Tmax ?
Key length
Yes
No
• Introduction and Motivation
• Proposed Data Remanence based Approach
• SRAM PUF Measurement Results
• Summary
18
Outline
• Average inter-chip Hamming distance is 0.4935 (ideally close to 0.5).
19
Uniqueness of Generated Key
Chip 1
Data ‘1’ Data ‘0’
Chip 2
Chip 3 Chip 4
256-bit Key
• Average intra-chip Hamming distance is 0 under different temperatures.
20
PUF Stability: Temperature Effect
T = 80oCT = 25oCT = -10oC
Data Remanence based Approach
Power up ramp time = 0.78V/µs
Data ‘0’Data ‘1’
• Average intra-chip Hamming distance is 0.0026.
21
T = 80oCT = 25oCT = -10oC
TMV Selected Stable Cells
Power up ramp time = 0.78V/µs
Data ‘0’Data ‘1’Unstable cell
PUF Stability: Temperature Effect
22
T = 80oCT = 25oC
Randomly Selected Cells
Power up ramp time = 0.78V/µs
Data ‘0’Data ‘1’Unstable cells
T = -10oC
PUF Stability: Temperature Effect
• Average intra-chip Hamming distance is 0.081.
23
Data Remanence based Approach
T = -10oC
Power up ramp time = 0.78V/µs
Power up ramp time = 1.25V/µs
Power up ramp time = 8.33V/µs
Data ‘0’Data ‘1’
• Average intra-chip Hamming distance is 0 under different power ramp up rates.
PUF Stability: Power Up Ramp Effect
24
TMV Selected Stable Cells
T = -10oC
Power up ramp time = 0.78V/µs
Power up ramp time = 1.25V/µs
Power up ramp time = 8.33V/µs
Data ‘0’Data ‘1’Unstable cells
• Average intra-chip Hamming distance is 0.003.
PUF Stability: Power Up Ramp Effect
25
Randomly Selected Cells
T = -10oC
Power up ramp time = 0.78V/µs
Power up ramp time = 1.25V/µs
Power up ramp time = 8.33V/µs
Data ‘0’Data ‘1’Unstable cells
• Average intra-chip Hamming distance is 0.031.
PUF Stability: Power Up Ramp Effect
TMV selected stable cells
Unstable cells Data ‘0’Data ‘1’
Randomly selected cells
T =
80
oC
T =
25
oC
T =
-10
oC
This workPower up ramp time = 0.78V/µs
Power up ramp time = 1.25V/µs
Power up ramp time = 8.33V/µs
Avg. Intra-chip Hamming distance = 0 Avg. Intra-chip Hamming distance = 0.0091 Avg. Intra-chip Hamming distance = 0.0712
Power up ramp
time = 0.78V/µs
Power up ramp
time = 1.25V/µs
Power up ramp
time = 8.33V/µs
Power up ramp
time = 0.78V/µs
Power up ramp
time = 1.25V/µs
Power up ramp
time = 8.33V/µs
Overall PUF Stability Test
27
• 100% of the cells selected using proposed technique remain stable under device aging test.
Stress Time (hrs)0 10 20 30 40 50 60 70 80
0
0.05
0.1
0.15
0.2
Intr
a-c
hip
Ha
mm
ing
D
ista
nc
e
Stress: 1.5*Vnom, Measure: Vnom, 25oC
This work (256, 512, 1024-bit)
TMV (256, 512, 1024-bit)
Random (256, 512, 1024-bit)
PUF Stability: Aging Effect
• Proposed a data remanence based technique by momentarily shutting down the power supply to select the most stable cells as the key.
• Measurement results confirmed 100% key stability under different conditions:
– Temperature variations.
– Power ramp up rate variations.
– Device aging effect.
28
Summary
This research has been supported by the National Science Foundationunder grant number CNS-1441639 and the semiconductor researchcorporation under contract number 2014-TS-2560.
Acknowledgements