all-digital pll frequency and phase noise degradation...
TRANSCRIPT
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All-Digital PLL Frequency and
Phase Noise Degradation Measurements
Using Simple On-Chip Monitoring Circuits
Gyusung Park, Bongjin Kim*, Minsu Kim, Vijay Reddy** and Chris H. Kim
University of Minnesota, Minneapolis, MN, USA*Nanyang Technological University, Singapore
**Texas Instruments, Dallas, TX, USA
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• Experimental study of all-digital PLL (ADPLL) reliability issues
• ADPLL frequency and phase window measurements using on-chip monitors
Purpose
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Outline
• Motivation
• Proposed on-chip monitors
• 65nm ADPLL chip test setup
• Stress, recovery, annealing results
• Conclusions
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Target Circuit: All-Digital Phase Locked Loop (ADPLL)
Phase
Detector
PI
Controller
Digitally
Controlled
Oscillator
÷ N
Freq. Divider
Fout=N*Fref
0 or 1Control
outputFref
• Key building block for processor clock generation and wireless communication
• No prior work on ADPLL reliability behavior
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ADPLL Reliability Figure-of-Merit
• Frequency: open-loop and closed-loop
• Phase noise, jitter degradation
DCO: Digitally Controlled Oscillator
V. Reddy, et al., IEDM 2009
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Drawback of Conventional Off-chip Measurement
• Requires high speed probes or packages, off-chip drivers and connectors
• Each of these components introduces inaccuracy in the measurement
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Outline
• Motivation
• Proposed on-chip monitors
• 65nm ADPLL chip test setup
• Stress, recovery, annealing results
• Conclusions
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Beat Frequency Monitor
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“Silicon Odometer”, T. Kim, et al., JSSC 2008
• “Silicon odometer” beat frequency detection circuit adopted for frequency measurements
• Higher precision (~ps) and shorter measurement time (~μs) compared to simple counter based scheme
Co
un
ter
Re
se
t
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Beat Frequency Monitor Before Stress
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Beat Frequency Monitor Under Stress
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Phase Window Monitor
D. Jiao, JSSC 2012
• Clock period (including jitter) compared with tunable delay
• Indirectly measure phase noise by sweeping tunable delay
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Phase Window Measurement
• As tunable delay approaches the clock period, error rate increases
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Phase Window Measurement
• As tunable delay increases beyond the clock period, error rate decreases
• Phase window in right figure = a measure of phase noise
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Outline
• Motivation
• Proposed on-chip monitors
• 65nm ADPLL chip test setup
• Stress, recovery, annealing results
• Conclusions
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Die Photo and Chip Description
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Process 65nm CMOS
System All-Digital PLL
Nominal supply 1.2V
Stress supply 2.4V
Annealing temp. 110°C, 240°C
DCO frequency (free running)
720MHz @1.2V1.54GHz @2.4V
Circuit area 0.08mm2
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Measurement Setup
Pattern Generation & AcquisitionEquipment
Control software
Oscilloscope
Power Supply
Hot PlateDUT
No power
@ 110°°°°C, 240°°°°C
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Open-loop and Closed-loop Configurations
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• Stress mode: Stress supply (2.4V) for stressed DCO, 0V for reference DCO
• Measurement mode: Nominal supply (1.2V) for both stressed and reference DCOs
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Outline
• Motivation
• Proposed on-chip monitors
• 65nm ADPLL chip test setup
• Stress, recovery, annealing results
• Conclusions
![Page 19: All-Digital PLL Frequency and Phase Noise Degradation ...people.ece.umn.edu/groups/VLSIresearch/papers/2018/IRPS18_ADPLL_slides.pdf · Beat Frequency Monitor 8 “Silicon Odometer”,](https://reader035.vdocuments.mx/reader035/viewer/2022070703/5e7c1f1f61002008920c1427/html5/thumbnails/19.jpg)
Open-Loop Results: Frequency
• Stress BTI, HCI frequency degradation
• Natural recovery and annealing
• Cool down the chip after annealing remove anyresidual heat
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(a) Stressed @ 27°C, 2.4V, 1.54GHz(b) Natural recovery @ 27°C, 0V(c) Annealing @ 110°C, 0V(d) Annealing @ 240°C, 0V
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Open-Loop Results: Frequency
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(a) Stressed @ 27°C, 2.4V, 1.54GHz(b) Natural recovery @ 27°C, 0V(c) Annealing @ 110°C, 0V(d) Annealing @ 240°C, 0V
• Stress BTI, HCI frequency degradation
• Natural recovery and annealing
• Cool down the chip after annealing remove anyresidual heat
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Open-Loop Results: Phase Window
• Phase window @ error rate = 1E-8
• More degradation larger phase window
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• Feedback loop ensures that output frequency is constant
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DCO Frequency Degradation (%)(open loop)
PL
L F
req
ue
nc
y
(MH
z,
clo
se
d l
oo
p)
65nm, 1.2V, 27°C
Closed-Loop Results: Frequency
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Closed-Loop Results: Phase Window
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• Error rate curves all centered around same frequency due to feedback loop
• Longer stress larger phase window
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• Phase window almost fully recovered after annealing
@ 240°°°°C
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Phase Window Recovery
Closed-loopOpen-loop
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Outline
• Motivation
• Proposed on-chip monitors
• 65nm ADPLL chip test setup
• Stress, recovery, annealing results
• Conclusions
![Page 26: All-Digital PLL Frequency and Phase Noise Degradation ...people.ece.umn.edu/groups/VLSIresearch/papers/2018/IRPS18_ADPLL_slides.pdf · Beat Frequency Monitor 8 “Silicon Odometer”,](https://reader035.vdocuments.mx/reader035/viewer/2022070703/5e7c1f1f61002008920c1427/html5/thumbnails/26.jpg)
Conclusions
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• ADPLL frequency and phase noisecharacterized for the first time using on-chipmonitors
• Phase noise increases with stress for bothopen-loop and closed-loop configurations
• High temperature annealing can be used torecover most of the degradation
• Post-stress phase noise measurementscritical for reliability assurance