A Class D Audio Amplifier as an Application for Silicon Carbide SwitchesVerena Grifone Fuchs, Carsten Wegner, Sebastian Neuser, Dietmar Ehrhardt University of Siegen, IMT, Hoelderlinstraße 3, D-57068 Siegen, Germany Email: verena.grifone@uni-siegen.de

Abstract

Class D amplifiers emend the energy efficiency and the size to power ratio of audio amplifiers. Lower gate charge combined with high breakdown voltages and good reverse recovery characteristics bring out high potential for SiC-devices in class D audio amplification. Two prototypes of a PWM-driven class D power stages have been developed. For the half bridge topology, SiC MOSFETs from Cree and superjunction transistors from Infineon (CoolMOS) are used. Comparing the turn-off behaviour, a remarkable lower fall time (1.9x) and improved switching waveforms were investigated for the SiC device. Relating to this, the blanking time for switching the SiC half bridge could be reduced by two. Shorter blanking times significantly emend the audio signal of the amplifier due to less PWM-timing errors and improved THD (Total Harmonic Distortion). The measured fall time matched well with the calculation.

1. Introduction and Motivation

1.1. Class D Audio Principle

In contrast to a linear amplifier (class A, class B, class AB), a class D audio amplifier oper-ates in switch-mode. In a linear amplifier the power transistors work as linear regulators that control the output voltage with respect to the input signal. A class D amplifier is driven by a pulse modulation of the input signal (e.g. PWM or PDM), using the transistors as switches. The topology comprises a comparator, a switching power stage and a LC-low-pass filter as shown in Fig. 1. The PWM driving signal derives from the comparison of the audio signal (max. 20kHz) with a higher frequent carrier (see Fig. 2.). Typically configured as half bridge or full bridge, the power stage switches with a frequency between 200kHz-400kHz. The amp-lified PWM-signal is demodulated by a 2nd-order low-pass filter that also attenuates the switching frequency. Hence, the speaker is driven by an amplified, analog signal.

Fig. 1. Block diagram of a class D amplifier. The analog audio signal is converted into a PWM signal by the comparator and amplified by the power stage. Demodulated by 2nd order low pass filter, an analog signal drives the speaker speaker.

Depending on the application, power capabilities vary from a few milliwatts for headphones or mp3-players, to tens of watts for home stereos or automotive audio, to a few kilowatts for public addressed systems (professional power amplifiers) in theaters and stadiums. Using the transistors as a switch instead of a linear regulator, power loss in the output device is sig-nificantly reduced. Hence, a system efficiency of 85%-95% is possible [1].

1.2. Drawbacks and Design Challenges

The aim of a class D amplifier is an appropriate reconstruction of the audio input with minimal Total Harmonic Distortion (THD) of the audio signal, lowest noise and highest efficiency. The drawback of the switch-mode operation are non-linearities and distortion that increase the complexity of designing an accurate class D amplifier.

The most challenging task is the proper conversion of the audio input into a PWM signal. This conversion causes non-linearities and distortion, that will not be found in an linear ampli-fier. In every sampling period, the average value of the PWM signal must exactly equal the current audio input. The average value of the PWM is determined by the voltage-time-integral over one period. Any errors of this integral lead to a wrong average value. Accordingly, the audio input is demodulated incorrectly. A false modulation results in distortion and noise (THD+N) on the output signal. The voltage-time-integral is affected by both amplitude and timing errors of the PWM. Amplitude errors occur due to variation of the power supply. Since the voltage supply is directly connected to the power stage, any inaccuracy will affect the PWM average. Timing errors are generated by two major sources: blanking times, where both transistors are turned off, and the delay of the voltage transition. A blanking time (dead time) has to be introduced after each switching event to avoid cross conduction in the power stage. The transition delay emerge from the finite rise and fall times of the gate driver and the power device. Minimizing amplitude and timing errors will improve distortion and noise (THD+N) significantly. A close look has to be payed on this issue – otherwise the quality of the audio signal will not be comparable to a linear amplifier. [1]

Switching and conduction losses should be reduced to op-timize efficiency, costs and case size. Reduced losses will need less cooling that contributes to the system costs. A higher efficiency offers more output power, as the power of the typical mains supply used for audio amplifiers is limited. Apart from case size and cooling, weight is an important topic to the power amplifiers installed at major events (e.g. open air festivals, soccer arena, major concerts). Improving efficiency and cooling, weight can also be reduced.

Fig. 2. Generation of the PWM driving signal by comparing the analog input with a high-frequency carrier.

1.3. Silicon Carbide and Class D Audio

The physical and electronic properties of silicon carbide (like a high electrical breakdown field, wider band gap, higher thermal conductivity and higher saturated electron drift velocity) offer several advantages for the switching device compared to conventional silicon devices that are well known from [2]. For class D audio, device properties that result in faster switch-ing transitions and shorter dead time are of great interest. Furthermore, a higher switching frequency, reduced switching and conduction losses as well as less cooling are aimed for. Hence, the benefit of silicon carbide will be found in device characteristics like higher temper-ature capability and enhanced breakdown voltage with low on-resistance. Particularly with re-gard to the timing errors, the reduced gate charge and lower reverse recovery charge of the body diode is advantageous.

2. Power Stage Prototype Characterisation

In a first approach of analyzing the benefit of silicon carbide for class D audio, switching waveforms were compared to gain information about the switching speed of the SiC device. Therefor two almost identical prototypes of a class D power stage have been developed, one comprising silicon carbide MOSFETs, one with state-of-the-art silicon MOSFETs. The topo-logy of the power stage prototype is a half bridge configuration, according to Fig. 1. The max-imum supply voltage for the power stage is 230V. Considering a half bridge configuration with ±230V, the transistors need a maximum breakdown voltage of 600V. As 600V SiC-devices are not available, we use a 1200V device with the following parameters:

CREE „Z-FET“ CMF20120D - Silicon Carbide MOSFET

ID,cont. = 33A@25°C / 17A@100°C, RDS(on) = 80mOhm, QG = 90nC, VBd(DSS) = 1200V

Making the devices comparable, the silicon one is chosen by its drain current. A 1200V tran-sistor is not practicable for an audio amplifier, since its high on-resistance and the slow switching ability would introduce too much loss. Hence, a state-of-the-art superjunction MOS-FET was chosen from CoolMOS CFD series. The CFD-series is a CoolMOS technology sim-ilar to the C6/E6-series, but provided with a fast body diode.

INFINEON „CoolMOS“ IPW65R080CFD - Superjunction MOSFET

ID,cont. = 43A@25°C / 27A@100°C, RDS(on) = 80mOhm, QG = 170nC, VBd(DSS) = 650V

The power stage prototypes are characterized both theoretically and practically with respect to the turn-off behavior.

2.1. Theoretical View on the Turn-off Event

In this section, the turn-off event is discussed and analyzed in detail. Relating to this analys-is, the fall time for both devices is estimated under the given conditions. All considerations will be made for a maximum duty cycle that is investigated in the measurement.

ZVS - Zero Voltage Switching

At maximum duty cycle, the voltage transition of the bridge voltage is determined only by the high-side transistor. The high-side device conducts for 80% of the switching cycle and the current flows from the bridge to the load. During the off-time of the high-side, the load current is on its positive maximum and will not become zero or change direction. When both transist-ors are switched off (dead time), the current commutates into the body diode of the low-side due to the inductor of the low-pass filter. The output voltage drops before the low-side device is turned on. After the dead time, the low-side transistor is switched on and the current shifts from the body diode into the channel. As the device is already conducting there is only a small voltage over the drain-source channel, when switching it. Hence, this process is called zero voltage switching (ZVS). Turning off the low-side, the current shifts back into the diode. The output voltage is affected by the forward voltage of the diode but it will not rise until the high-side FET is turned on again. Hence, at maximum duty cycle, both voltage transitions are controlled by the high-side switch.

Analysis of the Turn-off Event

The turn-off event of the high side switch is analyzed for a positive load current. For a basic understanding, the assumption of an idealized switching characteristic is adequate. Accord-ingly, the following simplifications are made. All voltage and current transitions are assumed to be linear. Reverse recovery effects of the body diode, ripple current and all other parasitic effects will not be considered. The supply voltage Vs and the output current IL are assumed to be constant. Fig. 3. shows the corresponding waveforms of Vgs, IL and Vs for the high-side switch. Low-side waveforms are not displayed to simplify matters. The turn-off event is di-vided into the following section: initiation (t1), delay time (t1-t2), fall time (t2-t3), commutation time (t3-t4), residual discharge (t4-t5).

Initiation

When the turn-off event is initiated by a low level of the gate driver at t1 (driver delays are neglected). The bridge voltage Vbrd equals1 the supply voltage Vs and the input capacitance is charged to the gate driver voltage. Since the FET is fully conducting, the drain-source capa-citance Cds is shorted and the input capacitance is a parallel connection of the gate-source capacitance Cgs and the gate-drain capacitance Cgd.

Delay Time

The delay time is the delay from the start of the gate-source voltage drop at Vgs(t1) to the be-ginning of the bridge voltage drop at Vbrdg(t2). During this time the input capacitance is dis-charged to a specific value. Due to the parallel connection, Cgs and Cgd are discharged to the same value of Vgs by the gate driver. The gate-source voltage Vgs drops, while the bridge voltage Vbrdg, remains constant (see Fig. 3.) - As long as the transistor is fully conducting, Vbrd

equals VS and will not alter. For both capacitance the final discharging value of Vgs calculates

to VGS ,mill

=VGS , th

+ Iload

/gfs

(miller plateau). At the end of the delay time, the miller plateau

VGS,mill is reached and the transition of Vbrdg will start.

Fall Time

The fall time describes the time needed for the voltage transition of the bridge voltage (t2 – t3). During this time the output capacitance of the FET is charged. The output capacitance con-sists of the gate-drain capacitance Cgd and the drain-source capacitance Cds. As the capacit-ances are charged, the increasing drain-source voltage Vds pushes the bridge voltage Vbrdg

towards -Vs. While the Vbrdg falls (and Vds

rises), the gate-source voltage remains con-stant2 (miller plateau). The gate current ex-clusively charges Cgd, so Vgs is trapped and cannot further discharge. Idealized, the drain current remains constant until the voltage transition is finished at ID(t3). But in praxis, Id

slightly decreases, according to the transcon-ductance. A high transconductance of a device indicates that, small variations in Vgs

will imply great variations in the drain current. Since Vgs decreased during the delay time, the drain current is slightly reduced. Thus, the drain current becomes smaller while the load current is kept constant by the inductor. The arising difference will charge the drain-source capacitance Cds. At the end of the fall time (t3), the all capacitance are fully charged. The bridge voltage has reached its low-value (-Vs) and the current commutation will initiate.

Fig. 3. Switching transitions of voltage and cur-rent at turn-off.

Commutation Time

During the commutation time the load current commutates from the high-side transistor into the body diode of the low-side FET (t3 – t4). Now, (as Cgd is fully charged) the discharging of Cgs continues and Vgs starts falling again (t3). The decreasing gate-source voltage reduces

1 The conducting voltage, determined by the on-resistance of the transistor, is neglected.

2 The idealised miller plateau is constant, whereas the actual plateau has a descending slope.

the depth of the inversion layer. Hence, the conducting channel depletes and the drain cur-rent starts to fall. Less current will be able to run through the FET, so the current shifts into the body diode of the low side. At the end of the commutation time (t4), the complete current is running through the diode. The high-side FET is turned off, since VGS,th is reached.

Residual discharge

In the last section, the residual charge of the gate is depleted (t4 – t5). The gate-source voltage falls from VGS,th to zero and the entire inversion layer is completely decreased. The conduct-ing channel between source and drain disappears and the turn-off procedure is completed.

Now, the ZVS of the low-side transistor can be initiated by the gate driver.

Calculation of the Fall Time

The turn-off behavior for both MOSFETS is studied under a load of 4Ω and a gate resistance of RG,off(SiC) = 8.4Ω for the SiC device and RG,off(SJ) = 3.1Ω for the superjunction device (see section 2.2). The expected fall time of the bridge voltage is pre-estimated using equation (1) derived in [3]. This equation is based on the previous simplifications. A precise theoretical treatment needs to consider the non-linear transitions, generated by the parasitic capacit-ances. An idealized switching characteristic, where the bridge voltage has a linear transition, is assumed (Fig. 3.). The fall time is calculated as ratio of the miller charge Qgd and the cur-

rent at turn-off: tfall ˜

=Qgd/ IG ,off

. The turn-off current IG,off is derived from the miller plateau,

VGS ,mill

=VGS , th

+ Iload

/gfs

divided by the gate resistance RG,off.

(1)

The gate-drain charge Qgd is determined by the difference of the of QG at the beginning to the end of the miller plateau in the curve of typical gate charge characteristics in the data sheet. The gate-source voltage of the miller plateau is taken from the transfer characteristics in the data sheet. Relating to a load current of Iload=9A, a miller plateau of VGS,mill=8.5V for the Z-FET and VGS,mill=5.5V for the CoolMOS is found. The Z-FET is turned-off by a negative voltage of -4V as explained in section 2.2. Adding this voltage to VGS,mill of the Z-FET, the fall time for the Cree Z-FET tfall~(SiC) and the Infineon CoolMOS tfall~(SJ) are evaluated:

tfall ˜ (SiC)=

40nC

8.5V+4V8.4Ω

=27ns and

tfall ˜ (SJ )=

100nC

5.5V

3.1Ω

=56ns.

The ratio of the fall times calculates to tfall~(SJ)/tfall~(SiC) = 2.1.

2.2. Prototype Setup

The power stage prototype consists of several on-board voltage generations, bootstrap capa-citors, snubber- and gate drive circuits, a half bridge and a 2nd-order low pass filter. The half- bridge operates at a switching frequency of fsw = 400kHz, currently supplied by ±50V. A low-pass filter demodulates the PWM-signal from the half-bridge with L=18µH and C=1.5µF. Un-desired components above the audio band (including the switching frequency) are attenu-ated with a cut-off frequency of fco=30.5kHz. Related to this frequency, the impedances of the low pass filter is ZLC = 3.4Ω.

tfall ˜

=Qgd

VGS , th

+Iload

gfs

RG ,off

The speaker is replaced by a resistive load of 4Ω with respect to a common value for an au-dio amplifier. Instead of an audio signal, an 1kHz sine from an analog signal generator is used. A DSP from the “piccolo” series of Texas Instruments converts the input signal into a PWM driving signal. Two individual, synchronized signals are provided for the high-side and low-side gate driver input. The floating voltage for the gate driver circuit is generated directly on board of our PCB using a DC-DC converter and a full bridge rectifier.

Driving Infineon´s CoolMOS a gate signal of 0V to 12V is recommended in [5]. Compared to the superjunction transistor, the SiC-MOSFET has a low transconductance. This implies that changes of the drain current due to variations of Vgs will be smaller for the SiC device, as seen in the transfer characteristic. With respect to the output characteristics, the transition from the active region to the saturation region requires a larger interval over VDS compared to a conventional MOSFET. According to [4], the nominal threshold voltage is 2.5V, but the device is not fully on until VGS exceeds 16V. Hence, the device requires a positive voltage of 20V to turn on and a negative voltage of -4V for turning off.

Both transistors should be provided with the same maximum gate current for the turn-off event. Taking the gate-source voltage of the miller plateau and the gate resistance for the Z-FET from section 2.1., p.5, the turn-off current IG,off calculates to 1.48A:

IG ,off

=VGS ,mill

RG ,off

=8.5V+4V8.4Ω

=1.48A .

Again, the negative turn-off voltage of -4V has to be considered. The gate resistance of the Z-FET RG,off = 8.4Ω implies both the internal and the ex-ternal gate resistance recommended in the data sheet. (Total resistance for turn-on: RG,on(SiC) = 11.8Ω). With the given gate current IG,off, the total turn-off resistance for the CoolMOS calculates to RG,off(SJ) = 3.1Ω. (Total gate resistance for turn-on: RG,on(SJ) = 5.5Ω).

Apart from the gate resistance and the gate driv-ing voltage, circuit and layout of both prototypes are exactly the same.

Fig. 4. Power stage prototype of a class D amplifier with SiC MOSFETs from Cree.

2.3. Analysis of the Switching Performance

The fall time is measured with an output voltage of Vout,peak=36V and a load current of Iout,peak=9A corresponding to the output resistance of 4Ω. The duty cycle of the PWM varies from 14% to 86% and the supply voltage is Vsupl,=±50V. For safe operation, a blanking time of 100ns was chosen for the SiC power stage. The dead time for the superjunction FETs had to be increased to 200ns, to avoid cross-conduction.

The results of the measurements are shown in Fig. 5. Setting the trigger on the positive peak of the sine, the turn-off behavior is observed at maximum duty cycle. For both prototypes the gate signal of the high side and and low side (VGS,HS, VGS,LS) and the bridge voltage (Vbrdg) are displayed. Markers show the delay time (tdly) and the fall time of the bridge voltage (tfall) with respect to the theoretical analysis in section 2.1., p.4.

Fig. 5. Switching behavior at maximum duty cycle. Left: CoolMOS (SJ); Right: Cree Z-FET (SiC)

Ringing

The CoolMOS shows remarkable ringing at turn-on. Ringing is observed at every voltage transition due to hard switching on the output capacitance of the FETs, the parasitic circuit capacitance of the PCB (6x-multi-layer), the snubber capacitance and the inductor of the low-pass filter. Optimizing the snubber circuit work is still in progress but the reverse recovery process has also a contribution to the ringing [6]. The body diode of the CoolMOS behaves snappier than the Z-FET diode and the reverse recovery charge is 7 times higher [5],[7]. As already mentioned, the body diode of the low-side FET is conducting, when the high-side FET is switched on (see ZVS, section 2.1., p.3). Turning off the diode, the reverse recovery charge Qrr,SiC is discharged by the reverse recovery current Irr. In the data sheet, reverse re-covery charges are given with Qrr,SJ=1000nC and Qrr,SiC=142nC. Therefore, no significant ringing occurs turning on the Z-FET and the bridge voltage is much more accurate. At turn-off, reverse recovery effects have no contribution to ringing, as the body diode of the high side did not conduct before.

Delay Time and Fall Time

Defining the fall time from 90%-10% of the bridge voltage, the following results are found:

SiC Z-FET → delay time : tdly(SiC) = 30ns, fall time : tfall(SiC) = 45ns.

CoolMOS → delay time : tdly(SJ) = 115ns, fall time : tfall(SJ) = 86ns.

The CoolMOS requires almost twice the time for the voltage transition - the fall time is exten-ded by factor 1.9. The delay time of the power stage with SiC devices is just under 4 times (3.8x ) shorter. As mentioned in the theoretical analysis, discharging the input capacitance delays the voltage transition. Referring to the data sheet, the input capacitances are Ciss,SiC = 1915pF and Ciss,SJ = 5030pF. The ratio is only factor 2.6 but in the data sheet C iss is given for Vgs =0V, when the transistor is completely turned off. When Vgs > 0 and the FET is still con-ducting, the gate-drain capacitance Cgd has a major contribution to the input capacitance. While the gate-source charge is approximately the same (Qgs,SiC = 23.8nC and Qgs,SJ = 25nC), the gate-drain charge of the CoolMOS is almost 3 times higher (Qgd,SiC = 43.1nC and Qgd,SJ = 120nC). Due to the parallel connection of Cgs and Cgd , the ratio of Ciss for Vgs > 0 is influenced by Cgd. In the data sheet the gate-drain capacitance Cgd is found as reverse transfer capacit-ance Crss. A positive charge of Crss is defined with a positive voltage from drain to source. When the transistor is conducting, the voltage from drain to gate is negative. Negative voltage values of Crss are usually not displayed in the curves. According to the extrapolation of the Crss-curve in the data sheet, a value of Crss = 2000pF is reasonable. The ratio calcu-lates to 7030pF/1915pF = 3.6 corresponding to the ratio of the delay times.

The gate signal of the SiC device rises and falls a lot quicker, passing only a marginal miller plateau. Hence, the minimum off-time for the SiC device is smaller allowing higher duty cycle variations for the same switching frequency. As seen from Fig. 5., the possible duty cycle

variation for the Z-FET is is higher. For a rising gate signal of the CoolMOS the minimum off-time has to be increased.

During the experiments it was noticed that the heat sink of the SiC power stage heated up less. Tested under the same conditions of supply voltage and load current, the SiC power stage is more efficient. Due to faster switching transitions the SiC transistors develop less switching loss and therefore less heat. A detailed examination concerning switching loss and system efficiency is part of the ongoing work.

Idealized Fall Time from Calculation

An idealized fall time is derived from the measured curves in accordance with the theoretical analysis. Fig. 6. displays the asymptotes fitted in the bridge voltage trans-ition of the SiC power stage corresponding to the as-sumption in the calculation. The idealized fall time is de-termined by the intersection point of the asymptotes, finding following results:

SiC Z-FET: tfall˜(SJ) = 72ns,

CoolMOS: tfall˜(SiC) = 34ns.

The measured fall time for both transistors match very well with the calculation. The ratio of the practical derived fall time (2.1) equals the theoretically derived ratio (2.1).

Fig. 6. Asymptotes for the idealized fall time.

3. Conclusion & Prospects

Analyzing the turn-off behavior of a power stage prototyp, it is found that SiC transistors bring out high potential for class D audio amplifiers. The theoretical derivation and measurement of the fall time showed an improvement for the half bridge topology. Already in the first ap-proach the dead time for safe switching could be reduced by a factor of two. Shorter blanking times significantly enhance the quality of the audio signal, emending PWM-timing errors and THD (toral harmonic distortion). A detailed analyzis of the emendation in PWM timing errors and the improvement of THD is part of the ongoing work. Both bridge voltage and gate si-gnals show major improvements concerning the waveform (see Fig. 5.). A remarkable lower delay time (3.8x) and half the fall time (1.9x) was investigated for the SiC power stage. It was noticed that the heat sink of the SiC power stage heated up less due to reduced switching loss. Studying the switching losses and their effect on the system efficiency in detail, we will confirm the benefit of SiC transistors for class D audio amplification.

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versity of Denmark (DTU), Ph.D. Thesis, April 1998.[4] Cree Inc., „Z-FET Datasheet of CMF20120D “ Rev. A, 2011.[5] Infineon, „CoolMOS Datasheet of IPW65R080CFD“ Rev. 2.0, 2011.[6] B. Lu, “Performance Evaluation of CoolMOS and SiC Diode for Single-Phase Power Factor Cor-

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