8085 internal structure
TRANSCRIPT
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8051 AND ADVANCED PROCESSOR
ARCHITECTURES
Lesson-10: Processor organization
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1.1. The Structural Units in a Processor:The Structural Units in a Processor:
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Organisation of various structural units of processor
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BusesBuses1) Internal and external buses
interconnect the processorinternal units with the external
system memories, I/O devicesand all other system elements
2) Address, data and control buses
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MDR, MAR, BIU , PC and SPMDR, MAR, BIU , PC and SP
3) MDR (memory data register) holds tMDR,
MAR, BIU, PC and SP A andhe accessedbyte or word
4) MAR (memory address register) holds the
address5) BIU (Bus Interface Unit)
6) Program Counter or Instruction Pointer
and7) Stack Pointer
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RegistersRegisters
8) ARS (Application Register Set): Set ofon-chip registers for use in the
application program. Register set
alsocalled file and associates an ALU or FLPU.
9) Register window- a subset of registerswith each subset storing static variablesand status words of a task or program
thread. Changing windows help in fastcontext-switching in a program.
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10) ALU and FLPU (Arithmetic and
Logic operations Unit and FloatingPoints operations Unit). FLPU
associates a FLP register set foroperations.
ALU, FLPUALU, FLPU
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12) Instruction, Data and Branch Target Cachesand associated PFCU (Prefetch control unit)
for pre-fetching the instructions, data andnext branch target instructions, respectively.
Multi-way Cache Example- 16 kB, 32-way
Instruction cache with 32 byte block for dataand 16 kB in ARM
Cache block Enables simultaneous caching of
several memory locations of a set of
instructions
CachesCaches
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AOUAOU13) AOU (Atomic Operations Unit ) An
instruction is broken into number of
processor-instructions called atomicoperations (AOs), AOU finishes theAOs before an interrupt of the
process occurs - Prevents problemsarising out of incomplete processor-operations on the shared data in the
programs
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Features in most processorsFeatures in most processors
Fixed Instruction Cycle TimeRISC
processor core 32-bit Internal Bus Width to facilitate the
availability of arithmetic operations on 32-
bit operands in a single cycle. The 32-bitbus a necessity for signal processing and
control system instructions.
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Features in most processorFeatures in most processor
Program-Counter (PC) bits and its
reset value
Stack-Pointer bits with and its initial
reset value
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Instruction, Branch Target and Data Cache
Memory-Management unit (MMU)
Floating Point Processing unit
System Register Set
Features in advanced architecturesFeatures in advanced architectures
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Floating Point Register Set
Pre-fetch Control Unit for data into the I-
and D-caches
Instruction level parallelism units (i)
multistage pipeline (ii) Multi-line
superscalar processing
Features in advanced architecturesFeatures in advanced architectures
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Executing most instructions on in a single
clock cycle execution per instruction (by
hardwired implementation of instructions)
Using multiple register-sets or register-
windows or files and
Greatly reducing ALU dependency on the
external memory accesses for data due to thereduced number of addressing modes
provided for the ALU instructions.
RISC architectureRISC architecture
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Before ALU operations, the operands are
loaded into the registers and similarlythe write back result is in the register and
then stored at the external memory
addresses
RISC Load and store architectureRISC Load and store architecture
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55-- stage pipelinestage pipeline
Fetch
Decode
Execute
Write
back
Read
Operands
Successive Clock Intervals
I1 I2 I3 I4 I5 I6
I1 I2 I3 I4 I5
I1 I2 I3 I4
I1 I2 I3
I1 I2
Stages
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CyclesCycles
On cycle 1, the first instructionI0 enters theinstruction fetch (IF) stage of the pipeline andstops at pipeline latch (buffer) between instruction
fetch and instruction decode (ID) stage of thepipeline.
On cycle 2, the second instructionI1 enters theinstruction fetch stage, while instructionI
proceeds to instruction decode stage.
On cycle 3 the instructionI2 enters the register(inputs) read (RR) stage, instructionI1 is in the
instruction decode stage, and instructionI2 entersinstruction fetch stage.
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CyclesCycles
Instructions proceed through the pipeline at onestage per cycle until they reach the register (result)write-back (WB) stage, at which point execution ofthe instructionI0 is complete.
On cycle 6 in the example, instructionsI1 throughI5are in the pipeline, while instructionI0 hascompleted and is no longer in the pipeline.
The pipelined processor is still executinginstructions at a rate (throughput) of one instructionper cycle, but the latency of each instruction is now5 cycles instead of 1. But each cycle period is now
1/5 or less compared to the case without pipelining.Thus processing performance can improve or moretimes in five stage pipeline .
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Super scalingSuper scaling
Fetch
Decode
Execute
Write
back
Read
Operands
Pipeline1
I5
I4
I1
I3
I2
Stages Pipeline 2
I5
I4
I1
I3
I2
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SummarySummary
We learnt
Structural units in a processor to enableselection of appropriate processor for
an embedded System
Caches, Register set(s), buses
RISC architecture features
MMU, Floating Point Processing
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End of Lesson 10 of Chapter 2End of Lesson 10 of Chapter 2