8 memory management strategies

Memory Management Strategies

Background

SwappingSwapping

Contiguous Memory Allocation

Paging

Structure of the Page Table

Segmentation

1. Background1.1 Basic Hardware

• Main memory and registersare only storage CPU canaccess directly

• Register access in one CPUclock, but, main memory cantake many cyclestake many cycles

• Cache sits between mainmemory and CPU registers

• Protection of memory requiredto ensure correct operation

• A pair of base and limitregisters define the logicaladdress space

2Loganathan R, CSE, HKBKCE

1. Background Contd…

• CPU hardware compares every address generated in user mode with theregisters

• A program executing in user mode attempt to access OS memory or otherusers' memory results in a trap to the OS, which treats the attempt as a fatalerror

• This prevents a user program from accidentally or deliberately modifying thecode or data structures of either the OS or other users.

base base + limit


CPU

yes yesaddress

≥ <No No

Memory

Trap to OS monitor–addressing error

Hardware Address Protection with base and limit registers

1.2 Address Binding• A user program will go through several

steps, before being executed as shown• Address binding of instructions and data

to memory addresses can happen atthree different stages– Compile time: If memory location known

a priori, absolute code can be generated;must recompile code if starting locationchanges Eg. DOS .com Programs


changes Eg. DOS .com Programs– Load time: Must generate relocatable

code if memory location is not known atcompile time

– Execution time: Binding delayed until runtime if the process can be moved duringits execution from one memory segmentto another. Need hardware support foraddress maps (e.g., base and limitregisters)


1.3 Logical vs. Physical Address Space• Logical address – generated by the CPU, also referred as virtual address• Physical address – address seen by the memory unit i.e loaded to memory-address

register

• Logical and physical addresses are the same in compile-time and load-timeaddress-binding schemes; logical (virtual) and physical addresses differ inexecution-time address-binding scheme

• The run-time mapping from virtual to physical addresses is done by ahardware device called the memory-management unit (MMU)


• In MMU, the value inDynamic relocation using a relocation


• In MMU, the value inthe relocation register isadded to every addressgenerated by a userprocess at the time it issent to memory

• The user program dealswith logical addresses; itnever sees the realphysical addresses

Dynamic relocation using a relocationregister

1.4 Dynamic Loading• All routines are kept on disk in a relocatable load format and main program is

loaded into memory and is executed• Routine is not loaded until it is called• The relocatable linking loader is called to load the desired routine• Better memory-space utilization since unused routine is never loaded• Useful when large amounts of code are needed to handle infrequently

occurring cases• No special support from the operating system is required implemented


No special support from the operating system is required implementedthrough program design

1.5 Dynamic Linking and Shared Libraries• Linking postponed until execution time• Small piece of code, stub, used to locate the appropriate memory-resident

library routine• Stub replaces itself with the address of the routine, and executes the routine• Operating system needed to check if routine is in processes’ memory address• Dynamic linking is particularly useful for libraries• System also known as shared libraries


2. Swapping• A process can be swapped temporarily out of memory to a backing store,

and then brought back into memory for continued execution• Similar to round-robin CPU-scheduling algorithm , when a quantum expires,

the memory manager will swap out that process to swap another processinto the memory space that has been freed .


Swapping of twoprocesses using adisk as a backingstore.

• Backing store – fast disk large enough to accommodate copies of all memoryimages for all users and provide direct access to these memory images

• Roll out, roll in – swapping variant used for priority-based schedulingalgorithms; lower-priority process is swapped out so higher-priority processcan be loaded and executed

• The swapped out process will be swapped back into the same memory spaceit occupied previously due to the restriction by the method of addressbinding(assembly or load time)

• A process can be swapped into a different memory space If execution-timebinding is used since physical addresses are computed during execution time

• System maintains a ready queue of ready-to-run processes which havememory images on disk

2. Swapping Contd…


• System maintains a ready queue of ready-to-run processes which havememory images on disk

• The dispatcher swaps out a process in memory if there is no free memoryregion and swaps in the desired process from a ready queue

• Major part of swap time is transfer time; total transfer time is directlyproportional to the amount of memory swapped

• Example : User process is 10 MBBacking store is a hard disk with a transfer rate of 40 MB per secTransfer time = 10/40 MB per sec. = 250 millisecondsSwap time = transfer time+ Seek time(latency 8 millisec)= 258 millisec.Total swap time = swap out + swap in = 516 milliseconds

• Modified versions of swapping are found on many systems (i.e., UNIX, Linux,and Windows)

3. Contiguous Memory Allocation• Main memory usually into two partitions:

– Resident operating system, usually held in low memory with interrupt vector– User processes then held in high memory

3.1 Memory Mapping and Protection• Relocation registers used to protect user processes from each other, and from changing

operating-system code and data– Base register contains value of smallest physical address– Limit register contains range of logical addresses – each logical address must be less

than the limit register• MMU maps logical address dynamically by adding the relocation register• MMU maps logical address dynamically by adding the relocation register


Hardware support forrelocation and limitregisters

3.2 Memory Allocation• Memory is to divide memory into several fixed-sized partitions, when a partition is free,

a process is loaded into the free partition and when it terminates, the partitionbecomes available for another process

• Multiple-partition allocation (generalization of the fixed-partition)– Hole – block of available memory; holes of various size are scattered throughout memory

– OS maintains information about the allocated partitions and free partitions (hole)– When a process arrives, it is allocated memory from a hole large enough to accommodate it

– If the hole is too large, it is split into two parts., One part is allocated to the arrivingprocess; the other is returned to the set of holes

– If the new hole is adjacent to other holes, the adjacent holes are merged to form one larger hole

3. Contiguous Memory Allocation Contd…

– If the new hole is adjacent to other holes, the adjacent holes are merged to form one larger hole

• Dynamic storage allocation problem, which concerns how to satisfy a request of size nfrom a list of free holes and the solutions are:

• First-fit: Allocate the first hole that is big enough , Search from beginning or where theprevious first-fit search ended

• Best-fit: Allocate the smallest hole that is big enough, must search entire list, unlessordered by size, produces the smallest leftover hole

• Worst-fit: Allocate the largest hole; must also search entire list, produces the largestleftover holeFirst-fit and best-fit better than worst-fit in terms of speed and storage utilization


3.3 Fragmentation• External Fragmentation – total memory space exists to satisfy a

request, but it is not contiguous, i.e. storage is fragmented into a largenumber of small holes

• Internal Fragmentation – allocated memory may be slightly larger thanrequested memory; this size difference is memory internal to apartition, but not being used

• Reduce external fragmentation by

3. Contiguous Memory Allocation Contd…

• Reduce external fragmentation by1 Compaction– Shuffle memory contents to place all free memory together in one

large block– Compaction is possible only if relocation is dynamic, and is done at

execution time2 Permit the logical address space of the processes to be

noncontiguous, thus allowing a process to be allocated physicalmemory wherever available


4. Paging• Permits the physical address space of a process to be noncontiguous4.1 Basic Method• Divide physical memory into fixed-sized blocks called frames (size is power of 2)• Divide logical memory into blocks of same size called pages• The backing store is divided into fixed-sized blocks of size of frames• Hardware support for paging i.e. a page table to translate logical to physical addresses


• Address generated by CPU is divided into:

Page number (p) – used as an index into a page table which contains baseaddress of each page in physical memory

Page offset (d) – combined with base address to define the physical memoryaddress that is sent to the memory unit

4. Paging Contd…

• For given logical address space2m and page size 2n then m – nbits of a logical addressdesignate the page number,


Paging Model of Logicaland Physical Memory

page number page offset

p d

m - n n

designate the page number,and the n low-order bitsdesignate the page offset as :

where p is an index into thepage table and d is thedisplacement within the page

4. Paging Contd…

Paging example for a 32-byte(25)memory with logical address of 16 byte(24) and 4-byte(22) pages i.e. m=4 & n=2

For logical address 0 is page 0, offset 0Indexing into the page table, find thatpage 0 is in frame 5

Logical address 0 maps to physicaladdress = 5(frame number) x 4(page

32-byte memory and 4-byte pages14Loganathan R, CSE, HKBKCE

size) + 0(offset) = 20

Logical address 3 (page 0, offset 3)maps to physical address = 5x4 + 3 = 23

Logical address 13(page 3, offset 1)indexing to page 3 find frame number 2which maps to physical address = 2x4+ 1 = 9

4. Paging Contd…

In paging no external fragmentation: Any free frame can be allocated to a processthat needs it, but, may have some internal fragmentation i.e. last frame allocatedmay not be completely fullIf the process requires n pages, If n frames are available, they are allocatedThe first page of theprocess is loaded into oneof the allocated frames,and the frame number isput in the page table forthis process.

Before allocation After allocation15Loganathan R, CSE, HKBKCE

this process.The next page is loadedinto another frame, and itsframe number is put intothe page table and so onOS keeps tracks of whichframes are allocated,which frames areavailable, how many totalframes are there, and soon in a frame table

4.2 Hardware Support• Hardware implementation of Page Table is a set of high speed dedicated

Registers• Page table is kept in main memory and• Page-table base register (PTBR) points to the page table• Page-table length register (PTLR) indicates size of the page table• The CPU dispatcher reloads these registers, instructions to load or modify the

page-table registers are privileged• In this scheme every data/instruction access requires two memory accesses.

4. Paging Contd…

• In this scheme every data/instruction access requires two memory accesses.One for the page table and one for the data/instruction.

• The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-asidebuffers (TLBs)

• TLB entry consists a key (or tag) and a value, when it is presented with an item,the item is compared with all keys simultaneously


Page # Frame #

4. Paging Contd…

• When page number from CPU address is presented to the TLB, if the pagenumber is found, its frame number is immediately available and is used toaccess memory.

• If the page number is not in the TLB (known as a TLB miss), a memoryreference to the page table must be made, also the page number and framenumber to the TLB.

• If the TLB is full, theOS select one entryfor replacement.

• Replacement


Paging Hardware With TLB

• Replacementpolicies range fromLRU to random

• TLBs allow entries(for kernel code) tobe wired down, sothat they cannot beremoved from theTLB.

4. Paging Contd…

• Some TLBs store address-space identifiers (ASIDs) in each TLBentry which identifies each process and is used to provide address-space protection for that process

• TLB must be flushed (or erased) to ensure that the next executingprocess does not use the wrong translation information

• The percentage of times that a particular page number is found inthe TLB is called the hit ratio

4.3 Protection• Memory protection implemented by associating protection bit


• Memory protection implemented by associating protection bitwith each frame, Valid-invalid bit attached to each entry in thepage table:

–“valid” indicates that the associated page is in the process’slogical address space, and is thus a legal page–“invalid” indicates that the page is not in the process’s logicaladdress space

4. Paging Contd…


Valid (v) or Invalid (i) Bit In A Page Table

4.4 Shared Pages

• An advantage of paging is thepossibility of sharing commoncode

• If the code is reentrant code(or pure code), it can be shared

• One copy of read-only(reentrant) code shared amongprocesses (i.e., text editors,compilers, window systems).

4. Paging Contd…

compilers, window systems).

• Shared code must appear insame location in the logicaladdress space of all processes

• Each process keeps a separatecopy of the code and data

• The pages for the private codeand data can appear anywherein the logical address space


Sharing of code in a paging environment

5. Structure of the Page Table

5.1 Hierarchical Paging• Break up the logical address space into

multiple page tables• A simple technique is a two-level page table

• A logical address (on 32-bit machine with 1Kpage size) is divided into a page numberconsisting of 22 bits and a page offsetconsisting of 10 bits

Techniques for structuring the page table : 1. HierarchicalPaging 2. Hashed Page Tables 3. Inverted Page Tables

consisting of 10 bits

• Since the page table is paged, the pagenumber is further divided into a 12-bit pagenumber a 10-bit page offset

where pi is an index into the outer pagetable, and p2 is the displacement within thepage of the outer page table


Two-Level Page-Table Scheme

page number page offset

pi p2 d

12 10 10

• Address-Translation Scheme for a two-level 32-bit paging architecture

5. Structure of the Page Table Contd…

• Three-level Paging Scheme• Example 64 bit logical address


Using two-level paging scheme

Using three-level paging scheme

5.2 Hashed Page Tables• Common in address spaces > 32 bits• The virtual page number is hashed into a page table. This page table contains

a chain of elements hashing to the same location.• Virtual page numbers are compared in this chain searching for a match. If a

match is found, the corresponding physical frame is extracted.



Hashed Page Table

p & q - page numberss & r - frame numbers

5.3 Inverted Page Table• One entry for each real page of memory• Entry consists of the virtual address of the page stored in that real memory

location, with information about the process that owns that page• Decreases memory needed to store each page table, but increases time

needed to search the table when a page reference occurs• Use hash table to limit the search to one — or at most a few — page-table

entries



Inverted Page Table Architecture

6. Segmentation• Memory-management scheme that supports user view of memory i.e. a

collection of variable-sized segments, with no necessary ordering amongsegments

6.1 Basic Method• Segments are numbered and are referred to

by a segment number i.e. a logical addressconsists of a two tuple:

< segment-number, offset >• A program is a collection of segments,

User's view of a program


• A program is a collection of segments,compiler constructs separate segments for :

• The code

• Global variables

• The heap, from which memory isallocated

• The stacks used, by each thread

• The standard C library

6.2 Hardware• Segment table – maps 2 dimensional physical addresses, each table entry has:

– base – contains the starting physical address where the segments reside inmemory

– limit – specifies the length of the segment

6. Segmentation Contd…

• Segment-table baseregister (STBR) points tothe segment table’slocation in memory

• Segment-table length


• Segment-table lengthregister (STLR) indicatesnumber of segmentsused by a program;

Segment number s is legal

if s < STLR

Segmentationhardware.

6. Segmentation Contd…

• Segment 2 is 400bytes long and beginsat location 4300. Thus,a reference to byte 53of segment 2 ismapped onto location4300 + 53 = 4353

• Segment 3, byte 852,is mapped to 3200 (thebase of segment 3) +


Example of Segmentation

base of segment 3) +852 = 4052

• A reference to byte1222 of segment 0would result in a trapto the operatingsystem, as thissegment is only 1,000bytes long

8 memory management strategies

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