741 op-amp
DESCRIPTION
741 Op-Amp. Where we are going:. Typical CMOS Amplifier. -6. 10. -7. 10. -8. 10. Drain current (A). -9. 10. k = 0.58680 I o = 1.2104fA. -10. 10. nFET. pFET. S. D. -11. 10. 0.4. 0.45. 0.5. 0.55. 0.6. 0.65. 0.7. 0.75. 0.8. 0.85. 0.9. Gate voltage (V). G. G. B. - PowerPoint PPT PresentationTRANSCRIPT
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741 Op-AmpWhere we are going:
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Typical CMOS Amplifier
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Subthreshold MOSFETs
0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.910
-11
10-10
10-9
10-8
10-7
10-6
Gate voltage (V)
Dra
in c
urr
en
t (A
)
= 0.58680 Io = 1.2104fA
In linear scale, we have a quadraticdependence
In log-scale, wehave an exponentialdependence
G
S
D
nFET
G
S
D
B
pFET
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MOSFET Current-Voltage Curves
1
/)(0
//)(0
///0
TSG
TdsTSG
TDTSTG
uVV
uVuVV
uVuVuVDS
eI
eeI
eeeII
Saturation
4 Tds UV
eeIIuVVuVV TdgTSg //
0
1 //0
TSdTSg uVVuVVeeI
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Drain Characteristics
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Current Sources
Ever wonder howwe make one of these?
GND
Vb M5
Vout
Iout
CurrentSink
V1
Vdd
M6
Iout
CurrentSource
How “good” a current source?
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Current versus Drain Voltage
Not flat due to Early effect (channel length modulation)
Id = Id(sat) (1 + (Vd/VA) )
Id = Id(sat) eVd/VA
or
Ic = Ic(sat) (1 + (Vc/VA) )
Ic = Ic(sat) eVc/VA
Rout10A
GND
Iout
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Current Mirrors
GNDGND
Iin
Vb M5Mb
Vout
Iout
Iout = ( (W/L)5 / (W/L)b ) Iin
nFET Current Mirror
A good way to generate a bias current
pFET Current Mirror
Iout = ( (W/L)7 / (W/L)4 ) Iin
Vdd Vdd
Vb
Iin
Iout
M7M4
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Current Mirror
GNDGND
Iin
Vb
M5
Mb
Vout1
Iout1
GND
M6
Vout2
Iout2
GND
M7
Vout3
Iout3
Iout = ( (W/L)5 / (W/L)b ) Iin Iout / Iin =
( (W/L)6 / (W/L)b )
Iout / Iin =
( (W/L)7 / (W/L)b )
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Diode-Capacitor Dynamics
C (dVi/dt) = I
in - Ico exp(V
i/U
T)
Iout
= Ico
exp(Vi/U
T)
(C / Iout
) (d Iout
/dt) = Iin - I
out
C (d Iout
/dt) = Iout
( Iin - I
out )
GND
Iin
GNDGND
Iout
Vi
C
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Basic One-Transistor Circuits
Common GateCommon Source Source Follower
The fundamental two-transisor circuit: Differential Pair
Common BaseCommon Emitter Emitter Follower
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Multiple Transistor Configurations
GND
10A
Vdd
GND
Vout
Vin
500A
Vdd
100pA
Vdd
Vout
Vin
GND
Vout
Vin
JFETs as well….
SubthresholdMOS
Above thresholdMOS
BJT
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Above Threshold MOSFET Equations
I = (K/2) ( ((Vg - VT) - Vs)2 - ((Vg - VT ) - Vd) 2 )
Saturation: Qd = 0
I = (K/2) ( ((Vg - VT) - Vs)2
If = 1 (ignoring back-gate effects):
I = (K/2) ( 2(Vgs - VT) Vds - Vds2 )
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Gummel Plots
0.1 0.2 0.3 0.4 0.5 0.6 0.710
-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
Base-Emitter Voltage (V)
Cur
rent
s
Ic: n=1, Is = 5.52fA
Ib: n=1.019, Is = 0.048fA
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Small-Signal Modeling
gmV ro
V3
V2V2
r
V1 +
V
-
V3
V2
V1
V3
V2
V1
gm ror
BJT
Above VTMOSFET
Sub VTMOSFET
Av
(UT ) / I
I I
I / UT
I / UT
2I /(V1-V2 -VT)
VA / I
VA / I
VA / I
VA / UT
VA / UT
2VA/(V1-V2 -VT)
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Signal Flow in Transistors
Rules of Thumb
• The collector or drain can never be an input terminal.
• The base or gate can never be an output terminal.
In addition it is important to note polarity reversals on these signal paths.
• The base-collector or gate-drain path inverts.
• All other paths are noninverting.
(This of course assumes that there are no reactive elements causing phase shifts)
(Never is too strong a word)
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Spectrum of Amplifier “Loads”Vdd
GND
R1
Vout
Vin
10A
Vdd
GND
Vout
Vin
Vb
Vdd
GND
Vout
Vin
Ideal CurrentSource Load
Transistor CurrentSource Load
ResistiveLoad
Remember: On-chip resistors are expensive
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Basic One-Transistor Circuits
Source Follower or Emitter Follower
Buffers (Isolates) the input to (from) the output
Assuming an ideal current source:
Ibias = Ieo e(Vin -Vout )/UT
Vout = -UT ln(Ibias/Ieo) + Vin
Vout = Vin
Ibias = Ibias eVin -Vout )/UT
100A
Vdd
GND
Vout
Vin
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Basic One-Transistor CircuitsAssuming an ideal current source:
Ibias = Io eVin/UT e
-Vout/UT
Vout = UT ln(Ibias/Io) + Vin
Vout = Vin
Ibias = Ibias eVin/UT e
-Vout/UT
10nA
Vdd
GND
Vout
Vin
If we use a transistor as a current source:
Id = Ibias eVout/VA = Io e
Vin/UT e-Vout/UT
Vout = UT ln(Ibias/Io) + ( // (VA/UT))Vin
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MOS Follower Circuits
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Source Degeneration
GND
Vout
Vin
GND
Vout
Vin
CircuitElement
Why do this?
• Higher Linearity• Possible Stability
Why not do this? gm
• Lower Bandwidth• Higher Noise / f
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Source Degeneration
GND
Vout
Vin
GND
Vout
Vin
V1
Neglect VA of Q1 and assume matched devices:
Q1
II = Ieo e
V1 /UT = Ieo e(Vin - V1 + Vout/Av )/UT
2 V1 = Vin + Vout / Av
I = Ieo e(Vin + Vout/Av )/(2 UT)
A similar result for MOSFETs