7.2 peripheral supplementary 2 dma. reference siberschatz, “operating system concepts sixth...

10
7.2 Peripheral Supplementary 2 DMA

Upload: ashlynn-ray

Post on 13-Dec-2015

216 views

Category:

Documents


2 download

TRANSCRIPT

Page 1: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

7.2 Peripheral Supplementary 2

DMA

Page 2: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

Reference Siberschatz, “Operating System Concepts

Sixth Edition”, John Wiley and Sons, Inc

Page 3: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

Programmed I/O For a device that does large transfers, such

as disk drive, it seems wasteful to use an expensive general-purpose processor to watch status bits and to feed data into a controller register 1 byte at a time.

This process termed “programmed I/O”

Page 4: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

Direct Memory Access (DMA) Many computers avoid burdening the main

CPU with PIO by offloading some of this work to a special-purpose processor called a direct memory-access (DMA) controller.

Page 5: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

DMA To initiate a DMA transfer:

The host writes a DMA command block into memory This block contains

A pointer to the source of a transfer A pointer to the destination of the transfer A count pf the number of bytes to be transferred.

The CPU writes the address of this command to the DMA controller, then goes on with other work.

The DMA controller proceeds to operate the memory bus directly, placing addresses on the bus to perform transfer without the help of the main CPU.

Page 6: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

During DMA Device driver is told to transfer disk data to buffer at

address X. (in memory) Device driver tells disk controller to transfer C bytes

from disk to buffer at address X Disk controller initiates DMA transfer Disk controller sends each byte to DMA controller DMA controller transfers bytes to buffer X, increasing

memory address and decreasing C until C = 0 When C =0, DMA interrupts CPU to signal transfer

completion

Page 7: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

Performance When the DMA controller seized the memory

bus, the CPU is momentarily prevented from accessing main memory, although it can still access data items in its primary and secondary cache.

Although this cycle stealing can slow down the CPU computation, offloading the data-transfer work to a DMA controller generally improves the total system performance.

Page 8: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

Direct Virtual-memory access (DVMA) DVMA can perform a transfer between two

memory-mapped devices without the intervention of the CPU or the use of main memory.

Page 9: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

Pros and Cons If system prevents process from issuing

device commands directly (e.g. access memory directly): Pros:

protect data from access-control violations Protect eh system from erroneous use of device

controllers that could cause a system crash. Cons:

Relatively low system performance

Page 10: 7.2 Peripheral Supplementary 2 DMA. Reference Siberschatz, “Operating System Concepts Sixth Edition”, John Wiley and Sons, Inc

Pros and Cons Allow direct access:

Pros: Obtain high performance, since avoid kernal

communication, context switches, and layers of kernal software.

Cons: System security System stability.