68hc11 timing system

ELET 3144 R. Alba-Flores 1

68HC11 Timing System


Programmable Timer

The internal programmable timer is a device that is very powerful because it allows measuring of time periods, frequency, delays, etc., in very efficient and easy ways.

Time periods are measured using different internal timing devices which includes counters, scalars, flags and interrupts. This makes the measurement process more precise and easy to implement .

There are different devices that can be used to measure time include the following:

– Free running counter

– Timer overflow flag

– Timer overflow Interrupt

– Real time interrupt

– Output Compare Channels

– Input Capture Channels

– Pulse Accumulators

Time Measuring Methods


The 68HC11 timing is controlled by a crystal oscillator connected to the XTAL and EXTAL pins on the 68HC11.

The E clock, which determines the time of each instruction cycle is ¼ of the crystal frequency.

For the Adapt 11 evaluation board the basic clock is 8MHz and the E clock is 2 MHz.

Therefore the time of each instruction cycle is 0.5 µsec.

68HC11 Timing System


The output of the E clock is connected to a 16-bit counter, called the TCNT register, that is at locations $100E and $100F.

TCNT is cleared at RESET.

This is a read only register. It can not be written but it will be incremented by every tick of the E clock

The Free-Running Counter


The Free-Running Counter


Resolution is the smallest time interval that can be measured in a system.

In the 68HC11 the TCNT register is incremented once every 0.5 µsec. This 0.5 µsec is the resolution of the microcontroller system.

Because the TCNT register is 16 bits, it takes 65,536 ( 216 ) counts to cycle it around once.

At the standard clock frequency of 2 MHz, the TCNT register requires 32.77 msec to roll over ( 65,536 x 0.5 µsec).

The Prescalar

The 68HC11 contains a prescalar that allows the user to lengthen the time of each count by dividing the E clock before it is applied to the input of the TCNT register. The available factor are: 1, 4, 8, and 16 and can be selected using the bits 0 and bit 1 in the TMSK ($1024) control register.

PR1 PR0 PrescaleFactor

Bus Frequency (E Clock) 2 MHzResolution / Overflow

0 0 1 0.5 µsec / 32.77msec

0 1 4 2 µsec / 131.1 msec

1 0 8 4 µsec / 262.1 msec

1 1 16 8 µsec / 524.3 msec

The Prescalar


Every time the TCNT register rolls over from FFFF to 0000, the TOF (Timer Over Flow) bit is set.

The user has no control over TCNT, so TOF will be set every 32.77 msec

Timer Overflow

10

Clearing the TOF bitMany of the flag bits in the 68HC11 control registers, including the TOF, are cleared by writing a 1 into the bit position of the flag. Writing a 0 into the bit position has no effect on the flag.

A routine to clear TOF is:

SUB1: LDAA #$80 ; Set bit 7 to 1

STAA $1025 ; Write it to TFLG2

RTS ; Return

A flag can also be cleared using a BCLR instruction, with a 0 in the bit position to be cleared. This is because the 68HC11 uses the inverse mask to clear the bit. To clear TOF, for example, the following instructions would work:

LDX #$1000

BCLR $25 , X $7F


The TCNT register can be used to create time delays.

A subroutine to cause a time delay for any amount of time is shown below.

In this subroutine N1 is the number of 32.77ms intervals that the time delay requires

DIFF is the difference between the time of the intervals and the time of the delay.

In the subroutine the number of intervals is loaded into register Y .

The content of TCNT is added to DIFF and stored in register D.

Note that if the sum is too large for D, then Y must be incremented by one.

Example 1

ORG $2000 ; * This is a General Subroutine for any time delay

N1: FDB ? ? ; Number of 32.77ms intervals

DIFF: FDB ? ? ; Difference between the time of the interval and the time of the delay

TCNT: EQU $100E

TFLG2: EQU $1025

; * Starting of the subroutine

SUB1: LDY N1 ; Y will hold the number of intervals

JSR SUB2 ; Clear TOF

LDD TCNT ; Read TCNT and add the Difference,

ADDD DIFF ; Store the result in D

BCC LOOP1 ; If the sum of TCNT and DIFF is too large for register D

INY ; (i.e. Carry =1 in CCR), then Y must be incremented by one

LOOP1: CPY #0

BEQ LOOP2 ; Go to LOOP2 when done with number of intervals

LOOP3: TST TFLG2 ; Test TOF and wait to be set.

BPL LOOP3 ; When TOF is set clear it and decrement Y

JSR SUB2 ; Go to clear TOF

DEY

BNE LOOP1

LOOP2: CPD TCNT ; Wait until TCNT reaches the content

BHI LOOP2 ; of register D

RTS ; end of GENDEL subroutine, return to main program

; * Subroutine to clear TOF

SUB2: LDAA #$80

STAA TFLG2

RTS

Example 2.Using the program in example 1, generate a 100-ms time delay.

To create a 100-ms delay, we first divide 100 ms by 32.77 ms, the timer for TCNT to count around. This gives three cycles (3 X 32.77 ms = 98.31 ms) plus 1.69 ms, or 3380 counts of the E clock.

If N1 is set to 3 and DIFF is set to $0D34 (the hex equivalent of 3380), the program will generate a 100-ms time delay.

Exercise. Write a program to set PB0 high for 100 ms and then low for 100ms. Use the GENDEL subroutine of example 1.


Input Capture Registers


Input capture registers are a set of three 16-bit registers that are connected to the free running counter TCNT and are controlled by hardware signals (internally or externally generated)




The Input Capture registers can be used to trap or store the value of the TCNT counter.

There are 3 Input Capture Registers in the 68HC11, TIC1, TIC2 and TIC3, and they are 16 bit registers. They are connected to pins PA2, PA1 and PA0 (Input onlypins) at Port A.

These registers make a capture when an edge occurs in one of these input pins.

When a capture is made in one of the registers, the time of the capture (input capture) is copied from the TCNTregister into the Input Capture Register (TIC).


The three 16-bit TIC registers (TIC1, TIC2, TIC3), are located at memory locations $1010 to $1015


The Input Captures are controlled by the edge bits in TCTL2 ($1021) in the following way:

TCTL2 at $1021

0 0 EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A

EDGxB EDGxA Configuration0 0 Capture disabled0 1 Capture on rising edges only1 0 Capture on falling edge only1 1 Capture on any edge (rising or falling)


Example 3.

The time of a falling edge on pin PA1 must be detected. How must TCTL2 be set up to do this?

Sol.

PA1 is connected to TIC2 (Input Capture Register 2). The previous table shows that the edge bits must be 1and 0, respectively, to capture a falling edge, thus the code:

LDAA #$08

STAA $1021

will set up TCTL2 to capture the time of a falling edge on PA1.


Input Flags and Interrupts.

Bits 0, 1 and 2 of the TFLG1 register, at $1023, are used to signal an input capture on registers 3, 2,and 1, respectively, as shown in the following figure,

OC1I OC2I OC3I OC4I OC5I IC1I IC2I IC3I

OC1F OC2F OC3F OC4F OC5F IC1F IC2F IC3F

TMSK1 at $1022

TFLG1 at $1023

If a capture is made, the flag will set. The flag can be cleared by writing a "1" into its bit position.


The corresponding interrupt bit is in TMSK1. If this bit is set, a capture will cause an interrupt in accordance with the following table:

Register Pin Location INTERRUPT VECTOR PSEUDO-VECTOR

TIC1 PA2 $FFEE - $FFEF $00E8-$00EA

TIC2 PA1 $FFEC - $FFED $00E5-$00E7

TIC3 PA0 $FFEA - $FFEB $00E2-$00E4

Example 4.

Determining the Period of a Square Wave.

• The following program determines the period of a square wave by finding the time between rising edges.

• The TCTL at $1021 is set up to detect rising edges on PA0.

• Then the program jumps to SUB2, which clears the input capture flag IC3F, and waits until it is set again.

• The time of its setting is stored in TIC3, at $1014 and $1015. This time is saved in memory (at location FIRST) and SUB2 is executed again to get the time of the next positive edge.

• The difference between the times is a measure of pulse width.

23

; *** This is a program to determine the period of a square wave connected to PA0

; *** PA0 is connected to TIC3

TCTL: EQU $21

TFLG1: EQU $23

TIC3: EQU $14

ORG $C100

FIRST: FDB

RESULT: FDB

BEGIN: LDX #$1000

LDS #$C400

LDAA #$01 ; Set the edge bits for IC3

STAA TCTL,X ; to capture on rising edges

JSR SUB2 ; Clear IC3F and wait until it sets

LDD TIC3,X ; Save time of first edge

STD FIRST

JSR SUB2 ; Clear IC3F and wait until it sets

LDD TIC3,X ; Get time of next edge

SUBD FIRST ; Subtract to get the time difference

STD RESULT

SWI ; End of main program


; * Subroutine to clear the input capture flag IC3F, and then wait until it sets again

SUB2: LDAA #$01 ; Clear the ICF3

STAA TFLG1,X

LOOP: BRCLR

TFLG1,X $01 LOOP

; Wait until it sets

RTS

END

68hc11 timing system

Documents