56f8323 - nxp

56F830016-bit Digital Signal Controllers

freescale.com

56F8323Evaluation Module User Manual

MC56F8323EVMUMRev. 207/2005

Document Revision History

Version History Description of Change

Rev 1.0 Initial Public Release

Rev 2.0 Updated look and feel

TABLE OF CONTENTS

Table of Contents, Rev. 2

Freescale Semiconductor i Preliminary

Preface Preface-vii

Chapter 1 Introduction

1.1 56F8323EVM Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21.2 56F8323EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31.3 56F8323EVM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Chapter 2 Technical Summary

2.1 56F8323. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.2 RS-232 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42.3 Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82.3.1 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82.3.2 Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92.4 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-122.7 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142.7.1 Peripheral Daughter Card Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142.7.2 Memory Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-172.8 Serial 10-bit 4-channel D/A Converter (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-192.9 Motor Control PWM Signals and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-202.10 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-212.11 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-222.12 Peripheral Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-232.12.1 PWM Port A Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-232.12.2 Serial Peripheral Interface #0 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . 2-242.12.3 Serial Peripheral Interface #1 Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . 2-242.12.4 Serial Communications Port #0 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-252.12.5 Serial Communications Port #1 Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-252.12.6 Encoder #0 / Quad Timer Channel A Expansion Connector. . . . . . . . . . . . . . . . . . 2-262.12.7 Timer Channel C Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-262.12.8 FlexCAN Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-272.12.9 A/D Port A Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27

MC56F8323EVM User Manual, Rev. 2

ii Freescale Semiconductor Preliminary

2.12.10 GPIO Port A Expansion Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-282.12.11 GPIO Port B Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-292.12.12 GPIO Port C Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-292.12.13 IRQA / RESET / CLOCK Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . 2-302.13 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30

Appendix A 56F8323EVM Schematics

Appendix B 56F8323EVM Bill of Material

LIST OF FIGURES

List of Figures, Rev. 2

Freescale Semiconductor iii Preliminary

1-1 Block Diagram of the 56F8323EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21-2 56F8323EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31-3 Connecting the 56F8323EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52-1 Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42-2 Schematic Diagram of the Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62-3 Schematic Diagram of the Debug LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72-4 Block Diagram of the Parallel JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92-5 Schematic Diagram of the User Interrupt Interface. . . . . . . . . . . . . . . . . . . . . . . . . 2-112-6 Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112-7 Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-132-8 Serial 10-bit, 4-Channel D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-192-9 PWM Interface and LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-202-10 CAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-212-11 Software Feature Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-222-12 Typical Analog Input RC Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28


iv Freescale Semiconductor Preliminary

LIST OF TABLES

List of Tables, Rev. 2

Freescale Semiconductor v Preliminary

1-1 56F8323EVM Default Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42-1 Flow Control Header Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42-2 SCI1 Jumper Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52-3 RS-232 Serial Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52-4 LED Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62-5 JTAG Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82-6 Parallel JTAG Interface Disable Jumper Selection . . . . . . . . . . . . . . . . . . . . . . . 2-82-7 Parallel JTAG Interface Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-102-8 Parallel JTAG Interface Voltage Selection Jumper . . . . . . . . . . . . . . . . . . . . . . 2-102-9 Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . 2-142-10 Memory Daughter Card Connector Description . . . . . . . . . . . . . . . . . . . . . . . . 2-172-11 D/A Header Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-192-12 CAN Signal Isolation Jumper Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-212-13 CAN Header Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-222-14 PWM Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-232-15 SPI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-242-16 SPI #1 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-242-17 SCI #0 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-252-18 SCI #1 Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-252-19 Timer A Signal Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-262-20 Timer Channel C Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-262-21 CAN Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-272-22 A/D Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-272-23 GPIO Port A Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-282-24 GPIO Port B Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-292-25 GPIO Port C Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-292-26 IRQA / RESET / CLOCK Connector Description. . . . . . . . . . . . . . . . . . . . . . . 2-30


vi Freescale Semiconductor Preliminary

Preface, Rev. 2

Freescale Semiconductor vii Preliminary

PrefaceThis reference manual describes in detail the hardware on the 56F8323 Evaluation Module.

AudienceThis document is intended for application developers who are creating software for devices using the Freescale 56F8323 part.

OrganizationThis manual is organized into two chapters and two appendixes.

• Chapter 1, Introduction - provides an overview of the EVM and its features.• Chapter 2, Technical Summary - describes in detail the 56F8323EVM hardware.• Appendix A, 56F8323EVM Schematics - contains the schematics of the

56F8323EVM.• Appendix B, 56F8323EVM Bill of Material - provides a list of the materials used on

the 56F8323EVM board.

Suggested ReadingMore documentation on the 56F8323 and the 56F8323EVM kit may be found at URL:

www.freescale.com


viii Freescale Semiconductor Preliminary

Notation ConventionsThis manual uses the following notational conventions:

Term or Value Symbol Examples Exceptions

Active High Signals (Logic One)

No special symbol attached to the signal name

A0CLKO

Active Low Signals(Logic Zero)

Noted with an overbar in text and in most figures

WEOE

In schematic drawings, Active Low Signals may be noted by a back-slash: /WE

Hexadecimal Values Begin with a “$” symbol

$0FF0$80

Decimal Values No special symbol attached to the number

1034

Binary Values Begin with the letter “b” attached to the number

b1010b0011

Numbers Considered positive unless specifically noted as a negative value

5-10

Voltage is often shown as positive: +3.3V

Blue Text Linkable on-line ...refer to Chapter 7, License

Bold Reference sources, paths, emphasis

...see: www.freescale.com

Preface, Rev. 2

Freescale Semiconductor ix Preliminary

Definitions, Acronyms, and AbbreviationsDefinitions, acronyms and abbreviations for terms used in this document are defined below for reference.

A/D Analog-to-Digital; a method of converting Analog signals to Digital values

ADC Analog-to-Digital Converter; a peripheral on the 56F8323 partCAN Controller Area Network; a serial communications peripheral and

methodCiA CAN in Automation; an international CAN user’s group that coordinates

standards for CAN communications protocolsCTS Clear To SendD/A Digital-to-Analog; a method of converting Digital values to an Analog

form56F8323 A 16-bit controller with motor control peripheralsEOnCE Enhanced On-Chip Emulation; a debug bus and port created by

Freescale to enable a designer to create a low-cost hardware interface for a professional-quality debug environment

EVM Evaluation Module; a hardware platform which allows a customer to evaluate the silicon and develop his application

Flash Nonvolatile Random Access MemoryFlexCAN Flexible CAN Interface Module; a peripheral on the 56F8323 partGPIO General Purpose Input and Output port on Freescale’s family of

controllers; does not share pin functionallity with any other peripheral on the chip and can only be set as an input, output, or level-sensitive interrupt input

IC Integrated CircuitJTAG Joint Test Action Group; a bus protocol/interface used for test and debugLED Light Emitting DiodeLQFP Low-profile Quad Flat PackageMPIO Multi-Purpose Input and Output port on Freescale’s family of

controllers; shares package pins with other peripherals on the chip and can function as a GPIO


x Freescale Semiconductor Preliminary

ReferencesThe following sources were referenced to produce this manual:

[1] DSP56800E Reference Manual, DSP56800ERM; Freescale Semiconductor[2] 56F8300 Peripheral User Manual, MC56F8300UM; Freescale Semiconductor[3] 56F8323 Technical Data, MC56F8323; Freescale Semiconductor[4] CiA Draft Recommendation DR-303-1, Cabling and Connector Pin Assignment,

Version 1.0, CAN in Automation[5] CAN Specification 2.0B, BOSCH or CAN in Automation

OnCE On-Chip Emulation, a debug bus and port created by Freescale to allow a means for low-cost hardware which provides a professional-quality debug environment

PCB Printed Circuit BoardPLL Phase Locked LoopPWM Pulse Width ModulationQuad Dec Quadrature Decoder; a peripheral on the 56F8323 partRAM Random Access MemoryR/C Resistor/Capacitor NetworkSRAM Static Random Access MemoryRTS Request to SendSCI Serial Communications Interface; a peripherial on Freescale’s family of

controllersSPI Serial Peripheral Interface; a peripheral on Freescale’s family of

controllersUART Universal Asynchronous Receiver/TransmitterWS Wait State

Introduction, Rev. 2

Freescale Semiconductor 1-1 Preliminary

Chapter 1 IntroductionThe 56F8323EVM is used to demonstrate the abilities of the 56F8323 and to provide a hardware tool allowing the development of applications that use the 56F8323.

The 56F8323EVM is an evaluation module board that includes an 56F8323 part, peripheral expansion connectors, a CAN interface, an RS-232 interface, a JTAG-to-PC Printer port interface and a pair of daughter card connectors. The peripheral expansion connectors and daughter card expansion connectors are for signal monitoring and allow expansion for user features.

The 56F8323EVM is designed for the following purposes:• Allowing new users to become familiar with the features of the 56800E architecture. The

tools and examples provided with the 56F8323EVM facilitate evaluation of the feature set and the benefits of the family.

• Serving as a platform for real-time software development. The tool suite enables the user to develop and simulate routines, download the software to on-chip SRAM or Flash, run it, and debug it using a debugger via the JTAG/Enhanced OnCE (EOnCE) port. The breakpoint features of the EOnCE port enable the user to easily specify complex break conditions and to execute user-developed software at full speed until the break conditions are satisfied. The ability to examine and modify all user-accessible registers, memory and peripherals through the EOnCE port greatly facilitates the task of the developer.

• Serving as a platform for hardware development. The hardware platform enables the user to connect external hardware peripherals. The on-board peripherals can be disabled, providing the user with the ability to reassign any and all of the controller's peripherals. The EOnCE port's unobtrusive design means that all memory on the Processor is available to the user.


1-2 Freescale Semiconductor Preliminary

1.1 56F8323EVM ArchitectureThe 56F8323EVM facilitates the evaluation of various features present in the 56F8323 part. The 56F8323EVM can be used to develop real-time software and hardware products based on the 56F8323. The 56F8323EVM provides the features necessary for a user to write and debug software, demonstrate the functionality of that software and interface with the user's application-specific device(s). The 56F8323EVM is flexible enough to allow a user to fully exploit the 56F8323's features to optimize the performance of his product, as shown in Figure 1-1.

56F8323

RESET

JTAG / EOnCE

SPI #0

SCI #1

Timer C

PWMA

+3.3V & GND +3.3VA & AGND

+3.0VREF

Peripheral Expansion Connectors

JTAGConnector

ParallelJTAG

Interface

DSub25-Pin

DSub9-Pin

PWM LEDs

RS-232Interface

Power Supply+3.3V, +3.3VA, +5V & +3.0VA

4-Channel10-Bit D/A

SCI #0

Reset Logic

CAN Interface

Debug LEDs

CAN BusHeader

CAN BusDaisy Chain

Peripheral Daughter Card

Connector

Optional

Timer A

ADCAQuadDec #0

FlexCAN

D/A Header

XTAL/EXTAL8.00MHzCrystal

Figure 1-1. Block Diagram of the 56F8323EVM

56F8323EVM Configuration Jumpers



1.2 56F8323EVM Configuration JumpersFifteen jumper groups, (JG1-JG15), shown in Figure 1-2, are used to configure various features on the 56F8323EVM board. Table 1-1 describes the default jumper group settings.

JG6

MC56F8323EVM

U3

J3

JTAG

P2

S/N

LED3

P1

Y1

U1

S2 S1P3

U9

RESETIRQA

1

2

JG5

JG11

JG3

JG7

JG4 JG13

JG5

1

JG7

3

JG4

PWMA0PWMA1PWMA2PWMA3PWMA4PWMA5

U10

JG6

JG10 J19

J10

J18

JG8

J6J4

J16

J14

J2

J1

J5

J21

J7J8

J17

J9

J11J12

J13

J15

1JG1

3

1

JG8

3

3

4

JG12

JG3

JG9

JG10 JG2

JG11

JG9

JG2JG1JG12

PC0PC1PC2PC3PC4PC5

12

JG15

34

JG13

1JG14

3

J15

JG14

Figure 1-2. 56F8323EVM Jumper Reference

Table 1-1. 56F8323EVM Default Jumper Options

JumperGroup Comment Jumpers

Connections

JG1 Connect on-board 8.0MHz crystal input to EXTAL signal 1–2

JG2 Connect on-board 8.0MHz crystal input to XTAL signal 1–2

JG3 Enable on-board Parallel JTAG Host/Target Interface NC

JG4 Enable RS-232 output NC

JG5 Pass RXD1 & TXD1 signals to RS-232 level converter 1–2 & 3–4

JG6 Pass Temperature Diode signal to ANA7 input 1–2

JG7 Set user Jumper #0 to a 1 value 1–2

JG8 Set user Jumper #1 to a 1 value 1–2

JG9 SPI #0 Daisy Chain (Optional--not populated on board by default) NC

JG10 CAN bus termination selected 1–2

JG11 Connect Analog Ground to Digital Ground NC

JG12 Enable on-chip regulator 1–2

JG13 Pass RTS to CTS 1–2

JG14 Select +3.3V operation of on-board Parallel JTAG Host/Target Interface 1–2

JG15 Pass CAN_TX & CAN_RX signals to CAN tranceiver 1–2 & 3–4



56F8323EVM Connections



1.3 56F8323EVM ConnectionsAn interconnection diagram is shown in Figure 1-3 for connecting the PC and the external +12.0V DC/AC power supply to the 56F8323EVM board.

PC

CableParallel Extension

56F8323EVM

External+12VPower

P1

P3Connect cableto Parallel / Printer port

with 2.1mm,receptacleconnector

Figure 1-3. Connecting the 56F8323EVM Cables

Perform the following steps to connect the 56F8323EVM cables:

1. Connect the parallel extension cable to the Parallel port of the host computer.

2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3, on the 56F8323EVM board. This connection allows the host computer to control the board.

3. Make sure that the external +12V DC, 1.2A power supply is not plugged into a +120V AC power source.

4. Connect the 2.1mm output power plug from the external power supply into P3, shown in Figure 1-3, on the 56F8323EVM board.

5. Apply power to the external power supply. The green Power-On LED, LED13, will illuminate when power is correctly applied.

Technical Summary, Rev. 2


Chapter 2 Technical SummaryThe 56F8323EVM is designed as a versatile Flash-based microcontroller development card for developing real-time software and hardware products to support a new generation of applications in servo and motor control; digital and wireless messaging; digital answering machines; feature phones; modems; and digital cameras. The power of the 16-bit 56F8323, combined with the on-board RS-232 interface, CAN interface, Daughter Card Expansion interface and parallel JTAG interface, makes the 56F8323EVM ideal for developing and implementing many motor controlling algorithms, as well as for learning the architecture and instruction set of the 56F8323 processor.

The main features of the 56F8323EVM, with board and schematic reference designators, include:

• MC56F8323, a 16-bit +3.3V/+2.5V processor in a 64-pin LQFP package operating at 60MHz [U1]

• 8.00MHz crystal oscillator for processor frequency generation [Y1]• Optional external oscillator frequency input connectors [JG1 and JG2]• Joint Test Action Group (JTAG) port interface connector for an external debug Host

Target Interface [J3]• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer port

cable [P1], including a disable jumper [JG3]• On-board Parallel JTAG Host Taget Interface voltage level selector [JG14]• RS-232 interface for easy connection to a host processor [U3 and P2], with a disable

jumper [JG4]• RS-232 RTS and CTS signal connector [JG13]• CAN interface for high speed, 1.0Mbps, FlexCAN communications [U8 and J12]• CAN bypass and bus termination [J13 and JG10]• CAN signal to CAN transceiver isolation connector [JG15]• Peripheral Daughter Card Expansion Connector, which allows the user to attach his own

SCI, SPI, PWM, Quad Decoder or GPIO-compatible peripherals to the Processor [J1]



• Memory Daughter Card Expansion Connector, which allows the user to attach additonal power and grounds[J2]

• Connector which allows the user to attach his own SCI #0 / MPIO-compatible peripheral [J21]

• Connector which allows the user to attach his own SCI #1 / MPIO-compatible peripheral [J17]

• Connector which allows the user to attach his own SPI #0 / MPIO-compatible peripheral [J8]

• Connector which allows the user to attach his own SPI #1 / MPIO-compatible peripheral [J15]

• Connector which allows the user to attach his own PWMA-compatible peripheral [J5]• Connector which allows the user to attach his own CAN physical layer peripheral [J10]• Connector which allows the user to attach his own Timer A / Encoder #0-compatible

peripheral [J7]• Connector which allows the user to attach his own Timer C-compatible peripheral [J9]• Connector which allows the user to attach his own A/D port A-compatible peripheral [J6]• Connector which allows the user to attach his own peripheral to GPIO Port A [J16]• Connector which allows the user to attach his own peripheral to GPIO Port B [J18]• Connector which allows the user to attach his own peripheral to GPIO Port C [J19]• On-board power regulation from an external +12V DC-supplied power input [P3]• Light Emitting Diode (LED) power indicator [LED13]• Six on-board LEDs allow real-time debugging of user programs [LED1-6]• Six on-board Port A PWM monitoring LEDs [LED7-12]• Internal (OCR_DIS) Core Regulator selector [JG12]• Temperature Sense Diode-to-ANA7 selector [JG6]• Manual RESET push-button [S1]• Manual interrupt push-button for IRQA [S2]• General purpose jumper on GPIO PB3 [JG7]• General purpose jumper on GPIO PB0 [JG8]• Optional 4-Channel 10-bit Serial D/A, SPI for real-time user data display [U5]

56F8323



2.1 56F8323The 56F8323EVM uses a Freescale MC56F8323 part, designated as U1 on the board and in the schematics. This part will operate at a maximum external bus speed of 60MHz. A full description of the 56F8323, including functionality and user information, is provided in these documents:

• 56F8323 Technical Data Sheet, (MC56F8323): Electrical and timing specifications, pin descriptions, device specific peripheral information and package descriptions (this document)

• 56F8300 Peripheral User Manual, (MC56F8300UM): Detailed description of peripherals of the 56F8300 family of devices

• DSP56800E Reference Manual, (DSP56800ERM): Detailed description of the 56800E family architecture, 16-bit core processor, and the instruction set

Refer to these documents for detailed information about chip functionality and operation. They can be found on this URL:

www.freescale.com



2.2 RS-232 Serial CommunicationsThe 56F8323EVM provides an RS-232 interface by the use of an RS-232 level converter, Maxim MAX3245EEAI, designated as U3. Refer to the RS-232 schematic diagram in Figure 2-1. The RS-232 level converter transitions the SCI UART’s +3.3V signal levels to RS-232-compatible signal levels and connects to the host’s serial port via connector P2. Flow control is not provided, but could be implemented using uncommitted GPIO signals and connected to the RTS and CTS signals on JG13; see Table 2-1. The SCI1 port signals can be isolated from the RS-232 level converter by removing the jumpers in JG5; reference Table 2-2. The pin-out of connector P2 is detailed in Table 2-3. The RS-232 level converter/transceiver can be disabled by placing a jumper at JG4.

56F8323RS-232

Level Converter Interface

TXD1

RXD1

R1in

T1out

T2in

R2out

FORCEOFF

JG4

6

3

27

84

5x

1

9

+3.3V

Jumper Removed:Enable RS-232

P2

JG131

2

12Jumper Pin 1-2:

Disable RS-232

T1in

R1out

JG51 23 4

RTSCTS R2in

T2out

Figure 2-1. Schematic Diagram of the RS-232 Interface

Table 2-1. Flow Control Header Options

JG13

Pin # Signal

1 RTS to Transceiver

2 CTS from Transceiver

Table 2-2. SCI1 Jumper Options

JG5

Pin # Signal Pin # Signal

1 TXD1 2 TXD to RS-232 Transceiver

3 RXD1 4 RXD from RS-232 Transceiver

Table 2-3. RS-232 Serial Connector Description

P2


1 Jumper to 6 & 4 6 Jumper to 1 & 4

2 TXD 7 CTS

3 RXD 8 RTS

4 Jumper to 1 & 6 9 NC

5 GND

RS-232 Serial Communications



The 56F8323EVM uses on-chip 8.00MHz relaxation oscillator or the on-board 8.00MHz crystal, Y1, connected to its External Crystal Inputs, EXTAL and XTAL. To achieve its maximum internal operating frequency, the 56F8323 uses its internal PLL to multiply this input clock frequency. Additionally an external oscillator source can be connected to the device by using the oscillator bypass connectors, JG1 and JG2; see Figure 2-2. If the input frequency is above 8MHz, then the EXTAL input should be jumpered to ground by adding a jumper between JG1 pins 2 and 3. The input frequency would then be injected on JG2’s pin 2. If the input frequency is below 4MHz, then the input frequency can be injected on JG1’s pin 2.

56F8323

EXTERNAL OSCILLATOR

HEADERSJG11 23

1 2

EXTAL

XTAL

JG2

8.00MHz



Figure 2-2. Schematic Diagram of the Clock Interface

Six on-board Light-Emitting Diodes, (LEDs), are provided to allow real-time debugging for user programs. These LEDs will allow the programmer to monitor program execution without having to stop the program during debugging; refer to Figure 2-3. Table 2-4 describes the control of each LED.

Table 2-4. LED Control

Controlled by

User LED Color Signal

LED1 RED GPIO Port C Bit 0

LED2 YELLOW GPIO Port C Bit 1

LED3 GREEN GPIO Port C Bit 2

LED4 RED GPIO Port C Bit 3

LED5 YELLOW GPIO Port C Bit 4

LED6 GREEN GPIO Port C Bit 5

RS-232 Serial Communications



Setting PC0, PC1, PC2, PC3, PC4 or PC5 to a Logic One value will turn on the associated LED.

56F8323 INVERTING BUFFER

PC0

PC1

PC2GREEN LED

YELLOW LED

RED LED+3.3V

GREEN LED

YELLOW LED

RED LEDPC3

PC4

PC5

Figure 2-3. Schematic Diagram of the Debug LED Interface



2.3 Debug SupportThe 56F8323EVM provides an on-board Parallel JTAG Host Target Interface and a JTAG interface connector for external Target Interface support. Two interface connectors are provided to support each of these debugging approaches. These two connectors are designated the JTAG connector and the Host Parallel Interface Connector.

2.3.1 JTAG ConnectorThe JTAG connector on the 56F8323EVM allows the connection of an external Host Target Interface for downloading programs and working with the 56F8323’s registers. This connector is used to communicate with an external Host Target Interface which passes information and data back and forth with a host processor running a debugger program. Table 2-5 shows the pin-out for this connector.

Table 2-5. JTAG Connector Description

J3


1 TDI 2 GND

3 TDO 4 GND

5 TCK 6 GND

7 NC 8 KEY

9 RESET 10 TMS

11 +3.3V 12 NC

13 DE 14 TRST

When this connector is used with an external Host Target Interface, the parallel JTAG interface should be disabled by placing a jumper in jumper block JG3. Refer to Table 2-6 for this jumper’s selection options.

Table 2-6. Parallel JTAG Interface Disable Jumper Selection

JG3 Comment

No jumpers Enable On-board Parallel JTAG Interface

1–2 Disable on-board Parallel JTAG Interface

Debug Support



2.3.2 Parallel JTAG Interface ConnectorThe Parallel JTAG Interface Connector, P1, allows the 56F8323 to communicate with a Parallel Printer Port on a Windows PC; reference Figure 2-4. Using this connector, the user can download programs and work with the 56F8323’s registers. Table 2-7 shows the pin-out for this connector. When using the parallel JTAG interface, the jumper at JG3 should be removed, as shown in Table 2-6. A jumper at JG14 selects the Parallel Printer Port’s interface voltage between +3.3V and +5.0V; see Table 2-8.

DB-25 Connector Parallel JTAG Interface 56F8323

TDITDO

P_TRSTTMSTCK

P_RESET

OUTOUT

OUT

OUTOUT

OUTIN

ININ

IN

ININ

EN

TDITDOTRST

TMSTCK

RESET

JG312

+3.3V

Jumper Removed:Enable JTAG I/F

Jumper Pin 1-2:Disable JTAG I/F

P_DE OUTIN DE

Figure 2-4. Block Diagram of the Parallel JTAG Interface

Table 2-7. Parallel JTAG Interface Connector Description

P1


1 NC 14 NC

2 PORT_RESET 15 PORT_IDENT

3 PORT_TMS 16 N/C

4 PORT_TCK 17 N/C

5 PORT_TDI 18 GND

6 PORT_TRST 19 GND

7 PORT_DE 20 GND

8 PORT_IDENT 21 GND

9 PORT_VCC 22 GND

10 NC 23 GND

11 PORT_TDO 24 GND

12 NC 25 GND

13 PORT_CONNECT

Table 2-8. Parallel JTAG Interface Voltage Selection Jumper

JG14 Comment

1–2 +3.3V Parallel Printer Port Interface

2–3 +5.0V Parallel Printer Port Interface



Reset



2.4 External InterruptsOne on-board push-button switch is provided for external interrupt generation, as shown in Figure 2-5. S2 allows the user to generate a hardware interrupt for signal line IRQA. This switch allows the user to generate interrupts for user-specific programs.

56F8323

IRQA

+3.3V

10KS2

0.1µF

Figure 2-5. Schematic Diagram of the User Interrupt Interface

2.5 ResetLogic is provided on the 56F8323 to generate an internal Power-On RESET. Additional reset logic is provided to support the RESET signals from the JTAG connector, the Parallel JTAG Interface and the user RESET push-button, S1; refer to Figure 2-6.

RESETPUSHBUTTON

MANUAL RESET

JTAG_TAP_RESET

JTAG_RESETRESET

TRST

S1

Figure 2-6. Schematic Diagram of the RESET Interface



2.6 Power SupplyThe main power input to the 56F8323EVM, +12V DC at 1.2A, is through a 2.1mm coax power jack. This input power is rectified to provide a DC supply input. This allows a user the option to use a +12V AC power supply. A 1.2Amp power supply is provided with the 56F8323EVM; however, less than 500mA is required by the EVM. The remaining current is available for custom control applications when connected to the Daughter Card connectors. The 56F8323EVM provides +5.0V DC regulation for the CAN interface and additional regulators. The 56F8323EVM provides +3.3V DC voltage regulation for the processor, memory, D/A, ADC, parallel JTAG interface and supporting logic; refer to Figure 2-7. Additional voltage regulation logic provides a low noise +3.0V DC voltage reference to the controller’s A/D VREFH. Optionally, the processor’s A/D VREFH voltage can be provided by the +3.3VA supply on the board by removing U15 and adding a 10 ohm resistor at R83. A jumper, JG11, and resistor, R68, are provided to allow the analog and digital grounds to be isolated on the 56F8323EVM board. This allows the analog ground reference point to be provided on a custom board attached to the 56F8323EVM’s Daughter Card connectors. By removing R68, the AGND reference is disconnected from the 56F8323EVM’s digital ground. By placing a jumper in JG11 or by reinstalling R68, the AGND is reconnected to the 56F8323EVM’s digital ground. Power applied to the 56F8323EVM is indicated with a Power-On LED, referenced as LED13. Optionally, the user can provide the +2.5 DC voltage needed by the controller’s core on connector J14 and disable the on-chip CORE voltage regulator by removing the jumper on JG12. Additonally, four 0 ohm resistors or shorting wires must be added at R70, R71, R72 and R73, to allow the external +2.5V DC to pass to the 56F8323.

+5.0V DC+12V DC/ACPower

Condition CAN

56F8323VDD_IO & PLL

+3.3VRegulator

P3

56F8323EVMParts

56F8323VREFH

+3.3V DC

+3.0VA DC

+5.0VRegulator

56F8323 ADCA

+3.3VRegulator

+3.3VA DC

56F8323VDD Core+2.5V DC

Ext In1

2

J14

U15

R70-R73

R67 10Ω

BridgeRectifierInput

+3.0VRegulator

Power On

Power Supply



Figure 2-7. Schematic Diagram of the Power Supply



2.7 Daughter Card ConnectorsThe EVM board contains two daughter card expansion connectors. One connector, J1, contains the processor’s peripheral port signals. The second connector, J2, contains addional power and ground signals.

2.7.1 Peripheral Daughter Card Expansion ConnectorThe processor’s peripheral port signals are connected to the Peripheral Daughter Card Expansion connector, J1. The Peripheral Daughter Card connector is used to connect a user-specific daughter card to the processor’s peripheral port signals. The Peripheral Port Daughter Card connector is a 100-pin high-density connector with signals for the IRQs, RESET, SPI, SCI, PWM, ADC and Quad Timer ports. Table 2-9 shows the Peripheral Daughter Card connector’s signal-to-pin assignments.

Table 2-9. Peripheral Daughter Card Connector Description

J1


1 +12V 2 +12V

3 GND 4 GND

5 +5.0V 6 +5.0V

7 GND 8 GND

9 +3.3V 10 +3.3V

11 GND 12 GND

13 NC 14 NC

15 NC 16 NC

17 GND 18 GND

19 PHASEA0 / PB7 / TA0 20 PHASEB0 / PB6 / TA1

21 INDEX0 / PB5 / TA2 22 HOME0 / PB4 / TA3

23 TC0 24 SS0

25 TC0 26 SS0

27 TC1 28 MISO0

Daughter Card Connectors



29 IRQA 30 NC

31 TC1 32 TC3

33 PWMA0 34 PWMA1

35 PWMA2 36 PWMA3

37 PWMA4 38 PWMA5

39 GND 40 GND

41 ISA0 42 ISA1

43 ISA2 44 GND

45 FAULTA1 46 FAULTA0

47 NC 48 FAULTA2

49 GND 50 GND

51 NC 52 MISO0

53 NC 54 NC

55 NC 56 NC

57 GND 58 GND

59 NC 60 NC

61 NC 62 SS0

63 NC 64 NC

65 NC 66 NC

67 MOSI0 68 SS0

69 TC0 70 TC1

71 SCLK0 72 TC0

73 CAN_TX 74 CAN_RX

75 MOSI0 76 MISO0

77 SCLK0 78 SS0

Table 2-9. Peripheral Daughter Card Connector Description (Continued)

J1




79 GND 80 GND

81 +VREFH 82 +VREFH

83 GNDA 84 GNDA

85 NC 86 NC

87 NC 88 NC

89 NC 90 NC

91 NC 92 NC

93 AN0 94 AN1

95 AN2 96 AN3

97 AN4 98 AN5

99 AN6 100 AN7

Table 2-9. Peripheral Daughter Card Connector Description (Continued)

J1


Daughter Card Connectors



2.7.2 Memory Daughter Card Expansion ConnectorAdditional power and ground signals are connected to the Memory Daughter Card Expansion connector, J2. Table 2-10 shows the port signal-to-pin assignments.

Table 2-10. Memory Daughter Card Connector Description

J2


1 NC 2 NC

3 NC 4 NC

5 NC 6 NC

7 NC 8 NC

9 GND 10 GND

11 NC 12 NC

13 NC 14 NC

15 NC 16 NC

17 NC 18 NC

19 GND 20 GND

21 GND 22 GND

23 NC 24 NC

25 NC 26 NC

27 NC 28 NC

29 NC 30 NC

31 GND 32 GND

33 GND 34 GND

35 NC 36 NC

37 NC 38 NC

39 NC 40 NC

41 NC 42 NC



43 GND 44 GND

45 NC 46 NC

47 NC 48 NC

49 NC 50 NC

51 NC 52 GND

53 GND 54 GND

55 +3.3V 56 +3.3V

57 GND 58 GND

59 +5.0V 60 +5.0V

Table 2-10. Memory Daughter Card Connector Description (Continued)

J2


Serial 10-bit 4-channel D/A Converter (Optional)



2.8 Serial 10-bit 4-channel D/A Converter (Optional)The 56F8323EVM board contains the provions for a user to provide a serial 10-bit, 4-channel D/A converter connected to the 56F8323’s SPI #0 port. The output pins are uncommitted and are connected to a 4x2 header, J4, to allow easy user connections. Refer to Figure 2-8 for the D/A connections and Table 2-11 for the header’s pin-out. The D/A’s output full-scale range value can be set to a value from +0.0V to +2.4V by a trimpot, R48. If this trimpot is preset to +2.05V, it would provide approximately +2mV per step. If another device must be used with SPI #0’s MISO signal and with the D/A converter on the board, the daisy chain jumper, JG9, can be used to extend or isolate the serial chain.

135

7

246

8

D/A Connector

D/A 0

D/A 1

D/A 2

D/A 3

+3.3VAR48

VREF

MAX5251

DIN

DOUT

SCLK

CS

CL

MOSI0

12MISO0

SCLK0

SS0

JG9

56F8323

RSTO

Figure 2-8. Serial 10-bit, 4-Channel D/A Converter

Table 2-11. D/A Header Description

J4


1 D/A Channel 0 2 AGND






2.9 Motor Control PWM Signals and LEDsThe 56F8323 has one PWM unit. This unit contains six PWM output signals, three Fault input signals and three Phase Current sense inputs. The PWM signals are connected to a set of six PWM LEDs via inverting buffers. The buffers are used to isolate and drive the processor’s PWM outputs to the PWM LEDs. The PWM LEDs indicate the status of PWM signals; refer to Figure 2-9. Additionally, the PWM signals are routed out to a header, J5, and to the peripheral daughter card connector, J1, for easy use by the end user.

LED

+3.3V

LED9

56F8323

LED10

LED11

LED12

LED7

LED8

PWMA0PWMA1

PWMA2PWMA3

PWMA5

Buffer

PWMA0

Yellow LED

PWMA1

PWMA2PWMA3PWMA4PWMA5

Green LED

Yellow LED

Green LED

Yellow LED

Green LED

Phase A Top

Phase A Bottom

Phase B Top

Phase B Bottom

Phase C Top

Phase C Bottom

PWMA4

Figure 2-9. PWM Interface and LEDs

CAN Interface



2.10 CAN InterfaceThe 56F8323EVM board contains a CAN physical-layer interface chip that is attached to the FlexCAN port’s CAN_RX and CAN_TX pins on the 56F8323. The EVM board uses a Philips high-speed, 1.0Mbps, physical layer interface chip, PCA82C250. Due to the +5.0V operating voltage of the CAN interface chip, a pull-up to +5.0V is required to level shift the Transmit Data output line from the 56F8323. The CAN_TX and CAN_RX signals from the processor can be isolated by the connector at JG15; see Table 2-12. The CANH and CANL signals pass through inductors before attaching to the CAN bus connectors. A primary, J12, and daisy chain, J13, CAN connectors are provided to allow easy daisy chaining of CAN devices. CAN bus termination of 120 ohms can be provided by adding a jumper to JG10. Refer to Table 2-13 for the CAN connector signals and to Figure 2-10 for a connection diagram.

56F8323+5.0V

CAN Transceiver

J12

Daisy Chain CANConnector

J13

CAN BusConnector

CAN BusTerminator

JG10

120

PCA82C250T

1K

CAN_TX

CAN_RX

1

2

3

45

4

35

CANH

CANL

TXD

RXD

JG15

1

3 4

2

Figure 2-10. CAN Interface

Table 2-12. CAN Signal Isolation Jumper Options

JG15


1 CAN_TX 2 CAN_TX to CAN Transceiver

3 CAN_RX 4 CAN_RX from CAN Transceiver

Table 2-13. CAN Header Description

J12 and J13


1 NC 2 NC

3 CANL 4 CANH

5 GND 6 NC

7 NC 8 NC

9 NC 10 NC



2.11 Software Feature JumpersThe 56F8323EVM board contains two software feature jumpers that allow the user to select “user-defined” software features. Two GPIO port pins, PB3 and PB0, are pulled high or low with 10K ohm resistors on JG7 and JG8, respectively. Attaching a jumper between pins 1 and 2 will place a high, or 1, on the port pin. Attaching a jumper between pins 2 and 3 will place a low, or 0, on the port pin; see Figure 2-11.

56F8323JG7

User Jumper#0

12

3

10K

10K

+3.3V

JG8User Jumper

#11

23

10K

10K

+3.3V

SCLK0 / PB3

SS0 / PB0

Figure 2-11. Software Feature Jumpers




2.12 Peripheral Expansion ConnectorsThe EVM board contains a group of Peripheral Expansion Connectors used to gain access to the resources of the 56F8323. The following signal groups have expansion connectors:

• PWM Port A• Serial Peripheral Interface Port #0• Serial Peripheral Interface Port #1• Serial Communications Port 0• Serial Communications Port 1• Encoder #0 / Timer Channel A• Timer Channel C• FlexCAN Port• A/D Input Port A• GPIO Port A• GPIO Port B• GPIO Port C• IRQA / RESET / CLOCK

2.12.1 PWM Port A Expansion ConnectorThe PWM port A is attached to this connector. Refer to Table 2-14 for connection information.

Table 2-14. PWM Port A Connector Description

J5


1 PWMA0 / PA0 2 PWMA1 / PA1

3 PWMA2 / PA2 / SS1 4 PWMA3 / PA3 / MISO1

5 PWMA4 / PA4 / MOSI1 6 PWMA5 / PA5 / SCLK1

7 FAULTA0 / PA6 8 FAULTA1 / PA7

9 FAULTA2 / PA8 10 NC

11 ISA0 / PA9 12 ISA1 / PA10

13 ISA2/PA11 14 GND



2.12.2 Serial Peripheral Interface #0 Expansion ConnectorThe Serial Peripheral Interface #0 is an MPIO port attached to this connector. This port can be configured as a Serial Peripheral Interface or as a General Purpose I/O port. Refer to Table 2-15 for connection information.

Table 2-15. SPI #0 Connector Description

J8


1 MOSI0 / PB2 2 MISO0 / PB1 / RXD1

3 SCLK0 / PB3 4 SS0 / PB0 / TXD1

5 GND 6 +3.3V

2.12.3 Serial Peripheral Interface #1 Expansion ConnectorThe Serial Peripheral Interface #1 is an MPIO port attached to this connector. This port can be configured as a Serial Peripheral Interface or as a General Purpose I/O port. Refer to Table 2-16 for the connection information.

Table 2-16. SPI #1 Connector Description

J15


1 MOSI1 / PWMA4 2 MISO1 / PWMA3

3 SCLK1 / PWMA5 4 SS1 / PWMA2

5 GND 6 +3.3V




2.12.4 Serial Communications Port #0 Expansion ConnectorThe Serial Communications Port #0 is an MPIO port attached to the SCI #0 expansion connector. This port can be configured as a Serial Communications Interface or as Timer Port C channels. Refer to Table 2-17 for connection information.

Table 2-17. SCI #0 Connector Description

J21


1 TXD0 / TC0 2 RXD0 / TC1

3 GND 4 +3.3V

5 GND 6 +5.0V

2.12.5 Serial Communications Port #1 Expansion ConnectorThe Serial Communications Port #1 is an MPIO port attached to the SCI #0 expansion connector. This port can be configured as a Serial Communications Interface or as SPI0 signals. Refer to Table 2-18 for connection information.

Table 2-18. SCI #1 Connector Description

J17


1 TXD1 / SS0 2 RXD1 / MISO0

3 GND 4 +3.3V

5 GND 6 +5.0V



2.12.6 Encoder #0 / Quad Timer Channel A Expansion ConnectorThe Encoder #0 / Quad Timer Channel A port is an MPIO port attached to the Timer A expansion connector. This port can be configured as a Quadrature Decoder interface port, as a Quad Timer port, or as GPIO. Refer to Table 2-19 for the signals attached to the connector.

Table 2-19. Timer A Signal Connector Description

J7


1 PHASEA0 / TA0 / PB7 2 PHASEB0 / TA1 / PB6

3 INDEX0 / TA2 / PB5 4 HOME0 / TA3 / PB4

5 GND 6 +3.3V

2.12.7 Timer Channel C Expansion ConnectorThe Timer Channel C port is an MPIO port attached to the Timer C expansion connector. This port can be configured as a Quad Timer Interface, as SCI0 signals, or as GPIO. Refer to Table 2-20 for the signals attached to the connector.

Table 2-20. Timer Channel C Connector Description

J9


1 TC0 / TXD0 / PC6 2 TC1 / RXD0 / TC5

3 GND 4 TC3 / PC4




2.12.8 FlexCAN Expansion ConnectorThe FlexCAN port is an MPIO port attached to the FlexCAN expansion connector. This port can be configured as a FlexCAN Interface or as GPIO. Refer to Table 2-21 for connection information.

Table 2-21. CAN Connector Description

J10


1 CAN_TX / PC3 2 GND

3 CAN_RX / PC2 4 GND

2.12.9 A/D Port A Expansion ConnectorThe 8-channel Analog-to-Digital conversion port A is attached to this connector. Refer to Table 2-22 for connection information. There is an RC network on each of the Analog Port A input signals; see Figure 2-12.

Table 2-22. A/D Port A Connector Description

J6


1 AN0 2 AN1

3 AN2 4 AN3

5 AN4 6 AN5

7 AN6 8 AN7

9 GNDA 10 +VREFH

To Controller Analog Port100 ohm

Analog Input

0.0022µF



Figure 2-12. Typical Analog Input RC Filter

2.12.10 GPIO Port A Expansion ConnectorThe GPIO port A is attached to this connector. Refer to Table 2-23 for connection information.

Table 2-23. GPIO Port A Connector Description

J16


1 PA0 / PWMA0 2 PA1 / PWMA1

3 PA2 / PWMA2 / SS1 4 PA3 / MISO1 / PWMA3

5 PA4 / PWMA4 / MOSI1 6 PA5 / SCLK1 / PWMA5

7 PA6 / FAULTA0 8 PA7 / FAULTA1

9 PA8 / FAULTA2 10 PA9 / ISA0

11 PA10 / ISA1 12 PA11 / ISA2

13 GND 14 +3.3V




2.12.11 GPIO Port B Expansion ConnectorThe GPIO port B is attached to this connector. Refer to Table 2-24 for connection information.

Table 2-24. GPIO Port B Connector Description

J18


1 PB0 / SS0 2 PB1 / MISO0

3 PB2 / MOSI0 4 PB3 / SCLK0

5 PB4 / HOME0 6 PB5 / INDEX0

7 PB6 / PHASEB0 8 PB7 / PHASEA0

9 GND 10 +3.3V

2.12.12 GPIO Port C Expansion ConnectorThe GPIO port C is attached to this connector. Refer to Table 2-25 for connection information.

Table 2-25. GPIO Port C Connector Description

J19


1 PC0 / EXTAL 2 PC1 / XTAL

3 PC2 / CAN_RX 4 PC3 / CAN_TX

5 PC4 / TC3 6 PC5 / TC1

7 PC6 / TC0 8 NC

9 GND 10 +3.3V



2.12.13 IRQA / RESET / CLOCK Expansion ConnectorThe IRQA / RESET / CLOCK signals are attached to this connector. Refer to Table 2-26 for connection information.

Table 2-26. IRQA / RESET / CLOCK Connector Description

J11


1 IRQA 2 RESET

3 EXTAL / PC0 4 XTAL / PC1

9 GND 10 +3.3V

2.13 Test PointsThe 56F8323EVM board has a total of eleven test points:

• Analog Ground (AGND) [TP4]• Four Digital Grounds (GND) [TP1, TP2, TP3 & TP10]• Two +3.3V [TP6 & TP11]• +3.3VA [TP5]• Two +5.0V [TP7 & TP8]• +12V [TP9]

56F8323EVM Schematics, Rev. 2

Freescale Semiconductor Appendix A-1 Preliminary

Appendix A 56F8323EVM Schematics

A A

B B

C C

D D

E E

44

33

22

11

Single trace

to GNDA

Single trace

to GNDA

ON

-CH

IP C

OR

E R

EG

ULA

TO

R1-2

N/C

ENABLE REGULATOR

DISABLE REGULATOR

DS

PO

Des

ign

MC

56F

8323

Pro

cess

or

MC

56F

8323

EV

M.D

SN

1.1

113

Mon

day,

May

12,

200

3A

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Titl

e

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX

: (48

0) 4

13-2

510

FAU

LTA

2

FAU

LTA

1

FAU

LTA

0

VR

EFP

VR

EFM

VR

EFN

AN

A7

TE

MP

_SE

NS

E

VC

AP

3

VC

AP

2

VC

AP

1

VC

AP

4

VC

AP

1

VC

AP

3V

CA

P4

VC

AP

2

OC

R_D

IS

OC

R_D

IS

VD

D_I

O4

VD

D_I

O3

VD

D_I

O2

VD

D_I

O1

VD

D_I

O3

VD

D_I

O2

VD

D_I

O1

VD

D_I

O4

VA

PW

MA

1P

WM

A2

PW

MA

5

ISA

1IS

A0

ISA

2FA

ULT

A0

FAU

LTA

1FA

ULT

A2

PW

MA

0

PW

MA

4P

WM

A3

PH

AS

EA

0

HO

ME

0IN

DE

X0

PH

AS

EB

0

AN

A6

AN

A0

AN

A7

AN

A2

AN

A1

AN

A5

AN

A4

AN

A3

/IRQ

A

EXT

ALXT

AL

/RE

SE

T

TD

IT

DO

TMS

/TR

ST

TC

K

MIS

O0

/SS

0S

CLK

0M

OS

I0

TC

1T

C3

TC

0

CA

N_R

XC

AN

_TX

+3.3

VA

+VR

EFH

+3.3

V_P

LL

VD

Dco

re

+3.3

V

+3.3

V

R15

47K

R16

47K

R17

47K

C5

0.1u

FC

410.

001u

FC

4210

0pF

C8

0.1u

FC

70.

1uF

C6

0.1u

F

JG6

12

R70

0 O

hm

DN

P

R71

0 O

hm

DN

P

R72

0 O

hm

DN

P

R73

0 O

hm

DN

P

C1

2.2u

FC

22.

2uF

C3

2.2u

FC

42.

2uF

JG12 1 2

R74 1K

U1

MC

56F8

323F

G60

12

3 4 7 8 9 10 13 14 15

47 462

16 18 19 26 27 28 29 30 31 32 33 34

64 631 5853 5455 56212522 24 62 61

52 51 50 49

57 23 5 436 20 48 59 11 4417 604542

41

40

39 37 3836 35

IRQ

A

PW

MA

0/P

A0

PW

MA

1/P

A1

PW

MA

2/S

S1/

PA

2P

WM

A3/

MIS

O1/

PA

3P

WM

A4/

MO

SI1

/PA

4P

WM

A5/

SC

LK1/

PA

5

FAU

LTA

0/P

A6

FAU

LTA

1/P

A7

FAU

LTA

2/P

A8

XT

AL/

PC

1E

XT

AL/

PC

0

RE

SE

T

ISA

0/P

A9

ISA

1/P

A10

ISA

2/P

A11

AN

A0

AN

A1

AN

A2

AN

A3

AN

A4

AN

A5

AN

A6

AN

A7

TE

MP

_SE

NS

E

TC

1/R

XD

0/P

C5

TC

3/P

C4

TC

0/T

XD

0/P

C6

TR

ST

TC

K

TM

S

TD

IT

DO

SS

0/T

XD

1/P

B0

SC

LK0/

PB

3

MIS

O0/

RX

D1/

PB

1M

OS

I0/P

B2

CA

N_T

X/P

C3

CA

N_R

X/P

C2

PH

A0/

TA

0/P

B7

PH

B0/

TA

1/P

B6

IND

EX

0/T

A2/

PB

5H

OM

E0/

TA

3/P

B4

VC

AP

1V

CA

P2

VC

AP

3V

CA

P4

VD

D_I

O1

VD

D_I

O2

VD

D_I

O3

VD

D_I

O4

VS

S_I

O1

VS

S_I

O3

VS

S_I

O2

VS

S_I

O4

OC

R_D

IS

VD

AA

_OS

C_P

LL

VD

DA

_AD

C

VR

EFH

VS

SA

_AD

C

VR

EFP

VR

EFL

O

VR

EFM

IDV

RE

FN

R79

0 O

hm

R77

0 O

hm

R78

0 O

hm

R76

0 O

hm

R80

0 O

hm


Appendix A-2 Freescale Semiconductor Preliminary

Figu

re A

-1.

56F

8323

Pro

cess

or

A A

B B

C C

D D

E E

44

33

22

11

12

3

DS1818

IRQA PUSHBUTTON

User

SOFTWARE FEATURE JUMPERS

#0

Jumper

Jumper

#1

User

OSC BYPASS

RESET PUSHBUTTON

OPTIONAL

GPIOB3

GPIOB0

GPIOC0

GPIOC1

DS

PO

Des

ign

RE

SE

T, C

LOC

K &

IRQ

MC

56F

8323

EV

M.D

SN

1.1

213

Mon

day,

May

12,

200

3A

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Titl

e

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX

: (48

0) 4

13-2

510

/PO

R/IR

QA

SC

LK0

/SS

0

/PO

R

EX

TAL

XTAL

+3.3

V

+3.3

V

+3.3

V

+3.3

V

+3.3

V

C9

0.1u

F

R24

10K

S2

JG7

1 2 3

R25

10K

R26

1K R28

1KR27

10K

JG8

1 2 3

Y1

8.00

MH

zR

141M

U2

DS

1818

DN

P

21

3

Vcc

RS

TG

ND

R23

10K

JG2

1 2

JG1

1 2 3

S1


Freescale Semiconductor Appendix A-3Preliminary

Figu

re A

-2.

Res

et, C

lock

& IR

Q

A A

B B

C C

D D

E E

44

33

22

11

RS

-232

SH

UTD

OW

N J

UM

PE

R

1 - 2

N/C

RS-232 ENABLE

RS-232 DISABLE

CONNECTOR

CTS

DSR

DTR

RXD

TXD

RTS

DCD

SCI #1

RS-232

RTS/CTS

DS

PO

Des

ign

RS

-232

AN

D S

CI C

ON

NE

CT

OR

S

MC

56F

8323

EV

M.D

SN

1.1

313

Mon

day,

May

12,

200

3A

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Titl

e

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX

: (48

0) 4

13-2

510

R4I

N

R5I

N

R3I

N

T3I

N

/EN

T3I

N

/EN

R3I

NR

4IN

R5I

N

TXD

TXD

1R

XD

1

RT

S1

CT

S1

CT

S

RT

SR

XD

/SS

0M

ISO

0

+3.3

V

+3.3

V

+3.3

V

R35 1K R36 1KR34 1KR32 1KR30 1K

C32

1.0u

F

C33

1.0u

FC

351.

0uF

C34

1.0u

F

JG4 1 2

R29

1K

1 1 1

1 1

1

JG5

1 32 4

U3 M

AX

3245

EE

AI

271

26

2 2328 14 13 12 19 18 17 16 158765411109

22243 25

20

21

V+

C2+

VC

C

C2-

FOR

CE

ON

C1+

T1I

NT

2IN

T3I

N

R1O

UT

R2O

UT

R3O

UT

R4O

UT

R5O

UT

R5I

NR

4IN

R3I

NR

2IN

R1I

N

T3O

UT

T2O

UT

T1O

UT

FOR

CE

OFF

C1-

V-

GN

D

R2O

UT

B

INV

ALI

D

JG13 1 2

P2

594837261



Figu

re A

-3.

RS-

232

and

SCI C

onne

ctor

s

A A

B B

C C

D D

E E

44

33

22

11

SE

RIA

L D

/A C

ON

NE

CTO

R

Set

to 2

.7V

SP

I0D

AIS

YC

HA

IN

OP

TIO

NA

L

DS

PO

Des

ign

DE

BU

G S

ER

IAL

4-C

HA

NN

EL

D/A

CO

NV

ER

TER

MC

56F

8323

EV

M.D

SN

1.1

413

Mon

day,

May

12,

200

3A

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Titl

e

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX

: (48

0) 4

13-2

510

+Vre

f

D/A

1

D/A

3D

/A2

D/A

0

SC

LK0

MO

SI0

/SS

0

/RE

SE

T

MIS

O0

+3.3

V

+3.3

V

+3.3

VA

+Vre

f

R58

5.1K

DN

P

U5 M

AX

5251

BE

APD

NP

12 3 4 5 6 15 16 17 18 19

20

13

9 12 10 8 7 14 11A

GN

D

FBA

OU

TA

OU

TB

FBB

RE

FAB

RE

FCD

FBC

OU

TC

OU

TD

FBD

VD

D

UP

0

DIN

DO

UT

SC

LK

CS

CL

PD

L

DG

ND

J4 DN

P

1 3 5 7

2 4 6 8

1

R48

1K P

OT

DN

P

JG9

DN

P1 2



Figu

re A

-4.

Deb

ug S

eria

l 4-C

hann

el D

/A C

onve

rter

A A

B B

C C

D D

E E

44

33

22

11

PWM STATE

LEDS

YE

LLO

W L

ED

YE

LLO

W L

ED

GR

EE

N L

ED

GR

EE

N L

ED

GR

EE

N L

ED

YE

LLO

W L

ED

PA0

PA1

PA2

PA3

PA4

PA5

DS

PO

Des

ign

PW

M P

OR

T A

ST

ATE

LE

DS

MC

56F

8323

EV

M.D

SN

1.1

513

Mon

day,

May

12,

200

3A

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Titl

e

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX

: (48

0) 4

13-2

510

PW

MA

4

PW

MA

1

PW

MA

0

PW

MA

5

PW

MA

2

PW

MA

3

+3.3

V

R7

270

R8

270

R9

270

R10 27

0

R11 27

0

U6A

74A

C04

12

U6B

74A

C04

34

U6C

74A

C04

56

U6D

74A

C04

98

U6E

74A

C04

1110

U6F

74A

C04

1312

LED

7

LED

8

LED

9

LED

10

LED

11

LED

12R

12 270



Figu

re A

-5.

PW

M P

ort A

Sta

te L

EDs

A A

B B

C C

D D

E E

44

33

22

11

USER

LEDS

PC3

PC1

PC2

PC0

RE

D L

ED

YE

LLO

W L

ED

GR

EE

N L

ED

RE

D L

ED

PC4

PC5

YE

LLO

W L

ED

GR

EE

N L

ED

DS

PO

Des

ign

US

ER

DE

BU

G L

ED

S

MC

56F

8323

EV

M.D

SN

1.1

613

Mon

day,

May

12,

200

3A

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Titl

e

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX

: (48

0) 4

13-2

510

CA

N_T

X

CA

N_R

X

XTAL

EXT

AL

TC

1

TC

3

+3.3

V

U7B

74A

C04

34

U7C

74A

C04

56

U7D

74A

C04

98

R3

270

R2 27

0

LED

1R

1 270

U7A

74A

C04

12

LED

3

LED

2

LED

4

U7E

74A

C04

1110

U7F

74A

C04

1312

R6

270

LED

6

LED

5

R4

270

R5 27

0



Figu

re A

-6.

Use

r Deb

ug L

EDs

A A

B B

C C

D D

E E

44

33

22

11

PB4/TA3

PB5/TA2

PB6/TA1

SPI #0

PWMA

PB7/TA0

PB0/TXD1

PB1/RXD1

TXD1

RXD1

PA2/SS1

PA4/MOSI1

PA3/MISO1

PA5/SCLK1

QUAD DECODER #0

PA0

PA6

PA8

PA9

PA11

PA1

PA7

PA10

& TIMER CHANNEL A

PB2

PB3

SCI #1

SPI #1

/SS1

MISO1

MOSI1

SCLK1

GPIO PORT A

PA2

PA4

PA3

PA5

PA0

PA6

PA8

PA1

PA7

PA10

PA9

PA11

GPIO PORT B

PB1

PB0

PB2

PB3

PB4

PB6

PB5

PB7

PC3

PC4

IRQ, RESET

SCI #0

A/D PORT A

TXD0

PC2

CAN

PC4

& SCI #0

PC3

PC2

PC0

PC1

PC6/TXD0

PC0

PC5/RXD0

PC6

& GPIO PORT C

PC5

PC1

RXD0

& CLOCK

TIMER CHANNEL C

GPIO PORT C

Spare

Spare

DSP

O D

esig

n

DSP

PO

RT

EXPA

NSI

ON

CO

NN

ECTO

RS

MC

56F8

323E

VM.D

SN1.

17

13M

onda

y, M

ay 1

2, 2

003

B

DSP

Sta

ndar

d Pr

oduc

ts D

ivis

ion

2100

Eas

t Ellio

t Roa

dTe

mpe

, Ariz

ona

8528

4

Title

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:Sh

eet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX:

(480

) 413

-251

0

PWM

A0PW

MA2

PWM

A4

PWM

A1PW

MA3

PWM

A5FA

ULT

A0FA

ULT

A2FA

ULT

A1

ISA0

ISA1

ISA2 M

OSI

0M

ISO

0SC

LK0

/SS0

IND

EX0

HO

ME0

PHAS

EB0

PHAS

EA0

/SS0

MIS

O0

PWM

A4PW

MA3

PWM

A5PW

MA2

PWM

A0PW

MA2

PWM

A4

PWM

A1PW

MA3

PWM

A5FA

ULT

A0FA

ULT

A2FA

ULT

A1

ISA1

ISA0

ISA2

MIS

O0

SCLK

0/S

S0M

OSI

0H

OM

E0PH

ASEB

0IN

DEX

0PH

ASEA

0

TC1

EXTA

L

AN7

TC1

AN3

AN5

/IRQ

AC

AN_R

XTC

0

AN4

TC0

AN2

CAN

_TX

AN6

XTAL

TC3

TC3

AN0

AN1

TC1

CAN

_TX

/RES

ET

TC0

CAN

_RX

EXTA

LXT

AL

+3.3

V+3

.3V

+3.3

V

+3.3

V

+3.3

V+5

.0V

+3.3

V

+5.0

V

+3.3

V

+3.3

V

+3.3

V

+VR

EFH

J5 1 3 5 7 9 11 13

2 4 6 8 10 12 14

J8 1 3 5

2 4 6

J7 1 3 5

2 4 6

1

J15

1 3 5

2 4 6

J16

1 3 5 7 9 11 13

2 4 6 8 10 12 14

J17

1 3 5

2 4 6

J18

1 3 5 7 9

2 4 6 8 10

J6 1 3 5 7 9

2 4 6 8 10

J11

1 3 5

2 4 61

J9 1 32 4

J19

1 3 5 7 9

2 4 6 8 10

J21

1 3 5

2 4 6

J10

1 32 4



Figu

re A

-7.

Por

t Exp

ansi

on C

onne

ctor

s

A A

B B

C C

D D

E E

44

33

22

11

Daughter Peripheral Port Connector

PC6

PC5

PB0/TXD1

PC4

PB0

PB0

GND

GND

GND

GND

GND

GND

GND

GND

TD1

TD0

PB2

PB3

RXD1

TXD1

RXD0

TXD0

Daughter Address/Data Connector

TA2

TA0

TA3

PC5

PC6

TA1

PB1

DS

PO

Des

ign

DA

UG

HTE

R C

AR

D C

ON

NE

CTO

R

MC

56F

8323

EV

M.D

SN

1.1

813

Mon

day,

May

12,

200

3A

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Titl

e

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX

: (48

0) 4

13-2

510

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DA

GN

D

GN

D

GN

DA

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DA

GN

D

GN

D

GN

D

/SS

0

TC

1T

C0

MIS

O0

/IRQ

A

CA

N_T

XC

AN

_RX

TC

0

/SS

0T

C1

MO

SI0

MIS

O0

TC

0

SC

LK0

/SS

0

SC

LK0

MO

SI0

/SS

0

TC

3

TC

0

TC

1

PH

AS

EA

0IN

DE

X0

PH

AS

EB

0H

OM

E0

PW

MA

0P

WM

A2

PW

MA

4

PW

MA

1P

WM

A3

PW

MA

5

FAU

LTA

1FA

ULT

A0

FAU

LTA

2

ISA

2IS

A0

ISA

1

AN

6

AN

0A

N2

AN

4

AN

1

AN

7A

N5

AN

3

/SS

0

MIS

O0

+VR

EFH

+12V

+12V

+VR

EFH

+5.0

V

+3.3

V

+5.0

V

+3.3

V

+3.3

V

+5.0

V+5

.0V

+3.3

V

J2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 5051

5253

5455

5657

5859

60

J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 5051

5253

5455

5657

5859

6061

6263

6465

6667

6869

7071

7273

7475

7677

7879

8081

8283

8485

8687

8889

9091

9293

9495

9697

9899

100



Figu

re A

-8.

Dau

ghte

r Car

d C

onne

ctor

s

A A

B B

C C

D D

E E

44

33

22

11

CAN BUS CONNECTOR

DAISY-CHAIN

CAN BUS CONNECTOR

CAN BUS

TERMINATION

CAN Select

DS

PO

Des

ign

HIG

H-S

PE

ED

CA

N IN

TE

RF

AC

E

MC

56F

8323

EV

M.D

SN

1.1

913

Sat

urda

y, J

une

28, 2

003

A

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Titl

e

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX

: (48

0) 4

13-2

510

CA

NL

BC

AN

HB

CA

NL

BC

AN

H

BC

AN

L

BC

AN

LB

CA

NH

CA

NH

BC

AN

HB

CA

NL

CA

N_T

XC

AN

_RX

+5.0

V

+5.0

V

U8

PC

A82

C25

0T

1 4

23 5 67

8

TX

DR

XD

GN

D

VC

CV

RE

F

CA

NL

CA

NH

SLO

PE

R37

1K

1

J12

1 3 5 7 9

2 4 6 8 10

J13

1 3 5 7 9

2 4 6 8 10

JG10

1 2

R38

120

1/4W

L1

JG15

1 32 4



Figu

re A

-9.

Hig

h-Sp

eed

CA

N In

terf

ace

A A

B B

C C

D D

E E

44

33

22

11

Parallel JTAG Interface

KEY

JTAG Connector

On-Board

Host Target Interface

Disable

POR

T_D

E

POR

T_VC

C

DSP

O D

esig

n

PAR

ALLE

L JT

AG H

OST

TAR

GET

INTE

RFA

CE

AND

JTA

G C

ON

NEC

TOR

MC

56F8

323E

VM.D

SN1.

110

13Fr

iday

, Jun

e 20

, 200

3B

DSP

Sta

ndar

d Pr

oduc

ts D

ivis

ion

2100

Eas

t Ellio

t Roa

dTe

mpe

, Ariz

ona

8528

4

Title

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:Sh

eet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX:

(480

) 413

-251

0

P_R

ESET

/J_T

RST

/J_R

ESET

TDO

P_R

ESET

TMS

TCK

/J_T

RST

POR

T_TD

O

POR

T_TM

S

/PO

RT_

TRST

POR

T_TC

K

POR

T_TD

I

POR

T_C

ON

NEC

T

POR

T_R

ESET

POR

T_ID

ENT

/J_R

ESET

/J_T

RST

/DE

P_D

E

/J_T

RST

PWR

/DE

TDI

PWR

TDO

P_D

E

POR

T_PU

POR

T_C

ON

NEC

T

POR

T_PU

/J_R

ESET

TDI

TDO

TCK

TMS

/RES

ET

/TR

ST

/PO

R

+3.3

V

+3.3

V

+3.3

V

+3.3

V+5

.0V

+3.3

V

+Vse

l

+Vse

l

R47

5.1K

R46

5.1K

J3 135791113

2468101214

R22

47K

R18 47

K

JG3

12

P11 32

1514 164

175

186

197

208

219

2210

2311

2412

2513

R57

51 O

hm

Q1

2N22

22A

U11

A

74AC

00

1 23

U11

C

74AC

00

9 108

U11

B

74AC

00

4 56

U11

D

74AC

00

12 1311

R44 5.1K

R21 47K

R19 47

K

R20 47

K

1

R45

5.1K

1

R42

5.1K

R43

5.1K

R41 5.1K

U9

MC

74H

C24

4DW

18 16 14 12 9 7

5 3

191

2 4 6 8 11 13

15 1720

10

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

2G1G

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

VCC

GN

D

U10

MC

74LC

X244

DW

18 16 14 12 9

7 5 3 1912 4 6 8 11

13 15 17

20

10

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

2G1G1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

VCC

GN

D

R53 0 O

hm

R51 0 O

hmR

52 0 O

hm

R55 0 O

hm

R54 0 O

hm

R56

51 O

hm

JG14

1 2 3

R81 1K R82 1K DN

P



Figu

re A

-10.

Pa

ralle

l JTA

G H

ost T

arge

t Int

erfa

ce a

nd J

TAG

Con

nect

or

A A

B B

C C

D D

E E

44

33

22

11

NOTE: Use a single trace

for GNDA signals to the

common GNDA point.

DS

PO

Des

ign

A/D

INP

UT

FILT

ER

S

MC

56F

8323

EV

M.D

SN

1.1

1113

Mon

day,

May

12,

200

3A

DS

P S

tand

ard

Pro

duct

s D

ivis

ion

2100

Eas

t Elli

ot R

oad

Tem

pe, A

rizon

a 85

284

Titl

e

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:S

heet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX

: (48

0) 4

13-2

510

AN

A7

AN

A0

AN

A1

AN

A2

AN

A3

AN

A4

AN

A5

AN

A6

AN

0

AN

1

AN

2

AN

3

AN

4

AN

5

AN

6

AN

7

C49

0.00

22uF

C51

0.00

22uF

C53

0.00

22uF

C55

0.00

22uF

C50

0.00

22uF

C52

0.00

22uF

C54

0.00

22uF

C56

0.00

22uF

R66

100

R59

100

R61

100

R63

100

R65

100

R60

100

R62

100

R64

100



Figu

re A

-11.

A

/D In

put F

ilter

s

A A

B B

C C

D D

E E

44

33

22

11

EXTERNAL POWER INPUT

7-12V DC/AC

12

3

4

MC33269

3.3V AND 5.0V

REGULATOR

TEST POINT

POWER GOOD LED

NOTE: Remove 0 OHM

resistor to use Analog

GND isolation jumper.

Single trace

to GNDA.

1 2 34

REG113NA3/3K

3.0V REF

REGULATOR

5

+3.0V

+3.3V

+3.3VA

GROUND

ANALOG GROUND

+5.0V

TEST POINT

TEST POINT

GROUND

TEST POINT

GROUND

TEST POINT

TEST POINT

TEST POINT

TEST POINT

+3.3V

+12.0V

TEST POINT

+5.0V

TEST POINT

GROUND

TEST POINT

External

VDDcore

INPUT

NOTE: To use, provide +2.5VDC

on pin-1. Add 0 OHM resistors

for VCAP1, VCAP2, VCAP3 and

VCAP4, and remove OCR_DIS

jumper.

DSP

O D

esig

n

POW

ER S

UPP

LIES

MC

56F8

323E

VM.D

SN1.

112

13M

onda

y, M

ay 1

2, 2

003

B

DSP

Sta

ndar

d Pr

oduc

ts D

ivis

ion

2100

Eas

t Ellio

t Roa

dTe

mpe

, Ariz

ona

8528

4

Title

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:Sh

eet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX:

(480

) 413

-251

0

+3.3

V

+3.3

V

+3.3

VA+3

.3V

VCC

+3.3

VA

+5.0

V

+5.0

V

+5.0

V

+3.3

VA+V

REF

H

+12V

+5.0

V

+VR

EFH

+5.0

V

+12V

+3.3

V+5

.0V

VDD

core

+3.3

V_PL

L

C10

0.1u

F

U12

MC

3326

9DT-

5.0

32 4

1

VIN

VOU

T

VOU

TG

ND

L2

FER

RIT

E BE

AD

L6

FER

RIT

E BE

AD

+C

4547

uF10

VDC

+C

4347

0uF

16VD

C+

C44

47uF

10VD

C

L3

FER

RIT

E BE

AD

TP5

1

TP4

1

TP1

1

TP6

1

TP2

1

TP3

1

D2

FM40

01

P31

3

2

-+

D1

3

1

4

2

C12

0.1u

F+

C47

47uF

10VD

C

U14

MC

3326

9DT-

3.3

32 4

1

VIN

VOU

T

VOU

TG

ND

R13

270 LE

D13

GR

EEN

LED

L5

FER

RIT

E BE

AD

L4

FER

RIT

E BE

AD+

C46

47uF

10VD

C

C11

0.1u

F

U15

REG

113N

A-3/

3K

15 4

23

VIN

VOU

T

NR

GN

D

EN+

C48

10uF

6VD

CC

360.

01uF

JG11

1 2

R68

0 O

hm

U13

MC

3326

9DT-

3.3

32 4

1

VIN

VOU

T

VOU

TG

ND

D4

FM40

01DN

P

D3

FM40

01DN

P

R67

0 O

hmD

NP

TP7

1

TP9

1

TP11

1

TP8

1

TP10

1

R69

0 O

hm

J14 1 2

R75

0 O

hm



Figu

re A

-12.

Po

wer

Sup

plie

s

A A

B B

C C

D D

E E

44

33

22

11

MC56F8323

A/D CONNECTOR

U8

PCA82C250

MAX5251

74AC04

74AC00

MAX3245

74LCX244

74AC04

74HC244

U10

U9

U11

U6

U7

U3

J6

U1

U5

PERIPHERAL CONNECTOR

J1

MEMORY CONNECTOR

J2

DSP

O D

esig

n

BYPA

SS C

APAC

ITO

RS

MC

56F8

323E

VM.D

SN1.

113

13Fr

iday

, Jun

e 20

, 200

3B

DSP

Sta

ndar

d Pr

oduc

ts D

ivis

ion

2100

Eas

t Ellio

t Roa

dTe

mpe

, Ariz

ona

8528

4

Title

Doc

umen

t

Dat

e:

Siz

e

Des

igne

r:Sh

eet

of

Rev

.N

umbe

r

(480

) 413

-509

0

FAX:

(480

) 413

-251

0

+5.0

V+3

.3V

+Vre

f+3

.3V

+3.3

VA

+3.3

V+3

.3V

+3.3

V

+3.3

V

+3.3

V+V

sel

+5.0

V+3

.3V

+12V

+VR

EFH

+5.0

V+3

.3V

+3.3

V+V

REF

H

C24

0.1u

FC

190.

1uF

C20

0.1u

FC

210.

1uF

C23

0.1u

F

C38

0.01

uF

C31

0.1u

F

C22

0.1u

F

C37

0.01

uFC

170.

1uF

C16

0.1u

FC

150.

1uF

C14

0.1u

FC

130.

1uF

C25

0.1u

F

C39

0.01

uFC

180.

1uF

C26

0.1u

FC

400.

01uF

C27

0.1u

FC

280.

1uF

C29

0.1u

FC

300.

1uF

C57

0.1u

FC

580.

1uF

C59

0.01

uF



Figu

re A

-13.

B

ypas

s C

apac

itors

56F8323EVM Bill of Material, Rev. 2

Freescale Semiconductor Appendix B-1 Preliminary

Appendix B 56F8323EVM Bill of Material

Qty Description Ref. Designators Vendor Part #

Integrated Circuits

1 MC56F8323 U1 Freescale Semiconductor, MC56F8323VFB60

0 Power-On Reset U2 (Optional) Dallas Semiconductor, DS1818

1 RS-232 Transceiver U3 Maxim, MAX3245EEAI

0 SPI 4-Channel D/A U5 (Optional) Maxim, MAX5251BEAP

2 74AC04 U6, U7 ON Semiconductor, MC74AC04AD

1 CAN Transceiver U8 Philips Semiconductor, PCA82C250T

1 74HC244 U9 ON Semiconductor, MC74LHC44AADW

1 74LCX244 U10 ON Semiconductor, MC74LCX244ADW

1 74AC00 U11 Fairchild, 74AC00SC

1 +5.0V Voltage Regulator U12 ON Semiconductor, MC33269DT-5

2 +3.3V Voltage Regulator U13, U14 ON Semiconductor, MC33269DT-3.3

1 +3.0V Voltage Regulator U15 Burr-Brown, REG113NA-3/3K

Resistors

13 270 Ω R1–R13 SMEC, RC73L2A271OHMJT

1 1M Ω R14 SMEC, RC73L2A105OHMJT

8 47K Ω R15–R22 SMEC, RC73L2A473OHMJT

4 10K Ω R23, R24, R25, R27 SMEC, RC73L2A103OHMJT

11 1K Ω R26, R28–R30, R32, R34–R37, R74, R81

SMEC, RC73L2A103OHMJT


Appendix B-2 Freescale Semiconductor Preliminary

Resistors (Continued)

1 120 Ω, 1/4W R38 YAGEO, CFR 120QBK

7 5.1K Ω R41–R47 SMEC, RC73L2A512OHMJT

13 0 Ω R51–R55, R68, R69, R75–R80 SMEC, RC73JP2A

2 51 Ω R56, R57 SMEC, RC73L2A51OHMJT

0 5.1K Ω R58 (Optional) SMEC, RC73L2A512OHMJT

8 100 Ω R59–R66 SMEC, RC73L2A101OHMJT

0 0 Ω R67, R70–R73 (Optional) SMEC, RC73JP2A

0 1K Ω R82 (Optional) SMEC, RC73L2A103OHMJT

Potentioneters

0 1K Ω R48 (Optional) BC/MEPCOPAL, ST4B102CT

Inductors

1 CAN Bus Filter L1 EPCOS, B82790-S0513-N201

5 1.0mH FERRITE BEAD L2–L6 Panasonic, EXC-ELSA35V

LEDs

2 Red LED LED1, LED4 Hewlett-Packard, HSMS-C650

5 Yellow LED LED2, LED5, LED7, LED9, LED11

Hewlett-Packard, HSMY-C650

6 Green LED LED3, LED6, LED8, LED10, LED12, LED13

Hewlett-Packard, HSMG-C650

Diode

1 +50V 1A BRIDGE RECT D1 DIODES, DF02S

1 S2B-FM401 D2 Vishay, DL4001DICT

0 S2B-FM401 D3 & D4 (Optional) Vishay, DL4001DICT

Capacitors

4 2.2µF, +25V DC(Low ESR)

C1–C4 TAIYO YUDEN, CELMK212BJ225MG-T

29 0.1µF C5–C31, C57, C58 SMEC, MCCE104K2NR-T1

4 1.0µF, +25V DC C32–C35 SMEC, MCCE105K3NR-T1


56F8323EVM Bill of Material, Rev. 2

Freescale Semiconductor Appendix B-3Preliminary

Capacitors (Continued)

6 0.01µF C36–C40, C59 SMEC, MCCE103K2NR-T1

1 0.001µF C41 SMEC, MCCE102K2NR-T1

1 100pF C42 SMEC, MCCE101K2NR-T1

1 470µF, +16V DC C43 ELMA, RV-16V471MH10R

4 47µF, +16V DC C44–C47 ELMA, RV2-16V470M-R

1 10µF, +10V DC C48 KEMET, T494B106M010AS

8 0.0022µF C49–C56 SMEC, MCCE222K2NR-T1

Jumpers

4 3 × 1 Bergstick JG1, JG7, JG8, JG14 SAMTEC, TSW-103-07-S-S

8 1 × 2 Bergstick JG2, JG3, JG4, JG6, JG10, JG11, JG12, JG13

SAMTEC, TSW-102-07-S-S

2 2 × 2 Bergstick JG5, JG15 SAMTEC, TSW-102-07-S-D

0 1 × 2 Bergstick JG9 (Optional) SAMTEC, TSW-102-07-S-S

Test Points

4 GND Test Point TP1–TP3, TP10 KEYSTONE, 5001 (BLACK)

1 GNDA Test Point TP4 KEYSTONE, 5002 (WHITE)

1 +3.3VA Test Point TP5 KEYSTONE, 5004 (YELLOW)

2 +3.3V Test Point TP6, TP11 KEYSTONE, 5000 (RED)

1 +5.0V & +12V Test Point TP7, TP8, TP9 KEYSTONE, 5003 (ORANGE)

0 1 × 1 Bergstick T15, T16 (Optional) Samtec, TSW-101-06-S-S

Crystals

1 8.00MHz Crystal Y1 CTS, ATS08ASM-T

Connectors

1 DB25M Connector P1 AMPHENOL, 617-C025P-AJ121

1 DE9S Connector P2 AMPHENOL, 617-C009S-AJ120

1 2.1mm coaxPower Connector

P3 Switchcraft, RAPC-722



Appendix B-4 Freescale Semiconductor Preliminary

Connectors (Continued)

1 Peripheral Daughter Card Connector

J1 HRS, FX6-100P-0.8SV2

1 Memory Bus Daughter Card Connector

J2 HRS, FX6-60P-0.8SV2

1 7x2 JTAG Header J3 SAMTEC, TSW-107-07-S-D

0 4x2 Header J4 (Optional) SAMTEC, TSW-104-07-S-D

5 5x2 Header J6, J12, J13, J18, J19 SAMTEC, TSW-105-07-S-D

2 7x2 Header J5, J16 SAMTEC, TSW-107-07-S-D

5 3x2 Header J7, J8, J11, J15, J17, J21 SAMTEC, TSW-103-07-S-D

2 2x2 Header J9, J10 SAMTEC, TSW-102-07-S-D

1 1x2 Header J14 SAMTEC, TSW-102-07-S-S

Switches

2 SPST Pushbutton S1–S2 Panasonic, EVQ-PAD05R

Transistors

1 2N2222A Q1 ZETEX, FMMT2222ACT

Miscellaneous

13 Shunt SH1–SH13 Samtec, SNT-100-BL-T

4 Rubber Feet RF1–RF4 3M, SJ5018BLKC


INDEX

Index, Rev. 2

Freescale Semiconductor Index - i Preliminary

Numerics1.2 Amp power supply 2-124-Channel 10-bit Serial D/A 2-256F8300 Peripheral User Manual 2-356F8323 Preface-ix56F8323 Technical Data Sheet 2-38.00MHz crystal oscillator 2-1

AA/D Preface-ixADC Preface-ixAnalog-to-Digital

A/D Preface-ixAnalog-to-Digital Converter

ADC Preface-ix

CCAN Preface-ix

bus termination 2-1bypass 2-1interface 2-1

CAN in AutomationCiA Preface-ix

CAN physical layer peripheral 2-2CiA Preface-ixClear To Send

CTS Preface-ixController Area Network

CAN Preface-ixCTS Preface-ix

DD/A Preface-ixDaughter Card Expansion

interface 2-1Debugging 2-6Digital-to-Analog

D/A Preface-ixDSP56800E Reference Manual 2-3

EEnhanced On-Chip Emulation

EOnCE Preface-ixEOnCE Preface-ixEvaluation Module

EVM Preface-ixEVM Preface-ixExternal oscillator frequency input 2-1

FFlexCAN Preface-ixFlexCAN Interface Module

FlexCAN Preface-ix

GGeneral Purpose Input and Output

GPIO Preface-ixGPIO Preface-ix

HHost Parallel Interface Connector 2-8Host Target Interface 2-8

IIC Preface-ixIntegrated Circuit

IC Preface-ix

JJoint Test Action Group

JTAG Preface-ixJTAG Preface-ix, 2-1JTAG/Enhanced OnCE (EOnCE) 1-1Jumper Group 1-4

JG1 1-4JG10 1-4JG11 1-4JG12 1-4JG13 1-4JG14 1-4JG15 1-4JG2 1-4JG3 1-4JG4 1-4JG5 1-4JG6 1-4JG7 1-4JG8 1-4JG9 1-4


Index-ii Freescale Semiconductor Preliminary

LLED Preface-ixLight Emitting Diode

LED Preface-ixLow-profile Quad Flat Package

LQFP Preface-ixLQFP Preface-ix

MMPIO Preface-ixMulti Purpose Input and Output

MPIO Preface-ix

OOn-board power regulation 2-2OnCE Preface-xOn-Chip Emulation

OnCE Preface-x

PParallel JTAG Host Target Interface 2-1PCB Preface-xperipheral port signals 2-14Phase Locked Loop

PLL Preface-xPLL Preface-xPrinted Circuit Board

PCB Preface-xPulse Width Modulation

PWM Preface-xPWM Preface-xPWMA-compatible peripheral 2-2

QQuadDec Preface-xQuadrature Decoder

interface port 2-26QuadDec Preface-x

RR/C Preface-xreal-time debugging 2-6Request To Send

RTS Preface-xResistor/Capacitor Network

R/C Preface-xRS-232 2-1

level converter 2-4schematic diagram 2-4

RTS Preface-x

SSCI Preface-xSCI/MPIO-compatible peripheral 2-2Serial Communications Interface

SCI Preface-xSerial Peripheral Interface

SPI Preface-xSPI Preface-xSPI/MPIO-compatible peripheral 2-2SRAM Preface-xStatic Random Access Memory

SRAM Preface-x

TTimer-compatible peripheral 2-2

UUART Preface-xUniversal Asynchronous Receiver/Transmitter

UART Preface-x

WWait State

WS Preface-xWS Preface-x

How to Reach Us:

Home Page:www.freescale.com

E-mail:[email protected]

USA/Europe or Locations Not Listed:Freescale SemiconductorTechnical Information Center, CH3701300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or [email protected]

Europe, Middle East, and Africa:Freescale Halbleiter Deutschland GmbHTechnical Information CenterSchatzbogen 781829 Muenchen, Germany+44 1296 380 456 (English)+46 8 52200080 (English)+49 89 92103 559 (German)+33 1 69 35 48 48 (French)[email protected]

Japan:Freescale Semiconductor Japan Ltd. HeadquartersARCO Tower 15F1-8-1, Shimo-Meguro, Meguro-ku,Tokyo 153-0064, Japan0120 191014 or +81 3 5437 [email protected]

Asia/Pacific:Freescale Semiconductor Hong Kong Ltd.Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 [email protected]

For Literature Requests Only:Freescale Semiconductor Literature Distribution CenterP.O. Box 5405Denver, Colorado 802171-800-441-2447 or 303-675-2140Fax: [email protected]

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST.© Freescale Semiconductor, Inc. 2005. All rights reserved.

MC56F8323EVMUMRev. 207/2005

Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

56f8323 - nxp

Documents