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AAnnddeeSShhaappee™™

AAGG110011PP

S

Document Number：DS0001-10

Issued：Dec. 2007

Copyright© 2007 Andes Technology Corporation.

All rights reserved

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Revision History Revision Number

Revision Date

Author Revised Chapters/Sections

Description

V1.0 12/18/2007 James 1 Introduction, 7 DMA Controller, 9 Static Memory Controller (SMC), 10 SDRAM Controller (SDRAMC), 15 AHB to APB Bridge (APB Bridge), 17 I2C Bus Interface Controller, 19 Timer, 20 Real Time Clock (RTC), 21 SD Memory Card Host Controller (SDC), 22 CompactFlash Host Interface Controller (CFC), 24 Synchronous Serial Port Controller (SSP/I2S/AC97)

Removed obsoleted contents

V0.4 12/5/2007 James Front page, insertion pages

First release

V0.3 07-27-2007 Arthur 1.2.4.5/4.6.2.12 1.2.4.5 fix typo

4.6.2.12 fix pll1frange description and modify pll1ns description

V0.2 04-17-2007 Wilson 6.1 /6.4.2.2 6.1 general description add Decoder and Multiplexer label

6.4.2.2 AHB provides 7 Request/Grant signal pairs

V0.1 04-02-2007 Wilson First draft

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Table of Contents 1 Introduction................................................................................................................................................................... 1

Features ....................................................................................................................................................................... 1 Block Diagram .............................................................................................................................................................. 3

1.1.1 Peripheral Components ............................................................................................................................ 3 1.1.2 System Bus Components ......................................................................................................................... 3

1.1.2.1 N1213 .............................................................................................................................................. 3 1.1.2.2 AHB Controller (AHBC) ................................................................................................................... 4 1.1.2.3 SDRAM Controller (SDRAMC) ........................................................................................................ 4 1.1.2.4 Static Memory Controller (SMC)...................................................................................................... 4 1.1.2.5 LCD Controller (LCDC).................................................................................................................... 5 1.1.2.6 DMA Controller (DMAC) .................................................................................................................. 6 1.1.2.7 USB 2.0 Device ............................................................................................................................... 6 1.1.2.8 Ethernet MAC 10 / 100 .................................................................................................................... 7 1.1.2.9 AHB to APB Bridge (APB Bridge).................................................................................................... 7

1.1.3 Core APB.................................................................................................................................................. 7 1.1.3.1 Timer................................................................................................................................................ 7 1.1.3.2 Watch Dog Timer (WDT) ................................................................................................................. 7 1.1.3.3 Real Time Controller (RTC)............................................................................................................. 8 1.1.3.4 Interrupt Controller (INTC)............................................................................................................... 8 1.1.3.5 GPIO................................................................................................................................................ 8 1.1.3.6 Pulse Width Modulator (PWM) ........................................................................................................ 9 1.1.3.7 I²C .................................................................................................................................................... 9 1.1.3.8 Clock/PLL ........................................................................................................................................ 9 1.1.3.9 Power Management Unit ................................................................................................................. 9

1.1.4 DMA APB................................................................................................................................................ 10 1.1.4.1 Synchronous Serial Port Controller (SSPC).................................................................................. 10 1.1.4.2 I²S / AC97 Controller (I²S / AC97C)............................................................................................... 10 1.1.4.3 Compact Flash Controller (CFC) ................................................................................................... 11 1.1.4.4 Multimedia Card and Secure Digital Host Controller (MMC / SDC) .............................................. 11 1.1.4.5 UART ............................................................................................................................................. 11

1.1.5 Extended AHB Connection..................................................................................................................... 12 System Architecture ................................................................................................................................................... 12

1.1.6 System AHB Bus .................................................................................................................................... 12 1.1.7 DMA AHB Bus ........................................................................................................................................ 12 1.1.8 System APB Bus .................................................................................................................................... 12

Operating Voltage ...................................................................................................................................................... 12 Package Types........................................................................................................................................................... 12

2 Signal Descriptions and Pin Assignments.................................................................................................................. 13

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Signal Descriptions..................................................................................................................................................... 13 BGA Pin Assignments ................................................................................................................................................ 19

3 Memory Map .............................................................................................................................................................. 21 Memory Map .............................................................................................................................................................. 21 Internal Registers ....................................................................................................................................................... 23

4 Power Management Unit............................................................................................................................................ 39 General Descriptions.................................................................................................................................................. 39 Features ..................................................................................................................................................................... 39 Block Diagram ............................................................................................................................................................ 40 Clock Manager ........................................................................................................................................................... 40

4.1.1 Low Frequency Crystal Input .................................................................................................................. 41 4.1.2 High Frequency Oscillator Input ............................................................................................................. 41 4.1.3 Core Phase Locked Loop (PLL1) ........................................................................................................... 42 4.1.4 150.0 MHZ Peripheral Phase Locked Loop (PLL3)................................................................................ 43 4.1.5 Clock Gating ........................................................................................................................................... 43

Resets and Power Modes .......................................................................................................................................... 43 4.1.6 Power-On Reset ..................................................................................................................................... 44 4.1.7 Hardware Reset...................................................................................................................................... 45 4.1.8 Watchdog Reset ..................................................................................................................................... 46 4.1.9 Normal Mode .......................................................................................................................................... 48 4.1.10 Frequency Scaling Mode........................................................................................................................ 48 4.1.11 Frequency Change Sequence (FCS) ..................................................................................................... 48 4.1.12 Sleep Mode............................................................................................................................................. 49 4.1.13 Power Management................................................................................................................................ 52

Programming Model ................................................................................................................................................... 53 4.1.14 Summary of the Clocks and Power Manager Registers......................................................................... 53 4.1.15 Register Descriptions.............................................................................................................................. 55

4.1.15.1 ID Number 0 Register (Offset == 0x00)......................................................................................... 55 4.1.15.2 Frequency Scaling Status Register (FSSR) (Offset == 0x04)....................................................... 56 4.1.15.3 OSC Control Register (Offset == 0x08)......................................................................................... 58 4.1.15.4 Power Mode Register (Offset == 0x0C) ........................................................................................ 58 4.1.15.5 Power Manager Control Register (Offset == 0x10) ....................................................................... 60 4.1.15.6 Power Manager Edge Detect Register (Offset == 0x14)............................................................... 60 4.1.15.7 Power Manager Edge Detect Status Register (Offset == 0x18) ................................................... 61 4.1.15.8 Power Manager Status Register (Offset == 0x20) ........................................................................ 61 4.1.15.9 Power Manager GPIO Sleep State Register (Offset == 0x24)...................................................... 63 4.1.15.10 Multi-Function Port Setting Register (Offset == 0x28)................................................................... 63 4.1.15.11 Misc (Offset == 0x2C).................................................................................................................... 65 4.1.15.12 PLL/DLL Control Register 0 (Offset == 0x30) ............................................................................... 65 4.1.15.13 PLL/DLL Control Register 1 (Offset == 0x34) ............................................................................... 67 4.1.15.14 AHB Module Clock Off Control Register (Offset == 0x38) ............................................................ 67 4.1.15.15 APB Module Clock Off Control Register (Offset == 0x3C)............................................................ 68

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4.1.15.16 Driving Capability and Slew Rate Control Register 0 (Offset == 0x40)......................................... 70 4.1.15.17 Driving Capability and Slew Rate Control Register 1 (Offset == 0x44)......................................... 70 4.1.15.18 Driving Capability and Slew Rate Control Register 2 (Offset == 0x48)......................................... 72 4.1.15.19 SDRAM Signal Hold Time Control (Offset == 0x4C)..................................................................... 73 4.1.15.20 Power Manager Scratch Pad Register 0 ~ 15 (Offset == 0x50 ~ 0x8C) ....................................... 74 4.1.15.21 AHB DMA and APB DMA Routing Control.................................................................................... 74 4.1.15.22 AHB DMA REQ/ACK Connection Configuration Status (Offset == 0x90)..................................... 75 4.1.15.23 Jumper Setting Status (Offset == 0x9C) ....................................................................................... 77 4.1.15.24 CFC REQ/ACK Connection Configuration (Offset == 0xA0)......................................................... 79 4.1.15.25 SSP1 REQ/ACK Connection Configuration (Offset == 0xA4)....................................................... 79 4.1.15.26 UART1 TX REQ/ACK Connection Configuration (Offset == 0xA8)............................................... 79 4.1.15.27 UART1 RX REQ/ACK Connection Configuration (Offset == 0xAC).............................................. 79 4.1.15.28 UART2 TX REQ/ACK Connection Configuration (Offset == 0xB0)............................................... 80 4.1.15.29 UART2 RX REQ/ACK Connection Configuration (Offset == 0xB4) .............................................. 80 4.1.15.30 SDC REQ/ACK Connection Configuration (Offset == 0xB8) ........................................................ 81 4.1.15.31 AC97/I2S REQ/ACK Connection Configuration (Offset == 0xBC) ................................................ 81 4.1.15.32 USB2.0 Device REQ/ACK Connection Configuration (Offset == 0xC8) ....................................... 81 4.1.15.33 External Device0 REQ/ACK Connection Configuration (Offset == 0xD4) .................................... 82 4.1.15.34 External Device1 REQ/ACK Connection Configuration (Offset == 0xD8) .................................... 82

5 N1213......................................................................................................................................................................... 84 General Descriptions.................................................................................................................................................. 84 Block Diagram ............................................................................................................................................................ 84

5.1.1 N12 Execution core ................................................................................................................................ 85 5.1.2 Dynamic branch prediction ..................................................................................................................... 85 5.1.3 Instruction Cache (ICache) ..................................................................................................................... 85 5.1.4 Data Cache (DCache) ............................................................................................................................ 85 5.1.5 Memory Management Unit (MMU) ......................................................................................................... 86 5.1.6 Local memory ......................................................................................................................................... 86 5.1.7 Bus Interface Unit (BIU).......................................................................................................................... 86 5.1.8 ICE.......................................................................................................................................................... 87 5.1.9 Power Saving Control Unit...................................................................................................................... 87

6 AHB Controller ........................................................................................................................................................... 88 General Description.................................................................................................................................................... 88 Features ..................................................................................................................................................................... 88 Block Diagram ............................................................................................................................................................ 89

6.1.1 Arbiter ..................................................................................................................................................... 89 6.1.2 Decoder .................................................................................................................................................. 90 6.1.3 Multiplexer .............................................................................................................................................. 90

Programming Model ................................................................................................................................................... 90 6.1.4 Summary of the AHB Controller Registers ............................................................................................. 90 6.1.5 Register Descriptions.............................................................................................................................. 91

6.1.5.1 AHB Slave n Base/Size Register (Offset == 0x00 ~ 0x58) ........................................................... 91 6.1.5.2 Priority Control Register (Offset == 0x80) ..................................................................................... 91

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6.1.5.3 Transfer Control Register (Offset == 0x84) ................................................................................... 92 6.1.5.4 Interrupt Control Register (Offset == 0x88) ................................................................................... 93

7 DMA Controller........................................................................................................................................................... 94 8 Ethernet MAC 10/100 Controller ................................................................................................................................ 95

General Description.................................................................................................................................................... 95 Features ..................................................................................................................................................................... 95 Block Diagram ............................................................................................................................................................ 96 Functional Block Description...................................................................................................................................... 96

8.1.1 AHB_MASTER ....................................................................................................................................... 96 8.1.2 AHB_SLAVE........................................................................................................................................... 98 8.1.3 DMA_ARBITER ...................................................................................................................................... 98 8.1.4 TXDMA ................................................................................................................................................... 98 8.1.5 RXDMA................................................................................................................................................... 99 8.1.6 TXMAC ................................................................................................................................................... 99 8.1.7 RXMAC................................................................................................................................................. 100 8.1.8 REGIST................................................................................................................................................. 101 8.1.9 PWR_MANAGE.................................................................................................................................... 101

Function Descriptions............................................................................................................................................... 103 8.1.10 Half-Duplex (CSMA/CD Access Protocol) ............................................................................................ 103 8.1.11 Full-Duplex Ethernet ............................................................................................................................. 104 8.1.12 Loop Back............................................................................................................................................. 104 8.1.13 Transmit Descriptors and Data Buffers ................................................................................................ 106 8.1.14 Receive Descriptors and Data Buffers ................................................................................................. 109 8.1.15 Transmitting Packets ............................................................................................................................ 111 8.1.16 Receiving Packets ................................................................................................................................ 111 8.1.17 Ethernet Address Filtering .................................................................................................................... 111 8.1.18 DMA Arbitration Scheme ...................................................................................................................... 112 8.1.19 Flow Control.......................................................................................................................................... 114

Programming Model ................................................................................................................................................. 114 8.1.20 Summary of the MAC Controller Registers .......................................................................................... 114 8.1.21 Register Descriptions............................................................................................................................ 116

8.1.21.1 Interrupt Status Register (Offset == 0x00) .................................................................................. 116 8.1.21.2 Interrupt Mask Register (Offset == 0x04) .................................................................................... 116 8.1.21.3 MAC Most Significant Address Register (Offset == 0x08) .......................................................... 117 8.1.21.4 MAC Least Significant Address Register (Offset == 0x0C)......................................................... 117 8.1.21.5 Multicast Address Hash Table 0 Register (Offset == 0x10) ........................................................ 117 8.1.21.6 Multicast Address Hash Table 1 Register (Offset == 0x14) ........................................................ 117 8.1.21.7 Transmit Poll Demand Register (Offset == 0x18) ....................................................................... 118 8.1.21.8 Receive Poll Demand Register (Offset == 0x1C)........................................................................ 118 8.1.21.9 Transmit Ring Base Address Register (Offset == 0x20) ............................................................. 118 8.1.21.10 Receive Ring Base Address Register (Offset == 0x24) .............................................................. 118 8.1.21.11 Interrupt Timer Control Register (Offset == 0x28)....................................................................... 119

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8.1.21.12 Automatic Polling Timer Control Register (Offset == 0x2C)........................................................ 122 8.1.21.13 DMA Burst Length and Arbitration Control Register (Offset == 0x30) ........................................ 123 8.1.21.14 MAC Control Register (Offset == 0x88) ...................................................................................... 126 8.1.21.15 MAC Status Register (Offset == 0x8C) ....................................................................................... 126 8.1.21.16 PHY Control Register (Offset == 0x90) ....................................................................................... 127 8.1.21.17 PHY Write Data Register (Offset == 0x94).................................................................................. 127 8.1.21.18 Flow Control Register (Offset == 0x98)....................................................................................... 128 8.1.21.19 Back Pressure Register (Offset == 0x9C) ................................................................................... 128 8.1.21.20 Test Seed Register (Offset == 0xC4) .......................................................................................... 129 8.1.21.21 DMA/FIFO State Register (Offset == 0xC8)................................................................................ 129 8.1.21.22 Test Mode Register (Offset == 0xCC)......................................................................................... 130 8.1.21.23 TX_MCOL and TX_SCOL Counter Register (Offset == 0xD4) ................................................... 130 8.1.21.24 RPF and AEP Counter Register (Offset == 0xD8) ...................................................................... 130 8.1.21.25 XM and PG Counter Register (Offset == 0xDC) ......................................................................... 131 8.1.21.26 RUNT_CNT and TLCC Counter Register (Offset == 0xE0)........................................................ 131 8.1.21.27 CRCER_CNT and FTL_CNT Counter Register (Offset == 0xE4)............................................... 131 8.1.21.28 RLC and RCC Counter Register (Offset == 0xE8)...................................................................... 131 8.1.21.29 BROC Counter Register (Offset == 0xEC).................................................................................. 132 8.1.21.30 MULCA Counter Register (Offset == 0xF0) ................................................................................ 132 8.1.21.31 RP Counter Register (Offset == 0xF4) ........................................................................................ 132 8.1.21.32 XP Counter Register (Offset == 0xF8) ........................................................................................ 132

Programming Guide ................................................................................................................................................. 132 8.1.22 Frame Transmitting Procedure............................................................................................................. 132 8.1.23 Frame Receiving Procedure................................................................................................................. 134

9 Static Memory Controller (SMC) .............................................................................................................................. 135 10 SDRAM Controller (SDRAMC)................................................................................................................................. 136 11 LCD Controller (LCDC) ............................................................................................................................................ 137

Description ............................................................................................................................................................... 137 Features ................................................................................................................................................................... 137 Design Block Diagram.............................................................................................................................................. 139 Application Block Diagram ....................................................................................................................................... 139 Architecture Overview .............................................................................................................................................. 140

11.1.1 AHB Slave Interface ............................................................................................................................. 140 11.1.2 AHB Master Interface ........................................................................................................................... 140 11.1.3 FIFO Controllers and FIFOs ................................................................................................................. 140 11.1.4 Pixel Data Unpack ................................................................................................................................ 140 11.1.5 Data Mode ............................................................................................................................................ 144

11.1.5.1 Raw RGB Mode........................................................................................................................... 144 11.1.5.2 YCbCr422 Mode.......................................................................................................................... 144 11.1.5.3 YCbCr420 Mode.......................................................................................................................... 145 11.1.5.4 RGB Palette Mode....................................................................................................................... 145

11.1.6 On-Screen Display (OSD) .................................................................................................................... 146 11.1.6.1 Font Based Architecture .............................................................................................................. 146

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11.1.6.2 Attribute Description .................................................................................................................... 148 11.1.6.3 OSD Window Control .................................................................................................................. 148

11.1.7 TFT Panel Interface .............................................................................................................................. 149 11.1.8 Interrupt Controller................................................................................................................................ 149

Programming Model ................................................................................................................................................. 150 11.1.9 Summary of FTLCDC100 Control Registers ........................................................................................ 150 11.1.10 Register Description ............................................................................................................................. 150

11.1.10.1 LCD Horizontal Timing Control (Offset == 0x00)......................................................................... 150 11.1.10.2 LCD Vertical Timing Control (Offset == 0x04)............................................................................. 151 11.1.10.3 LCD Clock and Signal Polarity Control (Offset == 0x08) ............................................................ 152 11.1.10.4 LCD Panel Frame Base Address (Offset == 0x10) ..................................................................... 152 11.1.10.5 LCD Interrupt Enable Mask (Offset == 0x18) .............................................................................. 154 11.1.10.6 LCD Panel Pixel Parameters (Offset == 0x1C) ........................................................................... 154 11.1.10.7 LCD Interrupt Status Clear (Offset == 0x20) ............................................................................... 155 11.1.10.8 LCD Interrupt Status (Offset == 0x24)......................................................................................... 156 11.1.10.9 OSD Scaling and Dimension Control (Offset == 0x34) ............................................................... 156 11.1.10.10 OSD Position Control (Offset == 0x38) ............................................................................... 157 11.1.10.11 OSD Foreground Color Control (Offset == 0x3C)............................................................... 157 11.1.10.12 OSD Background Color Control (Offset == 0x40)............................................................... 157 11.1.10.13 GPI/GPO Control (Offset == 0x44) ..................................................................................... 158 11.1.10.14 LCD Palette RAM Accessing Port (Offset == 0x200 ~ 0x3FC)........................................... 158 11.1.10.15 OSD Font Database Write Accessing Port (Offset == 0x8000 ~ 0xBFFC)......................... 160 11.1.10.16 OSD Window Attribute Write Accessing Port (Offset == 0xC000 ~ 0xC7FC)..................... 160

12 USB 2.0 Device Controller ....................................................................................................................................... 162 General Description.................................................................................................................................................. 162 Features ................................................................................................................................................................... 162 Block Diagram .......................................................................................................................................................... 163 Architecture Overview .............................................................................................................................................. 163

12.1.1 Parallel Interface Engine (PIE) ............................................................................................................. 164 12.1.2 Control Transfer FIFO (CXF)................................................................................................................ 165 12.1.3 Programmable Memory (PAM)............................................................................................................. 165 12.1.4 Ping-Pong Mechanism of PAM FIFO ................................................................................................... 166 12.1.5 Register Files (RGF)............................................................................................................................. 167 12.1.6 Power Management and Speed Emulation (PWE) .............................................................................. 168 12.1.7 AHB SPLIT-Capable Slave (HBS)........................................................................................................ 169 12.1.8 AHB Buffer (HBF) ................................................................................................................................. 169 12.1.9 AHB Buffer Controller (BFC)................................................................................................................. 171

USB Reset and Power Saving Mode ....................................................................................................................... 171 12.1.10 USB Reset ............................................................................................................................................ 171 12.1.11 Power Saving Mode.............................................................................................................................. 172

Programming Model ................................................................................................................................................. 176 12.1.12 Summary of the FUSB220 Registers ................................................................................................... 176

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12.1.13 Register Description ............................................................................................................................. 181 12.1.13.1 Main Control Register (Offset == 0x00)....................................................................................... 182 12.1.13.2 Device Address Register (Offset == 0x01).................................................................................. 184 12.1.13.3 Test Register (Offset == 0x02) .................................................................................................... 184 12.1.13.4 SOF Frame Number Register Byte 0 (Offset == 0x04) ............................................................... 185 12.1.13.5 SOF Frame Number Register Byte 1 (Offset == 0x05) ............................................................... 186 12.1.13.6 SOF Mask Timer Register Byte 0 (Offset == 0x06)..................................................................... 186 12.1.13.7 SOF Mask Timer Register Byte 1 (Offset == 0x07)..................................................................... 186 12.1.13.8 PHY Test Mode Selector Register (Offset == 0x08) ................................................................... 187 12.1.13.9 Vendor Specific IO Control Register (Offset == 0x09) ................................................................ 187 12.1.13.10 Vendor Specific IO Status Register (Offset == 0x0A) ......................................................... 188 12.1.13.11 CX Configuration and Status Register (Offset == 0x0B)..................................................... 188 12.1.13.12 Endpoint 0 Data Port Register Byte 0 (Offset == 0x0C) ..................................................... 189 12.1.13.13 Interrupt Group Mask Register (Offset == 0x10)................................................................. 191 12.1.13.14 Interrupt Mask Register Byte 0 (Offset == 0x11) ................................................................ 192 12.1.13.15 Interrupt Mask Register Byte 1 (Offset == 0x12) ................................................................ 192 12.1.13.16 Interrupt Mask Register Byte 2 (Offset == 0x13) ................................................................ 194 12.1.13.17 Interrupt Mask Register Byte 3 (Offset == 0x14) ................................................................ 195 12.1.13.18 Interrupt Mask Register Byte 4 (Offset == 0x15) ................................................................ 196 12.1.13.19 Interrupt Mask Register Byte 5 (Offset == 0x16) ................................................................ 197 12.1.13.20 Interrupt Mask Register Byte 6 (Offset == 0x17) ................................................................ 199 12.1.13.21 Interrupt Mask Register Byte 7 (Offset == 0x18) ................................................................ 199 12.1.13.22 Receive Zero-length Data Packet Register Byte 0 (Offset == 0x19) .................................. 200 12.1.13.23 Receive Zero-length Data Packet Register Byte 1 (Offset == 0x1A).................................. 201 12.1.13.24 FIFO Empty Byte 0 (Offset == 0x1C) .................................................................................. 202 12.1.13.25 FIFO Empty Byte 1 (Offset == 0x1D) .................................................................................. 202 12.1.13.26 Interrupt Group Register (Offset == 0x20) .......................................................................... 204 12.1.13.27 Interrupt Source Register Byte 0 (Offset == 0x21).............................................................. 204 12.1.13.28 Interrupt Source Register Byte 1 (Offset == 0x22).............................................................. 206 12.1.13.29 Interrupt Source Register Byte 2 (Offset == 0x23).............................................................. 206 12.1.13.30 Interrupt Source Register Byte 3 (Offset == 0x24).............................................................. 207 12.1.13.31 Interrupt Source Register Byte 4 (Offset == 0x25).............................................................. 208 12.1.13.32 Interrupt Source Register Byte 5 (Offset == 0x26).............................................................. 209 12.1.13.33 Interrupt Source Register Byte 6 (Offset == 0x27).............................................................. 210 12.1.13.34 Interrupt Source Register Byte 7 (Offset == 0x28).............................................................. 211 12.1.13.35 Isochronous Sequential Error Register Byte 0 (Offset == 0x29)......................................... 213 12.1.13.36 Isochronous Sequential Error Register Byte 1 (Offset == 0x2A) ........................................ 215 12.1.13.37 Isochronous Sequential Abort Register Byte 0 (Offset == 0x2B)........................................ 215 12.1.13.38 Isochronous Sequential abort Register Byte 1 (Offset == 0x2C)........................................ 216 12.1.13.39 Transferred Zero-length Register Byte 0 (Offset == 0x2D)................................................. 216 12.1.13.40 Transferred Zero-length Register Byte 1 (Offset == 0x2E) ................................................. 218 12.1.13.41 Idle Counter (Offset == 0x2F) ............................................................................................. 218 12.1.13.42 Endpoint x Map Register (One per Endpoint, x = 1 ~ 15) (Offset == 0x30 ~ 0x3E) ........... 219

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12.1.13.43 HBF Data Byte Count (Offset == 0x3F) .............................................................................. 221 12.1.13.44 IN Endpoint x MaxPacketSize Register Low Byte (One per Endpoint, x = 1 ~ 15) (Offset ==

0x(40+2(x-1))).............................................................................................................................. 222 12.1.13.45 IN Endpoint x MaxPacketSize Register High Byte (One per Endpoint, x = 1 ~ 15) (Offset ==

0x(41+2(x-1))).............................................................................................................................. 222 12.1.13.46 OUT Endpoint x MaxPacketSize Register Low Byte (One per Endpoint, x = 1 ~ 15) (Offset

== 0x(60+2(x-1)))......................................................................................................................... 223 12.1.13.47 OUT Endpoint x MaxPacketSize Register High Byte (One per Endpoint, x = 1 ~ 15) (Address

= 0x(61+2(x-1)))........................................................................................................................... 224 12.1.13.48 DMA Mode Enable Register Low Byte (Offset == 0x7E) .................................................... 226 12.1.13.49 DMA Mode Enable Register High Byte (Offset == 0x7F).................................................... 226 12.1.13.50 FIFOx Map Register (One per FIFO, x = 0 ~ 15) (Offset == 0x80 ~ 0x8F)......................... 226 12.1.13.51 FIFOx Configuration Register (One per FIFO, x = 0 ~ 15) (Offset == 0x90 ~ 0x9F) .......... 227 12.1.13.52 FIFOx Instruction Register (One per FIFO, x = 0 ~ 15) (Offset == 0xA0 ~ 0xAF) .............. 230 12.1.13.53 FIFOx Byte-Count Register Low Byte (One per FIFO, x = 0 ~ 15) (Offset == 0xB0 ~ 0xBF).............. 230 12.1.13.54 Data Port Register (Offset == 0xC0 ~ 0xFC) ...................................................................... 232

USB2.0 Transceiver Macrocell Tester (T&MT) Interface ......................................................................................... 233 12.1.14 FUSB220 Receives Even Data Bytes from Transceiver ...................................................................... 233 12.1.15 FUSB220 Receives Odd Data Bytes from Transceiver........................................................................ 234 12.1.16 FUSB220 Transmits Even Data Bytes to Transceiver ......................................................................... 234 12.1.17 FUSB220 Transmits Odd Data Bytes to Transceiver........................................................................... 235

Programming Guide ................................................................................................................................................. 236 12.1.18 Bulk / Isochronous / Interrupt Data Transfer......................................................................................... 236

12.1.18.1 Interrupt Handling ........................................................................................................................ 236 12.1.18.2 IN Endpoint Data Transfer........................................................................................................... 236 12.1.18.3 OUT Endpoint Data Transfer....................................................................................................... 237

12.1.19 Initial Register Setting for FIFO Control................................................................................................ 237 12.1.19.1 Setting the Relationship between Internal FIFO and Endpoint ................................................... 237

12.1.20 Setting the Properties of Endpoint........................................................................................................ 239 12.1.20.1 Max_packet_size for IN Endpoint................................................................................................ 239 12.1.20.2 Max_packet_size for OUT Endpoint............................................................................................ 239 12.1.20.3 Setting the Properties of Internal FIFO........................................................................................ 241

13 Interrupt Controller (INTC) ....................................................................................................................................... 242 General Description.................................................................................................................................................. 242 Features ................................................................................................................................................................... 242 Block Diagram .......................................................................................................................................................... 242

13.1.1 APB....................................................................................................................................................... 244 13.1.2 Config Register Block ........................................................................................................................... 244 13.1.3 Interrupt Detect Block ........................................................................................................................... 244 13.1.4 EVIC interrupt input detection............................................................................................................... 244 13.1.5 EVIC priority arbiter and vector encoder .............................................................................................. 245

Interrupt Routing Table............................................................................................................................................. 245 Programming Model ................................................................................................................................................. 247

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13.1.6 Summary of Interrupt Controller Registers ........................................................................................... 247 13.1.7 Register Descriptions............................................................................................................................ 249

13.1.7.1 HW1(+0x00)/HW0(+0x20) Source Register ................................................................................ 249 13.1.7.2 HW1(+0x04)/HW0(+0x24) Enable Register ................................................................................ 249 13.1.7.3 HW1(+0x08)/HW0(+0x28) Interrupt Clear Register .................................................................... 249 13.1.7.4 HW1(+0x0C)/HW0(+0x2C) Trigger Mode Register..................................................................... 249 13.1.7.5 HW1(+0x10)/HW0(+0x30) Trigger Level Register ...................................................................... 249 13.1.7.6 HW1(+0x0C)/HW0(+0x2C) Status Register ................................................................................ 249 13.1.7.7 Revision Register(+0x50) ............................................................................................................ 249 13.1.7.8 EVIC interrupt priority level configuration registers(+0x60~0x6c) ............................................... 250

14 General Purpose Input / Output (GPIO)................................................................................................................... 251 General Description.................................................................................................................................................. 251 Features ................................................................................................................................................................... 251 Block Diagram .......................................................................................................................................................... 252 Programming Model ................................................................................................................................................. 253

14.1.1 Summary Of General Purpose I/O Registers ....................................................................................... 253 14.1.2 Register Descriptions............................................................................................................................ 254

14.1.2.1 GpioDataOut (Offset == 0x00)..................................................................................................... 254 14.1.2.2 GpioDataIn (Offset == 0x04) ....................................................................................................... 255 14.1.2.3 PinDir (Offset == 0x08)................................................................................................................ 255 14.1.2.4 GpioDataSet (Offset == 0x10) ..................................................................................................... 255 14.1.2.5 GpioDataClear (Offset == 0x14).................................................................................................. 255 14.1.2.6 PinPullEnable (Offset == 0x18) ................................................................................................... 256 14.1.2.7 PinPullType (Offset == 0x1C)...................................................................................................... 256 14.1.2.8 IntrEnable (Offset == 0x20) ......................................................................................................... 256 14.1.2.9 IntrRawState (Offset == 0x24)..................................................................................................... 258 14.1.2.10 IntrMaskedState (Offset == 0x28) ............................................................................................... 258 14.1.2.11 IntrMask (Offset == 0x2C) ........................................................................................................... 258 14.1.2.12 IntrClear (Offset == 0x30)............................................................................................................ 259 14.1.2.13 IntrTrigger (Offset == 0x34) ......................................................................................................... 259 14.1.2.14 IntrBoth (Offset == 0x38) ............................................................................................................. 259 14.1.2.15 IntrRiseNeg (Offset == 0x3C) ...................................................................................................... 260 14.1.2.16 BounceEnable (Offset == 0x40) .................................................................................................. 260 14.1.2.17 BouncePreScale (Offset == 0x44)............................................................................................... 260

14.1.3 Timing ................................................................................................................................................... 261 14.1.3.1 Write to GpioDataOut Register.................................................................................................... 261 14.1.3.2 Positive Edge Trigger .................................................................................................................. 261 14.1.3.3 Level High Trigger ....................................................................................................................... 261

Programming Sequence........................................................................................................................................... 263 15 AHB to APB Bridge (APB Bridge) ............................................................................................................................ 264 16 Pulse Width Modulator (PWM)................................................................................................................................. 265

General Descriptions................................................................................................................................................ 265 Features ................................................................................................................................................................... 265

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Block Diagram .......................................................................................................................................................... 265 16.1.1 APB Slave............................................................................................................................................. 266 16.1.2 Control Register.................................................................................................................................... 266 16.1.3 Counters and Comparators .................................................................................................................. 266

Programming Model ................................................................................................................................................. 266 16.1.4 Summary of PWM Registers ................................................................................................................ 266 16.1.5 Register Descriptions............................................................................................................................ 266 16.1.6 PWM0 CTRL Register (Offset == 0x00) ............................................................................................... 266

16.1.6.1 PWM0 DUTY Register (Offset == 0x04) ..................................................................................... 267 16.1.6.2 PWM0 PERVAL Register (Offset == 0x08) ................................................................................. 267 16.1.6.3 PWM1 CTRL Register (Offset == 0x10)...................................................................................... 267 16.1.6.4 PWM1 DUTY Register (Offset == 0x14) ..................................................................................... 267 16.1.6.5 PWM1 PERVAL Register (Offset == 0x18) ................................................................................. 268

Pulse Width Modulator Output Signal Example ....................................................................................................... 268 17 I2C Bus Interface Controller...................................................................................................................................... 269 18 Watch Dog Timer (WDT).......................................................................................................................................... 270

General Descriptions................................................................................................................................................ 270 Features ................................................................................................................................................................... 270 Block Diagram .......................................................................................................................................................... 270 Programming Model ................................................................................................................................................. 271

18.1.1 Summary Of WDT Registers ................................................................................................................ 271 18.1.2 Register Descriptions............................................................................................................................ 272

18.1.2.1 WdCounter (Offset == 0x00) ....................................................................................................... 272 18.1.2.2 WdLoad (Offset == 0x04) ............................................................................................................ 272 18.1.2.3 WdRestart (Offset == 0x08)......................................................................................................... 273 18.1.2.4 WdCR (Offset == 0x0C) .............................................................................................................. 273 18.1.2.5 WdStatus (Offset == 0x10) .......................................................................................................... 273 18.1.2.6 WdClear (Offset == 0x14)............................................................................................................ 275 18.1.2.7 WdIntrCter (Offset == 0x18) ........................................................................................................ 275

Timing....................................................................................................................................................................... 275 18.1.3 Write to WdLoad Register..................................................................................................................... 275 18.1.4 Write to WdLoad Register..................................................................................................................... 276

Programming Sequence........................................................................................................................................... 276 19 Timer ........................................................................................................................................................................ 277 20 Real Time Clock (RTC) ............................................................................................................................................ 278 21 SD Memory Card Host Controller (SDC) ................................................................................................................. 279 22 CompactFlash Host Interface Controller (CFC) ....................................................................................................... 280 23 UART and IrDA Controller........................................................................................................................................ 281

General Descriptions................................................................................................................................................ 281 Features ................................................................................................................................................................... 281 Block Diagram .......................................................................................................................................................... 283

23.1.1 APB Interface........................................................................................................................................ 284

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23.1.2 Prescaler............................................................................................................................................... 284 23.1.3 Baud Rate Generator............................................................................................................................ 284 23.1.4 Tx FIFO and Rx FIFO........................................................................................................................... 284 23.1.5 Status FIFO .......................................................................................................................................... 284 23.1.6 Configuration and Status Registers...................................................................................................... 286 23.1.7 Modem Control and Flags .................................................................................................................... 286 23.1.8 SIR Logic .............................................................................................................................................. 286 23.1.9 FIR Logic............................................................................................................................................... 286 23.1.10 SIP Generator....................................................................................................................................... 286

Modes of Operation.................................................................................................................................................. 287 23.1.11 UART Mode .......................................................................................................................................... 287

23.1.11.1 FIR Transmission Closing Method .............................................................................................. 289 23.1.11.2 FIR Data-Receive Method in PIO mode...................................................................................... 290 23.1.11.3 Serial Infrared Interaction Pulse .................................................................................................. 290 23.1.11.4 Tx FIFO Underrun in FIR Mode................................................................................................... 291 23.1.11.5 Rx FIFO Overrun in FIR Mode .................................................................................................... 291 23.1.11.6 St FIFO Overrun in FIR Mode ..................................................................................................... 291 23.1.11.7 DMA Operation in FIR Mode ....................................................................................................... 291 23.1.11.8 DMA Data-Transmit Mode........................................................................................................... 292 23.1.11.9 DMA Data-Receive Mode............................................................................................................ 292

Programming Model ................................................................................................................................................. 294 23.1.12 Summary Of UART and IrDA Communications Controller Registers .................................................. 294 23.1.13 Registers Descriptions.......................................................................................................................... 295

23.1.13.1 Receiver Buffer Register (Offset == 0x00 for read)..................................................................... 295 23.1.13.2 Transmitter Holding Register (Offset == 0x00 for write).............................................................. 297 23.1.13.3 Interrupt Enable Register (Offset == 0x04) ................................................................................. 297 23.1.13.4 Interrupt Identification Register (Offset == 0x08) ........................................................................ 298 23.1.13.5 FIFO Control Register (Offset == 0x08 for write) ........................................................................ 300 23.1.13.6 Line Control Register (Offset == 0x0C) ....................................................................................... 302 23.1.13.7 Modem Control Register (Offset == 0x10) .................................................................................. 305 23.1.13.8 Line Status Register (Offset == 0x14 for read)............................................................................ 306 23.1.13.9 Modem Status Register (Offset == 0x18).................................................................................... 307 23.1.13.10 Scratch Pad Register (Offset == 0x1C)............................................................................... 308 23.1.13.11 Baud-Rate Divisor Latch (Offset == 0x00, 0x04 when DLAB = 1) ...................................... 308 23.1.13.12 Prescaler Register (Offset == 0x08 when DLAB =1) .......................................................... 310 23.1.13.13 Mode Definition Register Offset == 0x20) ........................................................................... 310 23.1.13.14 Auxiliary Control Register (Offset == 0x24)......................................................................... 311 23.1.13.15 Transmit Frame-Length Register (Offset == 0x28, 0x2C)................................................... 313 23.1.13.16 Maximum Receiver Frame-Length (Offset == 0x30, 0x34)................................................. 313 23.1.13.17 Preamble Length Register (Offset == 0x38) ....................................................................... 314 23.1.13.18 FIR Mode Interrupt Identification Register (Offset == 0x3C, PIO Mode) ............................ 314 23.1.13.19 FIR Mode Interrupt Identification Register (Offset == 0x3C, DMA Mode) .......................... 315 23.1.13.20 FIR Mode Interrupt Identification Enable Register (Offset == 0x40, PIO Mode)................. 316

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23.1.13.21 FIR Mode Interrupt Identification Enable Register (Offset == 0x40, DMA Mode)............... 316 23.1.13.22 Status FIFO Line Status Register (Offset == 0x44) ............................................................ 316 23.1.13.23 Status FIFO Received Frame Length Register - Low (Offset == 0x48).............................. 318 23.1.13.24 Status FIFO Received Frame Length Register - High (Offset == 0x4C) ............................ 318 23.1.13.25 FIR Mode Link Status Register (Offset == 0x50) ................................................................ 318 23.1.13.26 FIR Mode Link Status Interrupt Enable Register (Offset == 0x54) ..................................... 320 23.1.13.27 Resume Register (Offset == 0x58) ..................................................................................... 320 23.1.13.28 Rx FIFO Count Register (Offset == 0x5C) .......................................................................... 320 23.1.13.29 Last Frame Length Register Low (Offset == 0x60)............................................................. 321 23.1.13.30 Last Frame Length Register High (Offset == 0x64) ............................................................ 321

Programming Sequence........................................................................................................................................... 323 23.1.14 SIR Mode.............................................................................................................................................. 323 23.1.15 SIR Data Transmission Mode............................................................................................................... 323 23.1.16 SIR Data Receive Mode ....................................................................................................................... 324 23.1.17 FIR Mode .............................................................................................................................................. 324

23.1.17.1 FIR Data Transmission Mode...................................................................................................... 324 23.1.17.2 FIR Data Receive Mode .............................................................................................................. 325

24 Synchronous Serial Port Controller (SSP/I2S/AC97) ............................................................................................... 327 25 DC Characteristics ................................................................................................................................................... 328

Absolute Maximum Ratings ..................................................................................................................................... 328 Recommended Operating Conditions ...................................................................................................................... 328 I/O Pad Capacitance ................................................................................................................................................ 328

26 AC Characteristics.................................................................................................................................................... 330 AC Timing for SDRAM/SMC Interface ..................................................................................................................... 330 AC Timing for Ethernet MAC MII Interface............................................................................................................... 330 AC Timing for AMBA Bus Interface.......................................................................................................................... 331 AC Timing for USB2.0 T&MT Interface .................................................................................................................... 332

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List of Tables Table 1. AG101 Signal Descriptions. ............................................................................................................................. 13 Table 2. BGA Pin Assignments (I). ................................................................................................................................ 19 Table 3. BGA Pin Assignments (II). ............................................................................................................................... 20 Table 4. AG101 Internal Registers Sorted by Address.................................................................................................. 23 Table 5. Jumper Setting for the Output Frequency of PLL1. ......................................................................................... 42 Table 6. Effect of Each Type of Reset on Internal Register State. ................................................................................ 44 Table 7. Summary of PMU Registers. ........................................................................................................................... 53 Table 8. ID Register (IDNMBR0).................................................................................................................................... 55 Table 9. OSC Control Register (OSCC). ....................................................................................................................... 58 Table 10. Power Mode Register (PMODE).................................................................................................................... 58 Table 11. Power Manager Control Register (PMCR)..................................................................................................... 60 Table 12. Power Manager Edge Detect (PED) Register. .............................................................................................. 60 Table 13. Power Manager Edge Detect Status Register (PEDSR). .............................................................................. 61 Table 14. Power Manager Status Register (PMSR). ..................................................................................................... 61 Table 15. Power Manager GPIO Sleep State Register (PGSR).................................................................................... 63 Table 16. Multi-Function Port Setting Register (MFPSR). ............................................................................................. 63 Table 17. Misc. ............................................................................................................................................................... 65 Table 18. PLL/DLL Control Register 0 (PDLLCR0). ...................................................................................................... 65 Table 19. PLL/DLL Control Register 1 (PDLLCR1). ...................................................................................................... 67 Table 20. AHB Module Clock Off Control Register (AHBMCLKOFF)............................................................................ 67 Table 21. APB Module Clock Off Control Register (APBMCLKOFF). ........................................................................... 68 Table 22. Driving Capability and Slew Rate Control Register 0 (DCSRCR0). .............................................................. 70 Table 23. Driving Capability and Slew Rate Control Register 1 (DCSRCR1). .............................................................. 70 Table 24. Driving Capability and Slew Rate Control Register 2 (DCSRCR2). .............................................................. 72 Table 25. SDRAM Signal Hold Time Control (SDRAMHTC). ........................................................................................ 73 Table 26. Power Manager Scratch Pad Register (PSPR). ............................................................................................ 74 Table 27. Mapping of the AHB/APB DMA channels and the Device DMA REQ/GNT. ................................................. 75 Table 28. AHB DMA REQ/ACK Connection Configuration Status. ............................................................................... 77 Table 29. Table of Jumper Setting Status...................................................................................................................... 77 Table 30. CFC REQ/ACK Connection Configuration..................................................................................................... 79 Table 31. SSP1 REQ/ACK Connection Configuration................................................................................................... 79 Table 32. UART1 TX REQ/ACK Connection Configuration........................................................................................... 79 Table 33. UART1 RX REQ/ACK Connection Configuration. ......................................................................................... 80 Table 34. UART2 TX REQ/ACK Connection Configuration........................................................................................... 80 Table 35. UART2 RX REQ/ACK Connection Configuration. ......................................................................................... 81 Table 36. SDC REQ/ACK Connection Configuration. ................................................................................................... 81 Table 37. AC97 REQ/ACK Connection Configuration. .................................................................................................. 81 Table 38. USB2.0 Device REQ/ACK Connection Configuration.................................................................................... 82

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Table 39. External Device0 REQ/ACK Connection Configuration................................................................................. 82 Table 40. External Device1 REQ/ACK Connection Configuration................................................................................. 82 Table 41. Summary of the AHB Controller Registers. ................................................................................................... 90 Table 42. AHB Slave 0 Base/Size Register. .................................................................................................................. 91 Table 43. Priority Control Register. ................................................................................................................................ 92 Table 44. AHB Master Request Routing Table.............................................................................................................. 92 Table 45. Transfer Control Register............................................................................................................................... 92 Table 46. Interrupt Control Register............................................................................................................................... 93 Table 68. MAC controller Register Summary. ............................................................................................................. 114 Table 69. Interrupt Status Register. ............................................................................................................................. 116 Table 70. Interrupt Mask Register................................................................................................................................ 116 Table 71. MAC Most Significant Address Register. ..................................................................................................... 117 Table 72. MAC Least Significant Address Register. .................................................................................................... 117 Table 73. Multicast Address Hash Table 0 Register.................................................................................................... 117 Table 74. Multicast Address Hash Table 1 Register.................................................................................................... 117 Table 75. Transmit Poll Demand Register. .................................................................................................................. 118 Table 76. Receive Poll Demand Register. ................................................................................................................... 118 Table 77. Transmit Ring Base Address Register......................................................................................................... 118 Table 78. Receive Ring Base Address Register.......................................................................................................... 118 Table 79. Interrupt Timer Control Register. ................................................................................................................. 119 Table 80. Automatic Polling Timer Control Register. ................................................................................................... 122 Table 81. DMA Burst Length and Arbitration Control Register. ................................................................................... 123 Table 82. MAC Control Register. ................................................................................................................................. 126 Table 83. MAC Status Register.................................................................................................................................... 126 Table 84. PHY Control Register................................................................................................................................... 127 Table 85. PHY Write Data Register. ............................................................................................................................ 127 Table 86. Flow Control Register................................................................................................................................... 128 Table 87. Back Pressure Register. .............................................................................................................................. 128 Table 88. Test Seed Register. ..................................................................................................................................... 129 Table 89. DMA/FIFO State Register. ........................................................................................................................... 129 Table 90. Test Mode Register...................................................................................................................................... 130 Table 91. TX_MCOL and TX_SCOL Counter Register. .............................................................................................. 130 Table 92. RPF and AEP Counter Register. ................................................................................................................. 130 Table 93. XM and PG Counter Register. ..................................................................................................................... 131 Table 94. RUNT_CNT and TLCC Counter Register. ................................................................................................... 131 Table 95. CRCER_CNT and FTL_CNT Counter Register........................................................................................... 131 Table 96. RLC and RCC Counter Register.................................................................................................................. 131 Table 97. BROC Counter Register. ............................................................................................................................. 132 Table 98. MULCA Counter Register. ........................................................................................................................... 132 Table 99. RP Counter Register. ................................................................................................................................... 132 Table 100. XP Counter Register. ................................................................................................................................. 132 Table 116. Little Endian Byte, Little Endian Pixel. ....................................................................................................... 142

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Table 117. Little Endian Byte, Little Endian Pixel. ....................................................................................................... 143 Table 118. Little Endian Byte, Big Endian Pixel........................................................................................................... 144 Table 119. Mapping for Raw RGB Mode. .................................................................................................................... 144 Table 120. Pixel Sequence for YCbCr422 Mode. ........................................................................................................ 144 Table 121. Component Location/Sequence for YCbCr420 Mode. .............................................................................. 145 Table 122. Palette RAM Data Structure (for Entry 0)................................................................................................... 146 Table 123. Font Attribute Structure. ............................................................................................................................. 148 Table 124. LCD 18-Bit and 24-Bit Interface. ................................................................................................................ 149 Table 125. Control Register Summary......................................................................................................................... 150 Table 126. LCD Horizontal Timing Control. ................................................................................................................. 150 Table 127. LCD Vertical Timing Control. ..................................................................................................................... 151 Table 128. LCD Clock and Signal Polarity Control ...................................................................................................... 152 Table 129. LCD Panel Frame Base Address............................................................................................................... 152 Table 130. LCD Interrupt Enable Mask........................................................................................................................ 154 Table 131. LCD Panel Pixel Parameters ..................................................................................................................... 154 Table 132. LCD Interrupt Status Clear......................................................................................................................... 155 Table 133. LCD Interrupt Status .................................................................................................................................. 156 Table 134. OSD Scaling and Dimension Control......................................................................................................... 156 Table 135. OSD Position Control ................................................................................................................................. 157 Table 136. OSD Foreground Color Control ................................................................................................................. 157 Table 137. OSD Background Color Control................................................................................................................. 157 Table 138. GPI/GPO Control ....................................................................................................................................... 158 Table 139. LCD Palette RAM Accessing Port.............................................................................................................. 158 Table 140. OSD Font Database Write Accessing Port ................................................................................................ 160 Table 141. OSD Window Attribute Write Accessing Port ............................................................................................ 161 Table 142. Summary of the FUSB220 Registers......................................................................................................... 176 Table 143. Main Control Register. ............................................................................................................................... 182 Table 144. Device Address Register. .......................................................................................................................... 184 Table 145. Test Register.............................................................................................................................................. 184 Table 146. SOF Frame Number Register Byte 0......................................................................................................... 185 Table 147. SOF Frame Number Register Byte 1......................................................................................................... 186 Table 148. SOF Mask Timer Register Byte 0. ............................................................................................................. 186 Table 149. SOF Mask Timer Register Byte 1 .............................................................................................................. 186 Table 150. PHY Test Mode Selector Register. ............................................................................................................ 187 Table 151. Vendor Specific IO Control Register. ......................................................................................................... 188 Table 152. Vendor Specific IO Status Register. .......................................................................................................... 188 Table 153. CX Configuration and Status Register. ...................................................................................................... 188 Table 154. Interrupt Group Mask Register................................................................................................................... 191 Table 155. Interrupt Mask Register Byte 0. ................................................................................................................. 192 Table 156. Interrupt Mask Register Byte 1. ................................................................................................................. 192 Table 157. Interrupt Mask Register Byte 2. ................................................................................................................. 194 Table 158. Interrupt Mask Register Byte 3. ................................................................................................................. 195 Table 159. Interrupt Mask Register Byte 4. ................................................................................................................. 196

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Table 160. Interrupt Mask Register Byte 5. ................................................................................................................. 197 Table 161. Interrupt Mask Register Byte 6. ................................................................................................................. 199 Table 162. Interrupt Mask Register Byte 7. ................................................................................................................. 199 Table 163. Receive Zero-length Data Packet Register Byte 0. ................................................................................... 201 Table 164. Receive Zero-length Data Packet Register Byte 1. ................................................................................... 201 Table 165. FIFO Empty Byte 0..................................................................................................................................... 202 Table 166. FIFO Empty Byte 1..................................................................................................................................... 202 Table 167. Interrupt Group Register. ........................................................................................................................... 204 Table 168. Interrupt Source Register Byte 0................................................................................................................ 204 Table 169. Interrupt Source Register Byte 1................................................................................................................ 206 Table 170. Interrupt Source Register Byte 2................................................................................................................ 206 Table 171. Interrupt Source Register Byte 3................................................................................................................ 207 Table 172. Interrupt Source Register Byte 4................................................................................................................ 208 Table 173. Interrupt Source Register Byte 5................................................................................................................ 209 Table 174. Interrupt Source Register Byte 6................................................................................................................ 210 Table 175. Interrupt Source Register Byte 7................................................................................................................ 212 Table 176. Isochronous Sequential Error Register Byte 0........................................................................................... 213 Table 177. Isochronous Sequential Error Register Byte 1........................................................................................... 215 Table 178. Isochronous Sequential Abort Register Byte 0. ......................................................................................... 215 Table 179. Isochronous Sequential Abort Register Byte 1 .......................................................................................... 216 Table 180. Transferred Zero-length Register Byte 0. .................................................................................................. 216 Table 181. Transferred Zero-length Register Byte 1. .................................................................................................. 218 Table 182. Idle Counter................................................................................................................................................ 218 Table 183. Endpoint x Map Register............................................................................................................................ 219 Table 184. HBF Data Byte Count................................................................................................................................. 221 Table 185. IN Endpoint x MaxPacketSize Register Low Byte. .................................................................................... 222 Table 186. IN Endpoint x MaxPacketSize Register High Byte. ................................................................................... 222 Table 187. OUT Endpoint x MaxPacketSize Register Low Byte. ................................................................................ 223 Table 188. OUT Endpoint x MaxPacketSize Register High Byte. ............................................................................... 224 Table 189. DMA Mode Enable Register Low Byte....................................................................................................... 226 Table 190. DMA Mode Enable Register High Byte...................................................................................................... 226 Table 191. FIFOx Map Register................................................................................................................................... 226 Table 192. FIFOx Configuration Register. ................................................................................................................... 227 Table 193. FIFOx Instruction Register. ........................................................................................................................ 230 Table 194. FIFOx Byte-Count Register Low Byte........................................................................................................ 230 Table 195. Data Port Register...................................................................................................................................... 232 Table 196. Endpoint Map Register: Address = 3xH (x = 0 ~ E)................................................................................... 237 Table 197. FIFO Map Register: Address = 8xH (x = 0 ~ F). ........................................................................................ 237 Table 198. 40H + (x-1) * 2H for bits [7:0]. .................................................................................................................... 239 Table 199. 40H + (x-1) * 2H + 1 for bits [10:8]. ............................................................................................................ 239 Table 200. 60H + (x-1) * 2H for bits [7:0]. .................................................................................................................... 239 Table 201. 60H + (x-1) * 2H + 1 for bits [10:8]. ............................................................................................................ 239

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Table 202. Interrupt Routing Table. ............................................................................................................................. 246 Table 203. Summary of Interrupt Controller Registers. ............................................................................................... 247 Table 204. Summary of General Purpose I/O Registers. ............................................................................................ 253 Table 205. Gpio Data Out Register.............................................................................................................................. 254 Table 206. Gpio Data In Register................................................................................................................................. 255 Table 207. Pin Direction Register. ............................................................................................................................... 255 Table 208. Gpio Data Bit Set Register. ........................................................................................................................ 255 Table 209. Gpio Data Bit Clear Register...................................................................................................................... 256 Table 210. Pin Pull Enable Register. ........................................................................................................................... 256 Table 211. Pin Pull Type Register................................................................................................................................ 256 Table 212. Pull Truth Table.......................................................................................................................................... 256 Table 213. Interrupt Enable Register. .......................................................................................................................... 258 Table 214. Interrupt Raw State Register...................................................................................................................... 258 Table 215. Interrupt Masked State Register. ............................................................................................................... 258 Table 216. Interrupt Mask Register.............................................................................................................................. 258 Table 217. Interrupt Clear. ........................................................................................................................................... 259 Table 218. Interrupt Trigger Method Register.............................................................................................................. 259 Table 219. Interrupt Both Edge Trigger Register. ........................................................................................................ 259 Table 220. Interrupt Rise or Neg Edge Trigger Register. ............................................................................................ 260 Table 221. Bounce Enable Register. ........................................................................................................................... 260 Table 222. Bounce Clock Pre-scale Register. ............................................................................................................. 260 Table 230. Summary of PWM Control Register........................................................................................................... 266 Table 231. PWM0 CTRL Register................................................................................................................................ 267 Table 232. PWM0 DUTY Register. .............................................................................................................................. 267 Table 233. PWM0 PERVAL Register........................................................................................................................... 267 Table 242. Summary of WDT Registers. ..................................................................................................................... 271 Table 243. WdCounter Register................................................................................................................................... 272 Table 244. WdLoad Register. ...................................................................................................................................... 272 Table 245. WdRestart Register.................................................................................................................................... 273 Table 246. WdCR Register. ......................................................................................................................................... 273 Table 247. WdStatus Register. .................................................................................................................................... 273 Table 248. WdClear Register....................................................................................................................................... 275 Table 249. WdIntrCter Register. .................................................................................................................................. 275 Table 298. Summary of UART/SIR Mode Registers.................................................................................................... 294 Table 299. Receiver Buffer Register. ........................................................................................................................... 295 Table 300. Transmitter Holding Register. .................................................................................................................... 297 Table 301. Interrupt Enable Register. .......................................................................................................................... 297 Table 302. Interrupt Identification Register. ................................................................................................................. 298 Table 303. Interrupt Control Table. .............................................................................................................................. 298 Table 304. FIFO Control Register. ............................................................................................................................... 300 Table 305. Receiver’s FIFO Trigger Level. .................................................................................................................. 300 Table 306. Transmitter’s FIFO Trigger Level. .............................................................................................................. 302 Table 307. Line Control Register. ................................................................................................................................ 302

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Table 308. Parity Setting Table.................................................................................................................................... 303 Table 309. Word Length and Stop Bits Setting Table.................................................................................................. 303 Table 310. Modem Control Register. ........................................................................................................................... 305 Table 311. Line Status Register................................................................................................................................... 306 Table 312. Modem Status Register. ............................................................................................................................ 307 Table 313. Scratch Pad Register. ................................................................................................................................ 308 Table 314. Baud Rate Divisor Latch LSB. ................................................................................................................... 308 Table 315. Baud Rate Divisor Latch MSB. .................................................................................................................. 310 Table 316. Prescaler Register...................................................................................................................................... 310 Table 317. Mode Definition Register............................................................................................................................ 310 Table 318. Auxiliary Control Register. ......................................................................................................................... 311 Table 319. Status FIFO Trigger Level.......................................................................................................................... 311 Table 320. Transmit Frame-Length Register Low. ...................................................................................................... 313 Table 321. Transmit Frame-Length Register High....................................................................................................... 313 Table 322. Maximum Receiver Frame-Length Register Low. ..................................................................................... 313 Table 323. Maximum Receiver Frame-Length Register High...................................................................................... 313 Table 324. Preamble Length Register. ........................................................................................................................ 314 Table 325. Number of FIR Preambles. ........................................................................................................................ 314 Table 326. FIR Mode Interrupt Identification Register. ................................................................................................ 314 Table 327. FIR Mode Interrupt Identification Register. ................................................................................................ 315 Table 328. FIR Mode Interrupt Enable Register. ......................................................................................................... 316 Table 329. IrDA Mode Interrupt Enable Register......................................................................................................... 316 Table 330. Status FIFO Line Status Register. ............................................................................................................. 316 Table 331. Status FIFO Received Frame Length Register – Low. .............................................................................. 318 Table 332. Status FIFO Received Frame Length Register – High. ............................................................................. 318 Table 333. FIR Mode Link Status Register. ................................................................................................................. 318 Table 334. FIR Mode Link Status Interrupt Enable Register. ...................................................................................... 320 Table 335. Rx FIFO Count Register. ........................................................................................................................... 320 Table 336. Last Frame Length Register Low............................................................................................................... 321 Table 337. Last Frame Length Register High. ............................................................................................................. 321 Table 338. Frame Number Decoding Table................................................................................................................. 321 Table 347. Absolute Maximum Ratings. ...................................................................................................................... 328 Table 348. Recommended Operating Conditions........................................................................................................ 328 Table 349. I/O Pad Capacitance. ................................................................................................................................. 328 Table 350. AC Timing for SDRAM/SMC Interface. ...................................................................................................... 330 Table 351. AC Timing for Ethernet MAC MII Interface. ............................................................................................... 330 Table 352. AC Timing for AMBA Bus Interface............................................................................................................ 331 Table 353. AC Timing for USB2.0 T&MT Interface...................................................................................................... 332

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Figures List Figure 1. Block Diagram of AG101 .................................................................................................................................. 3 Figure 2. MCU Physical Memory Map. .......................................................................................................................... 22 Figure 3. PMU Block Diagram........................................................................................................................................ 40 Figure 4. Power-on Reset Timing. ................................................................................................................................. 45 Figure 5. Relationship Among the X_rst_b, X_reset_b and X_hreset_b. ...................................................................... 46 Figure 6. N1213 Functional Blocks. ............................................................................................................................... 84 Figure 7. Block Diagram of AHB Controller. .................................................................................................................. 89 Figure 15. MAC Block Diagram...................................................................................................................................... 96 Figure 16. Transmit Frame Control Flow of TXMAC.................................................................................................... 100 Figure 17. Receive Frame Control Flow of RXMAC. ................................................................................................... 101 Figure 18. Transmit Ring Descriptor Structure. ........................................................................................................... 106 Figure 19. Receive Ring Descriptor Structure. ............................................................................................................ 109 Figure 29. FTLCDC100 Design Block Diagram. .......................................................................................................... 139 Figure 30. Example of FTLCDC100 Application Block Diagram. ................................................................................ 139 Figure 31. Palette Remapping Operation. ................................................................................................................... 146 Figure 32. Font Structure (12x16 Dots Per Font)......................................................................................................... 147 Figure 33. OSD Basic Operation Description. ............................................................................................................. 148 Figure 34. Basic TFT Interface Timing Diagram. ......................................................................................................... 149 Figure 35. FUSB220 Block Diagram............................................................................................................................ 163 Figure 36. PIE Block Diagram...................................................................................................................................... 164 Figure 37. CXF Block Diagram. ................................................................................................................................... 165 Figure 38. PAM Block Diagram.................................................................................................................................... 166 Figure 39. Ping-Pong FIFO Mechanism with Different Block Size and Block Number................................................ 167 Figure 40. RGF Block Diagram. ................................................................................................................................... 168 Figure 41. PWE Block Diagram. .................................................................................................................................. 169 Figure 42. USB Reset and High-Speed Detection Handshake Timing Chart.............................................................. 171 Figure 43. FUSB220 Asserts u_susp_n to Turn Off the PLL in PHY........................................................................... 172 Figure 44. FUSB220 Wakened Up by Host Resume / Reset. ..................................................................................... 174 Figure 45. FUSB220 Wakened Up by AP.................................................................................................................... 176 Figure 46. Timing Diagram for tsusp_delay Programming. ......................................................................................... 219 Figure 47. FUSB220 Receives Even Data Bytes from Transceiver. ........................................................................... 233 Figure 48. FUSB220 Receives Odd Data Bytes from Transceiver.............................................................................. 234 Figure 49. FUSB220 Transmits Even Data Bytes to Transceiver................................................................................ 235 Figure 50. FUSB220 Transmits Odd Data Bytes to Transceiver. ................................................................................ 235 Figure 51. INTC Block Diagram. .................................................................................................................................. 243 Figure 52. GPIO Block Diagram................................................................................................................................... 252 Figure 53. Write to GpioDataOut Register. .................................................................................................................. 261 Figure 54. Positive Edge Trigger.................................................................................................................................. 261

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Figure 55. Level High Trigger....................................................................................................................................... 262 Figure 58. Block Diagram of PWM............................................................................................................................... 265 Figure 59. Basic Pulse Width Waveform. .................................................................................................................... 268 Figure 61. Block Diagram of Watch Dog Timer. .......................................................................................................... 270 Figure 62. Write to WdLoad Register........................................................................................................................... 275 Figure 63. Watch Dog Timer Interrupt. ........................................................................................................................ 276 Figure 81. Block Diagram of UARTCommunications Controller. ................................................................................. 283 Figure 82. UART Data Representation and Sampling................................................................................................. 287 Figure 83. SIR Encoding. ............................................................................................................................................. 288 Figure 84. Serial Infrared Interaction Pulse. ................................................................................................................ 290 Figure 85. Interconnection between MCR and MSR in Loop Back Mode. .................................................................. 306

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Preface This preface describes the contents of this manual.

About this manual This Datasheet provides the information about AndeShape™ platform IP AG101P specification. All information contains in this document is subject to change without notice

Version of AG101 data sheet This manual is version 1.0

Contact information Please contact Andes Technology Corporation by email at [email protected] or on the Internet at www.andestech.com for support.

Copyright notice © 2007 Andes Technology Corporation. All rights reserved.

This document contains certain confidential information of Andes Technology Corporation. Use of this copyright notice is precautionary and does not imply publication or disclosure. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the written permission of Andes Technology Corporation.

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1 Introduction AG101 is the main chip of the Andes AndeShape™ hardware development platform. It is a cost-effective, high

performance solution for SoC integration and verification in the early development stage. Users can easily attach their

IP through the extended AHB bus to evaluate the system performance of their applications and identify any design

flaws. The AG101 products specifically address the requirements of the personal, portable product market by providing

peripherals intelligently integrated with an advanced processor core and power management capabilities.

The SoC platform AG101 may work properly with any of AndeScore™ products with AHB front side bus, while the

first test chip of AG101 has integrated a hardcore of N1213 product family. The following list summarizes its features.

Features

Architecture

− AMBA-AHB bus based for high speed devices

− AMBA-APB bus based for low power devices

− Dedicated DMA AHB local memory bus

− Dedicated LCD AHB local memory bus

Embedded Processor:

− Andes N1213

− 32-bit RISC

− 32 KB I-Cache / 32KB D-Cache

− 16 KB local memory for instruction

− 16 KB local memory for data

− MMU with hardware page table walker

− 500+ MHZ clock speed

− Simulation model provided with IPs

External Bus Interface

− External AHB bus

− 32-bit SDRAM interface at up to 100 MHz

− Asynchronous SRAM/ROM/Flash

Clock / PLL

− 32.768 KHz low frequency oscillator/crystal input

− 5 – 10 MHz high frequency oscillator/crystal input

− Programmable frequency Core PLL

APB Bus Components

− Timer

− Watch Dog Timer

− Real Time Clock

− Interrupt Controller

− 23 GPIO

− Pulse Width Modulator

− I²C

− Synchronous Serial Port

− I²S / AC97

− Compact Flash Controller

− Multimedia Card / Secure Digital

− Bluetooth UART (BTUART)

− Standard UART (STUART)

Operating Frequency

− AMBA-AHB bus: Up to 100 MHz

− AMBA-APB bus: Up to 50 MHz

Operating Voltage

− 1.2V : Core

− 3.3V : Input / Output

Process:

− 0.13µm

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Andes Technology Confidential AndeShape_AG101P_DS0001_v1.0 2

− One DLL for de-skew clock function

− 4 clock output pins for SDRAM use

Power Management

− PLL frequency change control

− Clock gating control

− Frequency scaling control for CPU and system bus clock

− Sleep Mode

− poweren: Turn on / off the external main power

− powerok / powerlow_b: Indicate the power status

AHB Bus Components

− SDRAM Controller

− AHB to APB Bridge

− Static Memory Controller

− Ethernet MAC 10/100Mb Controller

− USB 2.0 Device

− DMA Controller

Package:

− 552-pin BGA

Extension:

− Tri-state AHB bus for external AHB devices

− 2 Req/Gnt pairs for external AHB masters

− 2 DMA channels

− 4 HSEL signals for external AHB slaves

− 6 Interrupt inputs

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Block Diagram

Figure 1. Block Diagram of AG101

1.1.1 Peripheral Components

The peripheral components can be divided into four groups: System Bus Components, Core APBs, DMA APBs,

and the extended AHB devices

1.1.2 System Bus Components 1.1.2.1 N1213 N1213 is a general-purpose 32-bit embedded RISC processor. It includes a CPU core, separate instruction/data caches

(32K bytes each, 4 way set associated), separate instruction and data local memories (16K bytes each), as well as a

memory management unit and an embedded debug module with JTAG interface.

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1.1.2.2 AHB Controller (AHBC)

The AHB Controller serves as a mechanism to control the access rights for the Advanced High-performance Bus

(AHB). This mechanism supports an arbiter and a decoder, providing a flexible programmable model to save SoC

integration efforts. The mechanism contains the following three (3) components: arbiter, decoder and multiplexer.

The AHBC features include:

● Compliant with AMBA 2.0 specifications ● Multi-level arbitration ● Round-robin arbitration 1.1.2.3 SDRAM Controller (SDRAMC)

Please refer to ATFSDMC021_DS_v1.3.pdf. 1.1.2.4 Static Memory Controller (SMC)

Please refer to ATFSMC020_DS_v1.7.pdf.

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1.1.2.5 LCD Controller (LCDC)

The TFT LCD controller provides all necessary control signals for adapting variety of TFT LCD panels. The

LCDC features include:

LCD Panel Interface:

● Parallel interface with up to 24-bit data bus for Thin Film Transistor (TFT) color displays

● Resolution programmable up to 1024x768

● Pixel clock rate up to 75 MHz

● Programmable polarity/duration for output enable, vertical sync, horizontal sync, and pixel clock

● Data/Synchronization on/off control

● Swap function for red and blue channels

Input Mode:

● RGB 16(5:6:5)/24(8:8:8) bits per pixel

● Palette (8/4/2/1 bits per pixel)

● YCbCr422 (16 bits per pixel)

● YCbCr420 (separate memory location)

Data Format:

● Little-endian, big-endian, and Windows CE

Palette:

● 256-entry 16-bit RGB color palette RAM

On Screen Display:

● RAM based programmable 12x16 font

● Font varieties up to 256

● Maximal window font number is 512

● Flexible dimension for both horizontal and vertical directions

● Programmable window position

● Up-scaling function with factors of 1, 2, 3, and 4

● Transparency of 25%, 50%, 75%, and 100%

● 4-entry, 8-bit color palette for foreground, and 3-entry, 8-bit color palette for background (1 entry reserved for

transparency)

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1.1.2.6 DMA Controller (DMAC)

Please refer to ATFDMAC020_DS_v1.8.pdf.

1.1.2.7 USB 2.0 Device The USB 2.0 device controller serves as an interface with USB devices based on the Universal Serial Bus 2.0

specification. The controller provides high speed signaling bit rate at 480 Mb/s, and full speed signaling bit rate at 12

Mb/s. Each endpoint, except endpoint 0, supports programmable transfer types for isochronous, bulk, and interrupt

transfer. The USB 2.0 device controller features include:

● Compliant with USB protocol revision 2.0

● Backward-compatible with USB1.1

● USB 2.0 Transceiver Macrocell Tester (T&MT) Interface revision 1.2 support

● Programmable transfer type and direction for each endpoint

● Up to fifteen (15) endpoints

● 7K-byte FIFOs for bulk, isochronous and high-bandwidth interrupt endpoint

● 2 * 64-byte FIFOs for non-high-bandwidth interrupt endpoint

● 64-byte FIFOs for endpoint 0

● Maintenance of data toggle bits

● Chirp sequence support

● Isochronous, bulk, interrupt and control transferring

● Suspend mode, remote wake-up, and resume function

● Automated CRC5/CRC16 generation and checking

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1.1.2.8 Ethernet MAC 10 / 100

The Ethernet MAC 10/100 is a high quality 10/100 ethernet controller with efficient data transfer functions

including AHB wrapper, DMA engine, on-chip memory (TX FIFO and RX FIFO), MAC, and MII interface. The

Ethernet MAC 10/100 features include:

● DMA engine for transmitting and receiving packets

● Programmable AHB burst size

● A transmit and receive interrupt mitigation mechanism

● Separate TX and RX FIFOs (2K bytes each)

● Half and full duplex modes

● Flow control for full duplex and backpressure for half duplex

● MII interface

● Little endian support

1.1.2.9 AHB to APB Bridge (APB Bridge)

An AMBA APB implementation typically contains a single APB bridge that converts AHB transfers into a suitable

format for the slave devices on the APB. The bridge provides latching of all address, data and control signals; as

well as a second level of decoding to generate slave select signals for the APB peripherals. The APB Bridge is the

only bus master on the AMBA APB; while it serves as a slave on the higher-level system bus. Additionally, the

APB Bridge provides DMA function to enhance the performance of data transfer. The APB bridge features

include:

● 4 sets of independent DMA channel for APB-to-AHB, AHB-to-APB, AHB-to-AHB or APB-to-APB transfer

● Connection up to 16 sets of APB Devices

1.1.3 Core APB 1.1.3.1 Timer

Please refer to ATFTMR010_DS_v1.2.pdf.

1.1.3.2 Watch Dog Timer (WDT)

The Watch Dog Timer WDT is generally used to restore a system from a deadlock situation. In normal operation, the

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user restarts the WDT at regular intervals before the counter counts down to zero. The WDT generates one or a

combination of the following signals: reset, interrupt or external interrupt. The WDT features include:

● Choices of trigging System Reset, System Interrupt, or External Interrupt upon timeout.

● 32-bit down counter

● PCLK or 32.768 KHz source selection

● Variable time-out period of reset

● Access protection 1.1.3.3 Real Time Controller (RTC)

Please refer to ATFRTC010_DS_v1.2.pdf.

1.1.3.4 Interrupt Controller (INTC)

The Interrupt Controller may communicate with the microproecessor in either IVIC mode and EVIC mode. The INTC features include:

● Operate at APB clock frequency

● 32 interrupt inputs to be mapped to two processor interrupt signals in IVIC mode or to EVIC mode interrupt vector

● 0(min.)~7(max.) configurable priority levels for each EVIC interrupt input

● Edge and level triggered interrupt sources with positive and negative directions(both IVIC and EVIC mode)

1.1.3.5 GPIO

Twenty-three (23) GPIOs are employed to input/output data between system and devices. Each GPIO can be

programmed to function as an input, an output, or as an interrupt input. It supports rising edge, falling edge,

both-edge and high level/low level interrupt sense types. The GPIO features include:

● Each port can separately trigger a GPIO interrupt

● Each port interrupt generation can be triggered by rising / falling edge, both edges or high / low level

● Each port can be pulled high or pulled low

● Sampling rate can be programmed for all I/O ports

● Output data bit can be set or cleared separately

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● All ports are set to input mode at hardware reset

1.1.3.6 Pulse Width Modulator (PWM)

Each PWM has two pulse width channels. The PWMs operate independently of each other; each is controlled by

its own distinct set of registers. The PWM features include:

● Two Pulse Width Modulator channels

● Enhanced period control through 6-bit clock divider and 10-bit period counter

● 10-bit pulse control

1.1.3.7 I²C

Please refer to ATFIIC010_DS_v1.4.pdf.

1.1.3.8 Clock/PLL

The AG101 functional blocks are driven by clocks derived either from a high-frequency clock input (5 – 10 MHz)

or an optional low-frequency clock input (32.768 KHz). The high frequency clock input drives both the core Phase

Locked Loop (PLL) and the peripheral PLL. The PLLs produce the desired clock frequencies to pace each specific

functional block. The low-frequency clock input is an optional clock that drives only the RTC and the power

management unit; it needs to be re-selected once a hard reset occurs.

1.1.3.9 Power Management Unit

AG101 offers a number of modes to manage power in the system. AG101 offers multiple power management

modes that vary greatly in terms of power saving efficiency and levels of functionality.

Supported modes include:

● Sleep Mode: only the contents in the RTC, power management unit, while expect SDRAM content to be preserved

as well by software programming to SDRAM controller

● Frequency Change Sequence (FCS) Mode: the core PLL settings can be configured so the system can operate at

different frequencies

● Frequency scaling control for CPU and system bus clock

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1.1.4 DMA APB 1.1.4.1 Synchronous Serial Port Controller (SSPC)

Please refer to ATFSSP010_DS_v1.4.pdf.

1.1.4.2 I²S / AC97 Controller (I²S / AC97C)


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1.1.4.3 Compact Flash Controller (CFC)

Please refer to ATFCFC010_DS_v1.2.pdf.

1.1.4.4 Multimedia Card and Secure Digital Host Controller (MMC / SDC)

Please refer to ATFSDC010_DS_v1.3.pdf.

1.1.4.5 UART

AG101 supports two (2) UARTs: a Bluetooth UART (BTUART), and a Standard UART (STUART), both

employing the same programming model. The BTUART provides a partial set of modem control pins, including

nCTS and nRTS. The other modem control pins can be implemented via General-Purpose Input/Output (GPIO).

The STUART does not provide any modem control pins. The three UARTs can support baud rates up to 1152

Kbps. The UART features include:

● High-speed NS 16C550A-compatible UART

● Programmable baud rates up to 1152 Kbps

● Ability to add or delete standard asynchronous communications bits (start, stop, and parity) in serial data

● Programmable baud rate generator that allows the internal clock to be divided by 1 to (216-1) to generate an internal

16X clock

● Fully programmable serial interface:

5-, 6-, 7-, or 8-bit characters

Even, odd, and no parity detection

1-, 1.5-, or 2-stop bit generation

● Complete status reporting capability

● Ability to generate and detect line breaks

● Fully prioritized interrupt system controls

● Separate DMA requests for data transmission and reception services

● Break, parity, overrun, framing error simulation for UART mode

● BTUART provides 32-byte transmit FIFO and 32-byte receive FIFO

● STUART provides 16-byte transmit FIFO and 16-byte receive FIFO

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1.1.5 Extended AHB Connection

One set of AHB interface has been provided in AG101 I/O to support external AHB devices, with up to 2 masters

and 4 slaves with split capability. While the original bus lock feature of AHB is not supported by AndeScore™, it

is not supported in this extended connection neither. Instead, AndeScore™ atomic operation signaling is supported

to fullfil atomic access requirement. Please refer to AndeScore™ datasheet for detail.

System Architecture

The system is built on the design of an AMBA multi-layer AHB backbone. While the core is accessing peripherals

or static memory, the SDRAM bandwidth can be fully utilized by the DMA controller. On the AG101 platform, the

following layers are provided:

1.1.6 System AHB Bus

The system AHB bus is the backbone of AG101 serving all masters connected to it.

1.1.7 DMA AHB Bus

The DMA AHB bus serves the DMA controller master. The DMA controller can be programmed to read from, and

write to, either port so each device needs only a single connection to the DMA controller. The DMA AHB Bus is

only connected to the SDRAM controller.

1.1.8 System APB Bus

The AHB-to-APB Bridge masters the system APB Bus. All APB slaves are connected to the APB bus.

Operating Voltage

The AG101 operating voltages are as follows:

● I/O voltage : 3.3 V

● Internal logic voltage: 1.2 V

Package Types

AG101 features a 552-pin PBGA package in the size of 35mm x 35mm x 2.5mm, with a ball pitch of 1.27mm.

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2 Signal Descriptions and Pin Assignments This chapter identifies and describes the AG101 signals that are assigned to the pins.

Signal Descriptions

The AG101 signals are listed in Table 1. In the table, “I” indicates input signals, “O” indicates output signals,

“I/O” indicates bi-directional signals and “SUP” indicates power supply pins.

Table 1. AG101 Signal Descriptions.

Signal Name Dir. Description SDRAM/SRAM Address / Data

X_memaddr[24:0] O SDRAM/SRAM memory address bus. X_memdata[32:0] IO SDRAM/SRAM memory data bus.

SDRAM X_sdram_cke O SDRAM clock enable. X_sdram_ras_b O SDRAM row address strobe. Active low. X_sdram_cas_b O SDRAM column address strobe. Active low. X_sdram_cs_b[3:0] O SDRAM chip select for banks 3 through 0. Active low. X_sdram_we_b O SDRAM write enable. Active low. X_sdram_dqm[3:0] O SDRAM DQM for data bytes 3 through 0. X_sdclk[3:0] O SDRAM clocks.

Static Memory X_smc_be_b[3:0] O Static memory byte enables. Active low. X_smc_we_b O Static memory write enable. Active low. X_smc_cs_b[3:0] O Static memory chip selects for banks 3 through 0. Active low. X_smc_oe_b O Static memory output enable. Active low.

CLCD X_clpower O LCD panel power enable. X_cllp O Line synchronization pulse (STN)/horizontal synchronization pulse (TFT). X_clcp O LCD panel clock. X_clfp O Frame synchronization pulse (STN)/vertical synchronization pulse (TFT). X_clac O STN AC bias drive or TFT data enable output. X_cld[23:0] O LCD panel data. X_clle O Line end signal. X_clcdclk I CLCD reference clock.

DMA I/F X_dma_req[1:0]/GPIO[13,10] I DMA request for external AHB devices.

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Signal Name Dir. Description X_dma_ack[1:0]/GPIO[14,11] O DMA acknowledge for external AHB devices. X_dma_tc[1:0]/GPIO[15,12] O DMA terminal count for external AHB devices.

USB 2.0 Device TMT X_u_clk I TM&T clock. A 30 MHz clock generated by PHY. X_u_data[15:0] IO Data input / output from TM&T. X_u_rxval I Receive data valid.

X_u_rxact I Receive active. Receive state machine of the transceiver has detected SYNC and is active.

X_u_rxerr I Receive error. Indicates that the transceiver detects errors while receiving data from USB host.

X_u_txrdy I Transmit data ready. X_u_linesta[1:0] I Line state. Reflects the state of DP and DM. X_u_txval O Transmit valid. Indicates that data output to the transceiver is valid. X_u_validh I/O Valid high.

X_u_vctload_b O

Vendor control load. Active low. This signal is controlled by the “VCTLOAD_B” bit of Vendor Specific IO Control Register (bit 4, address = 09H). Assertion of this signal means the transceiver should load the data from the output “u_vctl” for vendor-specific tests: 0: Transceiver should load data from the output “u_vctl” 1: NOP

X_u_vctl[3:0] O Vendor control data. These output data come from the “VCTL[3:0]” bits of Vendor Specific IO Control Register (bits 3 ~ 0, address = 09H). They are used for vendor-specific tests, and are valid when the output “X_u_vctload_b” is low.

X_u_xcvrsel O Transceiver select. 0: High speed 1: Full speed

X_u_termsel O Termination select. 0: Control PHY to turn off 1.5K Ohm pull-up resistor 1: Control PHY to turn on 1.5K Ohm pull-up resistor

X_u_susp_b O Suspend mode. Active low. Places the transceiver in a mode that draws minimal power from power supply.

X_u_opmode[1:0] O

Operation mode. 0: Normal Operation 1: Non-Driving 2: Disable Bit Stuffing and NRZI encoding 3: Reserved

X_u_usbrst O USB reset. Resets all states in the transceiver.

X_u_vbus I Vbus. Indicates a device has been attached. This input is used by FUSB220 to detect the attachment of a device to the hub / host.

X_sof O Start of Frame. The pulse is asserted every 1ms for external synchronization in full-speed mode. In high-speed mode, it is asserted every 125 µs.

Ethernet MAC 10 / 100

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Signal Name Dir. Description X_tx_clk I MII transmit clock. X_tx_en O MII transmit enable. X_txd[3:0] O MII transmit data. X_rx_clk I MII receive clock. X_rx_dv I MII receive data valid. X_rx_er I MII receive error. X_rxd[3:0] I MII receive data. X_crs I MII carrier sense. X_col I MII collision detect. X_mdc O MII management data clock. X_mdio I/O MII management data input / output. X_phy_linksts I PHY link status. X_pdn_phy O PHY power down.

N1213 ICE X_ick I ICE clock input. X_ims I ICE mode select. X_id IO ICE data. X_idi I ICE data input. X_extgoice I External device enters ICE after de-active reset. X_ntrst I Not test reset. Active LOW reset signal for the boundary scan logic. X_dbgack O When HIGH, this signal indicates the CPU is in debug state.

CFC I/F X_cfc_ncd1 I CFC card detect 1. X_cfc_ncd2 I CFC card detect 2. X_cfc_rdy I CFC ready. X_cfc_nwait I CFC wait. X_cfc_niois16 I CFC IO select 16. X_cfc_addr[10:0] O CFC address bus. X_cfc_nreg O CFC register select. X_cfc_noe O CFC output enable. X_cfc_new O CFC write enable. X_cfc_nce[1:0] O CFC card enable. X_cfc_niord O CFC I/O read. X_cfc_niowr O CFC I/O write. X_cfc_reset O CFC reset. X_cfc_data[15:0] IO CFC data bus.

GPIO X_gpio[9:0][24:22] IO General purpose I/O.

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Signal Name Dir. Description I²C

X_scl IO I²C clock.

X_sda IO I²C data.

INTC X_hwint0 ~X_hwint3 I Interrupt input for extended AHB devices. X_hwint4, X_hwint5 I Interrupt input for extended AHB devices.

PWM X_pwm[1:0]/GPIO[31,30] IO Pulse width modulation channels 0 and 1.

MMC/SD X_sd_cd I Card detect signal derived from connector. X_sd_wp I Card write protect signal derived from connector. X_sd_clk O Card clock. X_sd_cmd_rsp IO Commands are sent from the host controller to the card and reponses vice versa. X_sd_dat[3:0] IO Data line.

SSP X_ssprxd I Synchronous serial port receive. X_ssptxd O Synchronous serial port transmit. X_sspsclk IO Synchronous serial port clock. X_sspfs IO Synchronous serial port frame. X_GPIO[25]/X_sspextclkin I Synchronous serial port external clock.

I²S / AC97 X_ssp2rxd/X_ac97rxd I I²S data in / AC97 audio port data in.

X_ssp2txd/X_ac97txd O I²S data out / AC97 audio port data out.

X_ssp2sclk/X_ac97sclk IO I²S bit clock / AC97 audio port bit clock.

X_ssp2fs/X_ac97fs IO I²S sync / AC97 audio port sync.

X_ssp2_resetn/X_ac97_resetn O I²S system clock / AC97 audio port reset signal.

X_GPIO[26]/X_ac97clkout O AC97 24.4576 MHz clock out. BTUART

X_sin2 I BTUART receive. X_sout2 O BTUART transmit. X_ncts2 I BTUART clear to send. X_nrts2 O BTUART2 request to send.

STUART X_sin4 I STUART receive. X_sout4 O STUART transmit.

AHB Bus

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Signal Name Dir. Description X_hm[6:5]_hbusreq I Bus request. X_hm[6:5]_hgrant O Bus grant. X_hsplit[6:1] I Split completion request. X_hclk I AHB bus clock feedback. X_hmaster[2:0] O Master number. X_hmastlock O Locked sequence. X_hs[18,17,15,13]_hsel O Slave select. X_hclkout O AHB bus clock output. X_hready IO Transfer done. X_hdata[31:0] IO Data bus. X_haddr[31:0] IO Address bus. X_htrans[1:0] IO Transfer type. X_hresp[1:0] IO Transfer response. X_hwrite IO Transfer direction. X_hburst[2:0] IO Burst type. X_hsize[2:0] IO Transfer size. X_hreset_b O AHB bus reset. Active LOW. Miscellaneous X_cpu_mode I Reserved for Andes internal use; Not connected (NC)

X_OM I Reserved for Andes internal use; Not connected (NC)

X_default_endian I Reserved for Andes internal use; Not connected (NC)

X_BSE I Reserved for Andes internal use; Not connected (NC)

Power Management X_rst_b I Hard reset. Active LOW. X_reset_b O Reset output. Active LOW. X_oschin I High frequency oscillator input (5 – 10 MHz). X_oschout O High frequency oscillator output (5 – 10 MHz). X_osclin I Low frequency crystal input (32.768 KHz). X_osclout O Low frequency crystal output (32.768 KHz). X_pwren O Power enable for the power supply. X_powerlow_b I Power low (battery low). Active LOW. X_powerok I Power ok (main power ok). X_osc_dis I Test enable (disable OSCH / OSCL pad). X_por_b I Power-On-Reset. Active LOW.

Power and Ground Pins

V1 SUP Positive supply for all I/O pins. Must be connected to the common 3.3v supply on the PCB.

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Signal Name Dir. Description

V2 SUP Positive supply for internal logic. Must be connected to the low voltage 1.2v supply on the PCB.

GND SUP Ground supply for all I/O pins and internal logic. Must be connected to the common ground plane on the PCB.

VCC12A SUP Positive supply for the PLLs. Must be connected to the low voltage 1.2v supply on the PCB.

GNDA SUP Grounded supply for the PLLs. Must be connected to the common ground plane on the PCB.

VCC12I SUP Positive supply for the oscillators. Must be connected to the 1.2v supply the sub-battery provides.

GNDI SUP Grounded supply for the oscillators. Must be connected to the ground the sub-battery provides.

VCC3Alive SUP Positive supply for active I/O pins. Must be connected to the 3.3v supply the sub-battery provides.

VCC12Alive SUP Positive supply for active internal logic. Must be connected to the 1.2v supply the sub-battery provides.

GNDAlive SUP Grounded supply for active I/O pins and internal logic. Must be connected to the ground the sub-battery provides.

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BGA Pin Assignments

Table 2 and Table 3 show the pin assignments for the ball grid array (BGA).

Table 2. BGA Pin Assignments (I).

1 2 3 4 5 6 7 8 9 10 11 12 13

A X_ntrst NC NC NC X_reset_b X_hwint[2] X_hdata[3] X_hdata[9] X_hdata[15] X_hdata[20] X_hdata[26] X_haddr[0] X_haddr[6]

B X_idi X_ims NC NC NC X_hwint[3] X_hdata[2] X_hdata[8] X_hdata[14] X_hdata[19] X_hdata[25] X_hdata[31] X_haddr[5]

C X_ick X_id X_extgoice NC NC X_hwint[4] X_hdata[1] X_hdata[7] X_hdata[13] GND X_hdata[24] X_hdata[30] X_haddr[4]

D X_dbgack X_cpu_mode X_gpio[10] GND NC X_hwint[5] X_hdata[0] X_hdata[6] X_hdata[12] X_hdata[18] X_hdata[23] X_hdata[29] X_haddr[3]

E X_gpio[13] X_gpio[11] X_gpio[14] X_gpio[12] X_gpio[15] X_rst_b X_hwint[0] X_hdata[5] X_hdata[11] X_hdata[17] X_hdata[22] X_hdata[28] X_haddr[2]

F VCC12I X_oschin X_oschio GNDI VCC12I X_osclin X_hwint[1] X_hdata[4] X_hdata[10] X_hdata[16] X_hdata[21] X_hdata[27] X_haddr[1]

G X_osclio GNDI X_pwren X_powerlow_b X_powerok VCC3Alive

H X_osc_dis GNDAlive X_gpio[0] VCC12Alive X_gpio[1] GNDAlive

J X_gpio[2] X_gpio[3] X_gpio[4] X_gpio[5] X_gpio[6] X_gpio[7] V1 V1 V1 V1 V1

K X_gpio[8] X_gpio[9] GND X_por_b X_sdram_cke X_hclk V1

L X_hclkout X_sdclk[0] X_sdclk[1] X_sdclk[2] X_sdclk[3] NC V1 GND GND GND

M NC NC NC NC X_smc_be_b[3] VCC12A V1 GND GND GND

N GNDA X_smc_be_b[2] X_smc_be_b[1] X_smc_be_b[0] X_smc_we_b X_smc_oe_b V2 GND GND GND

P X_smc_cs_b[3] X_smc_cs_b[2] X_smc_cs_b[1] VCC12A GNDA X_smc_cs_b[0] V2 GND GND GND

R X_memdata[31] X_memdata[30] X_memdata[29] X_memdata[28] X_memdata[27] X_memdata[26] V2 GND GND GND

T X_memdata[25] X_memdata[24] GND X_memaddr[24] X_memaddr[23] X_memaddr[22] V1 GND GND GND

U X_memaddr[21] X_memaddr[20] X_memaddr[19] X_memaddr[18] X_memaddr[17] X_memaddr[16] V1

V X_memaddr[15] X_sdram_dqm[3

]

X_sdram_dqm[2] X_memaddr[14] X_memaddr[13] X_memaddr[12] V1 V2 V2 V2 V1

W X_memaddr[11] X_memaddr[10] X_memaddr[9] X_memaddr[8] X_memaddr[7] X_memaddr[6]

Y X_memdata[23] X_memdata[22] X_memdata[21] X_memdata[20] X_memdata[19] X_memdata[18]

AA X_memdata[17] X_memdata[16] X_sdram_cs_b[3] X_sdram_cs_b[2] X_sdram_cs_b[1] X_memdata[1] X_cld[23] X_clac X_cld[3] X_cld[9] X_cld[15] NC X_crs

AB X_sdram_cs_b[0] GND X_sdram_we_b X_sdram_cas_b GND X_memdata[2] X_cld[22] GND X_cld[2] X_cld[8] X_cld[14] X_cld[19] X_col

AC X_sdram_ras_b X_memdata[15] X_memdata[14] X_memaddr[0] X_memdata[7] X_memdata[3] X_cld[21] X_clfp X_cld[1] X_cld[7] X_cld[13] X_cld[18] X_rx_dv

AD X_memdata[13] X_memdata[12] X_memaddr[4] X_memaddr[1] X_sdram_dqm[0] X_memdata[4] X_cld[20] X_cllp X_cld[0] X_cld[6] X_cld[12] GND X_rx_er

AE X_memdata[11] GND X_memaddr[5] X_memaddr[2] GND X_memdata[5] X_clcdclk GND X_clpower X_cld[5] X_cld[11] X_cld[17] NC

AF X_memdata[10] X_memdata[9] X_memdata[8] X_memaddr[3] X_sdram_dqm[1] X_memdata[6] X_memdata[0] X_clcp X_clle X_cld[4] X_cld[10] X_cld[16] NC

AG101


Table 3. BGA Pin Assignments (II).

14 15 16 17 18 19 20 21 22 23 24 25 26

A X_haddr[12] X_haddr[18] X_haddr[24] X_haddr[30] X_hburst[1] X_hsize[0] NC NC X_hsplit1 X_hsplit5 NC NC NC

B X_haddr[11] X_haddr[17] X_haddr[23] X_haddr[29] X_hburst[2] X_hsize[1] NC NC X_hmastlock X_hsplit4 X_hsplit6 NC NC

C X_haddr[10] X_haddr[16] X_haddr[22] X_haddr[28] GND X_hsize[2] X_hm6_hbusreq GND X_hmaster[0] X_hsplit3 GND NC X_hreset_b

D X_haddr[9] X_haddr[15] X_haddr[21] X_haddr[27] X_htrans[0] X_hresp[0] X_hm5_hbusreq NC X_hmaster[1] X_hsplit2 X_BSE X_default_endian X_OM

E X_haddr[8] X_haddr[14] X_haddr[20] X_haddr[26] X_htrans[1] X_hresp[1] X_hready X_hm6_hgrant X_hmaster[2] NC X_hs13_hsel X_hs15_hsel X_hs17_hsel

F X_haddr[7] X_haddr[13] X_haddr[19] X_haddr[25] X_haddr[31] X_hburst[0] X_hwrite X_hm5_hgrant X_hs18_hsel NC GND NC NC

G NC NC NC NC NC NC

H NC NC NC NC NC NC

J V1 V1 V1 V1 V1 X_nrts2 X_ncts2 X_sout2 X_sin2 X_sout4 X_sin4

K V2 X_gpio[25] GND X_ssp2_resetn X_ssp2fs GND X_ssp2rxd

L GND GND GND V2 X_ssp2sclk X_ssp2txd X_gpio[26] X_sspsclk X_ssprxd X_ssptxd

M GND GND GND V2 X_sspfs NC NC NC NC NC

N GND GND GND V2 NC GND X_sda X_scl GND X_sd_cd

P GND GND GND V2 X_sd_dat2 X_sd_dat3 X_sd_cmd_rsp X_sd_clk X_sd_dat0 X_sd_dat1

R GND GND GND V2 X_sd_wp X_cfc_ncd2 X_cfc_data[10] X_cfc_niois16 X_cfc_data[9] X_cfc_data[2]

T GND GND GND V2 X_cfc_data[8] GND X_cfc_data[1] X_cfc_data[0] GND X_cfc_addr[0]

U V1 X_cfc_nreg X_cfc_addr[1] X_cfc_addr[2] X_cfc_nwait X_cfc_addr[3] X_cfc_reset

V V1 V2 V2 V2 V1 X_cfc_addr[4] X_cfc_addr[5] X_cfc_addr[6] X_cfc_rdy X_cfc_addr[7] X_cfc_nwe

W X_cfc_addr[8] GND X_cfc_niowr X_cfc_addr[9] GND X_cfc_niord

Y X_cfc_noe X_cfc_addr[10] X_cfc_nce[1] X_cfc_nce[0] X_cfc_data[15] X_cfc_data[7]

AA X_rxd[3] X_txd[1] X_u_vbus X_u_data[5] X_u_data[12] X_u_data[15] X_u_linesta[0] X_cfc_data[14] X_cfc_data[6] GNDA X_cfc_data[13] VCC12A X_cfc_data[5]

AB X_rxd[2] X_txd[0] X_sof X_u_data[3] X_u_data[9] GND X_u_rxerr X_u_opmode[0] GND X_cfc_data[12] X_cfc_data[4] GND X_cfc_data[11]

AC X_rxd[1] X_tx_en X_pdn_phy X_u_data[4] X_u_data[10] X_u_data[14] X_u_linesta[1] X_u_xcvrsel X_u_rxact X_cfc_data[3] X_cfc_ncd1 X_gpio[24] X_gpio[23]

AD X_rxd[0] X_tx_clk X_txd[3] X_u_data[1] X_u_data[8] X_u_data[13] X_u_txrdy X_u_termsel X_u_usbrst X_u_vctl[2] GNDA X_gpio[22] VCC12A

AE X_phy_linksts X_mdc GND X_u_data[2] X_u_data[7] GND X_u_validh X_u_susp_b GND X_u_txval X_u_vctl[0] GND X_gpio[31]

AF X_rx_clk X_mdio X_txd[2] X_u_data[0] X_u_data[6] X_u_data[11] X_u_vctl[1] X_u_rxval X_u_opmode[1] X_u_vctload_b X_u_vctl[3] X_u_clk X_gpio[30]

AG101


21

3 Memory Map This chapter describes the memory maps and the chip configuration registers of the AG101.

Memory Map

The base address for each peripheral register address is listed in the following AG101 memory map. The exact

address description for each peripheral is denoted on the side.

AG101


S R A M /R O M /F LA S H

R eserved

0x0000 0000

0 x07 F F F F F F

128 M B

0x0800 0000

0x1000 0000

128 M B

0x5000 0000

S D R A M

0 x0F F F F F F F

1G B

R eserved

0 x4F F F F F F F

0 x8F F F F F F F

1G B

0x9000 0000

0x900 F F F F F

A H B C ontro lle r0x9010 0000

0x901 F F F F F

S M C R egis te r0x9020 0000

0x902 F F F F F

S D R A M C R egis te r0x9030 0000

0x903 F F F F F

D M A C R eg is te r0x9040 0000

0x904 F F F F F

A H B to A P B B ridgeR eg is ter0x9050 0000

0x905 F F F F F

LC D C0x9060 0000

0x906 F F F F F

R eserved0x9070 0000

0x908 F F F F F

M A C 0x9090 0000

0x909 F F F F F

E xterna l A H B D ev ice(X _hs13 _hse l)0 x90 A 0 0000

0 x90 A F F F F F

U S B 2 .0 D ev ice0 x90 B 0 0000

0 x90 B F F F F F

E xterna l A H B D ev ice(X _hs15 _hse l)

R eserved

0 x90 C 0 0000

0 x90 C F F F F F

0 x90 D 0 0000

0 x90 D F F F F F

E xterna l A H B D ev ice(X _hs17 _hse l)0 x90 E 0 0000

0 x90 E F F F F F

E xterna l A H B D ev ice(X _hs18 _hse l)0x90 F 0 0000

0 x90 F F F F F F


0x910 F F F F F

E xterna l A H B D ev ice(X _hs19 _hse l)0x9200 0000

0x920 F F F F F

A P B D ev ices

R eserved 1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

1 M B

128 M B


256 M B


128 M B


0 x97 F F F F F F

0x9800 0000

0 x9F F F F F F F

0 xA 000 0000

0xA F F F F F F F

0 xB 000 0000

0 xB 7 F F F F F F

R eserved0 x9800 0000

0x980 F F F F F

P M U0 x9810 0000

0x981 F F F F F


0x982 F F F F F

B T U A R T0 x9830 0000

0x983 F F F F F

T IM E R0 x9840 0000

0x984 F F F F F

W D T0 x9850 0000

0x985 F F F F F

R T C0 x9860 0000

0x986 F F F F F

G P IO0 x9870 0000

0x987 F F F F F

IN T C0 x9880 0000

0x988 F F F F F


0x989 F F F F F

I2C0 x98 A 0 0000

0 x98 A F F F F F

S S P0 x98 B 0 0000

0 x98 B F F F F F

R eserved0x98 C 0 0000

0 x98 C F F F F F

C F C0x98 D 0 0000

0 x98 D F F F F F

S D C0x98 E 0 0000

0 x98 E F F F F F

R eserved0 x98 F 0 0000

0 x98 F F F F F F


0x990 F F F F F

P W M0 x9910 0000

0x991 F F F F F


0x992 F F F F F


0x993 F F F F F

I2S /A C 970 x9940 0000

0x994 F F F F F


0x995 F F F F F

S T U A R T0 x9960 0000

0x996 F F F F F

R eserved

0 x9970 0000

0 x9F F F F F F F

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

1M B

Figure 2. MCU Physical Memory Map.

AG101


23

Internal Registers

The internal registers in the AG101 are listed in Table 4.

Table 4. AG101 Internal Registers Sorted by Address.

Module Name Address Name Description AHB Controller 0x90100000 + 0x00 Base/Size register AHB slave 0 Base/Size Register AHB Controller 0x90100000 + 0x04 Base/Size register AHB slave 1 Base/Size Register AHB Controller 0x90100000 + 0x08 Base/Size register AHB slave 2 Base/Size Register AHB Controller 0x90100000 + 0x0C Base/Size register AHB slave 3 Base/Size Register AHB Controller 0x90100000 + 0x10 Base/Size register AHB slave 4 Base/Size Register AHB Controller 0x90100000 + 0x14 Base/Size register AHB slave 5 Base/Size Register AHB Controller 0x90100000 + 0x18 Base/Size register AHB slave 6 Base/Size Register AHB Controller 0x90100000 + 0x1C Base/Size register AHB slave 7 Base/Size Register AHB Controller 0x90100000 + 0x24 Base/Size register AHB slave 9 Base/Size Register AHB Controller 0x90100000 + 0x30 Base/Size register AHB slave 12 Base/Size Register AHB Controller 0x90100000 + 0x34 Base/Size register AHB slave 13 Base/Size Register AHB Controller 0x90100000 + 0x38 Base/Size register AHB slave 14 Base/Size Register AHB Controller 0x90100000 + 0x3C Base/Size register AHB slave 15 Base/Size Register AHB Controller 0x90100000 + 0x44 Base/Size register AHB slave 17 Base/Size Register AHB Controller 0x90100000 + 0x48 Base/Size register AHB slave 18 Base/Size Register AHB Controller 0x90100000 + 0x4C Base/Size register AHB slave 19 Base/Size Register AHB Controller 0x90100000 + 0x54 Base/Size register AHB slave 21 Base/Size Register AHB Controller 0x90100000 + 0x58 Base/Size register AHB slave 22 Base/Size Register AHB Controller 0x90100000 + 0x80 PLevel Priority Control Register AHB Controller 0x90100000 + 0x84 TransCtl Transfer Control Register AHB Controller 0x90100000 + 0x88 IntrSts Interrupt Control Register SMC 0x90200000 + 0x00 MB0CR Memory Bank 0 Configuration Register SMC 0x90200000 + 0x04 MB0TPR Memory Bank 0 Timing Parameter Register SMC 0x90200000 + 0x08 MB1CR Memory Bank 1 Configuration Register SMC 0x90200000 + 0x0C MB1TPR Memory Bank 1 Timing Parameter Register SMC 0x90200000 + 0x10 MB2CR Memory Bank 2 Configuration Register SMC 0x90200000 + 0x14 MB2TPR Memory Bank 2 Timing Parameter Register SMC 0x90200000 + 0x18 MB3CR Memory Bank 3 Configuration Register SMC 0x90200000 + 0x1C MB3TPR Memory Bank 3 Timing Parameter Register SMC 0x90200000 + 0x40 SSR Shadow Status Register SDRAMC 0x90300000 + 0x00 STP0 SDRAM Timing Parameter 0 SDRAMC 0x90300000 + 0x04 STP1 SDRAM Timing Parameter 1 SDRAMC 0x90300000 + 0x08 SCR SDRAM Configuration Register

AG101


Module Name Address Name Description SDRAMC 0x90300000 + 0x0C EB0BSR External Bank0 Base / Size Register SDRAMC 0x90300000 + 0x10 EB1BSR External Bank1 Base / Size Register SDRAMC 0x90300000 + 0x14 EB2BSR External Bank2 Base / Size Register SDRAMC 0x90300000 + 0x18 EB3BSR External Bank3 Base / Size Register SDRAMC 0x90300000 + 0x34 ATOC Arbiter Time Out Cycles DMAC 0x90400000 + 0x00 INT Interrupt Status Register DMAC 0x90400000 + 0x04 INT_TC Interrupt for Terminal Count Status Register DMAC 0x90400000 + 0x08 INT_TC_CLR Interrupt for Terminal Count Clear Register DMAC 0x90400000 + 0x0C INT_ERR/ABT Interrupt for Error/Abort Status Register DMAC 0x90400000 + 0x10 INT_ERR/ABT_CLRR Interrupt for Error/Abort Clear Register DMAC 0x90400000 + 0x14 TC Terminal Count Status Register DMAC 0x90400000 + 0x18 ERR/ABT Error/Abort Status Register DMAC 0x90400000 + 0x1C CH_EN Channel Enable Status Register DMAC 0x90400000 + 0x20 CH_BUSY Channel Busy Register Status Register DMAC 0x90400000 + 0x24 CSR Main Configuration Status Register DMAC 0x90400000 + 0x28 SYNC Sync Register DMAC 0x90400000 + 0x100 C0_CSR Channel 0 Control Register DMAC 0x90400000 + 0x104 C0_CFG Channel 0 Configuration Register DMAC 0x90400000 + 0x108 C0_SrcAddr Channel 0 Source Register DMAC 0x90400000 + 0x10C C0_DstAddr Channel 0 Destination Register DMAC 0x90400000 + 0x110 C0_LLP Channel 0 Linked List Pointer Register DMAC 0x90400000 + 0x114 C0_SIZE Channel 0 Transfer Size Register DMAC 0x90400000 + 0x120 C1_CSR Channel 1 Control Register DMAC 0x90400000 + 0x124 C1_CFG Channel 1 Configuration Register DMAC 0x90400000 + 0x128 C1_SrcAddr Channel 1 Source Register DMAC 0x90400000 + 0x12C C1_DstAddr Channel 1 Destination Register DMAC 0x90400000 + 0x130 C1_LLP Channel 1 Linked List Pointer Register DMAC 0x90400000 + 0x134 C1_SIZE Channel 1 Transfer Size Register DMAC 0x90400000 + 0x140 C2_CSR Channel 2 Control Register DMAC 0x90400000 + 0x144 C2_CFG Channel 2 Configuration Register DMAC 0x90400000 + 0x148 C2_SrcAddr Channel 2 Source Register DMAC 0x90400000 + 0x14C C2_DstAddr Channel 2 Destination Register DMAC 0x90400000 + 0x150 C2_LLP Channel 2 Linked List Pointer Register DMAC 0x90400000 + 0x154 C2_SIZE Channel 2 Transfer Size Register DMAC 0x90400000 + 0x160 C3_CSR Channel 3 Control Register DMAC 0x90400000 + 0x164 C3_CFG Channel 3 Configuration Register DMAC 0x90400000 + 0x168 C3_SrcAddr Channel 3 Source Register

AG101


25

Module Name Address Name Description DMAC 0x90400000 + 0x16C C3_DstAddr Channel 3 Destination Register DMAC 0x90400000 + 0x170 C3_LLP Channel 3 Linked List Pointer Register DMAC 0x90400000 + 0x174 C3_SIZE Channel 3 Transfer Size Register APB Bridge 0x90500000 + 0x04 Base/Size register APB Slave 1 Base/Size Register APB Bridge 0x90500000 + 0x08 Base/Size register APB Slave 2 Base/Size Register APB Bridge 0x90500000 + 0x0C Base/Size register APB Slave 3 Base/Size Register APB Bridge 0x90500000 + 0x10 Base/Size register APB Slave 4 Base/Size Register APB Bridge 0x90500000 + 0x14 Base/Size register APB Slave 5 Base/Size Register APB Bridge 0x90500000 + 0x18 Base/Size register APB Slave 6 Base/Size Register APB Bridge 0x90500000 + 0x20 Base/Size register APB Slave 8 Base/Size Register APB Bridge 0x90500000 + 0x2C Base/Size register APB Slave 11 Base/Size Register APB Bridge 0x90500000 + 0x40 Base/Size register APB Slave 16 Base/Size Register APB Bridge 0x90500000 + 0x44 Base/Size register APB Slave 17 Base/Size Register APB Bridge 0x90500000 + 0x48 Base/Size register APB Slave 18 Base/Size Register APB Bridge 0x90500000 + 0x4C Base/Size register APB Slave 19 Base/Size Register APB Bridge 0x90500000 + 0x50 Base/Size register APB Slave 20 Base/Size Register APB Bridge 0x90500000 + 0x54 Base/Size register APB Slave 21 Base/Size Register APB Bridge 0x90500000 + 0x58 Base/Size register APB Slave 22 Base/Size Register APB Bridge 0x90500000 + 0x5C Base/Size register APB Slave 23 Base/Size Register APB Bridge 0x90500000 + 0x80 ASrcAddr Source address for DMA channel A APB Bridge 0x90500000 + 0x84 ADstAddr Destination address for DMA channel A APB Bridge 0x90500000 + 0x88 ACyc Cycles for DMA channel A APB Bridge 0x90500000 + 0x8C ACmdR Command register for DMA channel A APB Bridge 0x90500000 + 0x90 BSrcAddr Source address for DMA channel B APB Bridge 0x90500000 + 0x94 BDstAddr Destination address for DMA channel B APB Bridge 0x90500000 + 0x98 BCyc Cycles for DMA channel B APB Bridge 0x90500000 + 0x9C BCmdR Command register for DMA channel B APB Bridge 0x90500000 + 0xA0 CSrcAddr Source address for DMA channel C APB Bridge 0x90500000 + 0xA4 CDstAddr Destination address for DMA channel C APB Bridge 0x90500000 + 0xA8 CCyc Cycles for DMA channel C APB Bridge 0x90500000 + 0xAC CCmdR Command register for DMA channel C APB Bridge 0x90500000 + 0xB0 DSrcAddr Source address for DMA channel D APB Bridge 0x90500000 + 0xB4 DDstAddr Destination address for DMA channel D APB Bridge 0x90500000 + 0xB8 DCyc Cycles for DMA channel D APB Bridge 0x90500000 + 0xBC DCmdR Command register for DMA channel D LCDC 0x90600000 + 0x00 LCD Timing0 LCD horizontal timing control LCDC 0x90600000 + 0x04 LCDTiming1 LCD vertical timing control LCDC 0x90600000 + 0x08 LCDTiming2 LCD clock and signal polarity control

AG101


Module Name Address Name Description LCDC 0x90600000 + 0x10 LCDFrameBase LCD panel frame base address LCDC 0x90600000 + 0x18 LCDIntEnable LCD interrupt enable mask LCDC 0x90600000 + 0x1C LCDControl LCD panel pixel parameters LCDC 0x90600000 + 0x20 LCDInClr LCD interrupt clear LCDC 0x90600000 + 0x24 LCDInterrupt LCD masked interrupts LCDC 0x90600000 + 0x34 OSDControl0 OSD scaling and dimension control LCDC 0x90600000 + 0x38 OSDControl1 OSD position control LCDC 0x90600000 + 0x3C OSDControl2 OSD foreground color control LCDC 0x90600000 + 0x40 OSDControl3 OSD background color control LCDC 0x90600000 + 0x44 GPIOControl GPI/GPO control

LCDC 0x90600000 + 0x200~ 0x90600000 + 0x3FC

PaletteWritePort LCD palette RAM write access port

LCDC 0x90600000 + 8000~ 0x90600000 + 0xBFFC

OSDFontWritePort OSD font database write access port

LCDC 0x90600000 + 0xC000~ 0x90600000 + 0xC7FC

OSDAttributeWritePort OSD window attribute write access port

Ethernet MAC 0x90900000 + 0x00 ISR Interrupt Status Register Ethernet MAC 0x90900000 + 0x04 IMR Interrupt Mask Register Ethernet MAC 0x90900000 + 0x08 MAC_MADR MAC Most Significant Address Register Ethernet MAC 0x90900000 + 0x0C MAC_LADR MAC Least Significant Address Register Ethernet MAC 0x90900000 + 0x10 MAHT0 Multicast Address Hash Table 0 Register Ethernet MAC 0x90900000 + 0x14 MAHT1 Multicast Address Hash Table 1 Register Ethernet MAC 0x90900000 + 0x18 TXPD Transmit Poll Demand Register Ethernet MAC 0x90900000 + 0x1C RXPD Receive Poll Demand Register Ethernet MAC 0x90900000 + 0x20 TXR_BADR Transmit Ring Base Address Register Ethernet MAC 0x90900000 + 0x24 RXR_BADR Receive Ring Base Address Register Ethernet MAC 0x90900000 + 0x28 ITC Interrupt Timer Control Register Ethernet MAC 0x90900000 + 0x2C APTC Automatic Polling Timer Control Register Ethernet MAC 0x90900000 + 0x30 DBLAC DMA Burst Length and Arbitration Control RegisterEthernet MAC 0x90900000 + 0x88 MACCR MAC Control Register Ethernet MAC 0x90900000 + 0x8C MACSR MAC Status Register Ethernet MAC 0x90900000 + 0x90 PHYCR PHY Control Register Ethernet MAC 0x90900000 + 0x94 PHYWDATA PHY Write Data Register Ethernet MAC 0x90900000 + 0x98 FCR Flow Control Register Ethernet MAC 0x90900000 + 0x9C BPR Back Pressure Register Ethernet MAC 0x90900000 + 0xC4 TS Test Seed Register Ethernet MAC 0x90900000 + 0xC8 DMAFIFOS DMA/FIFO State Register

AG101


27

Module Name Address Name Description Ethernet MAC 0x90900000 + 0xCC TM Test Mode Register Ethernet MAC 0x90900000 + 0xD4 TX_MCOL/X_SCOL TX_MCOL and TX_SCOL Counter Register Ethernet MAC 0x90900000 + 0xD8 RPF / AEP RPF and AEP Counter Register Ethernet MAC 0x90900000 + 0xDC XM / PG XM and PG Counter Register Ethernet MAC 0x90900000 + 0xE0 RUNT_CNT/ TLCC RUNT_CNT and TLCC Counter Register Ethernet MAC 0x90900000 + 0xE4 CRCER_CNT/FTL_CNT CRCER_CNT and FTL_CNT Counter Register Ethernet MAC 0x90900000 + 0xE8 RLC / RCC RLC and RCC Counter Register Ethernet MAC 0x90900000 + 0xEC BROC BROC Counter Register Ethernet MAC 0x90900000 + 0xF0 MULCA MULCA Counter Register Ethernet MAC 0x90900000 + 0xF4 RP RP Counter Register Ethernet MAC 0x90900000 + 0xF8 XP XP Counter Register

USB 2.0 Device 0x90B00000 + 0x00 main_ctl Main Control Register, which performs device management for the USB.

USB 2.0 Device 0x90B00000 + 0x01 dev_adr Device Address Register, which records the latest device address.

USB 2.0 Device 0x90B00000 + 0x02 tst_ep Test Register: Endpoints’ testing control signals for debugging.

USB 2.0 Device 0x90B00000 + 0x04 frm_numb0 Frame Number Register Byte 0: Frame number register records the SOF related frame number for high speed and full speed.

USB 2.0 Device 0x90B00000 + 0x05 frm_numb1 Frame Number Register Byte 1: Frame number register records the SOF related frame number for high speed and full speed.

USB 2.0 Device 0x90B00000 + 0x06 sof_tmskb0 SOF Mask Timer Register Byte 0. USB 2.0 Device 0x90B00000 + 0x07 sof_tmskb1 SOF Mask Timer Register Byte 1.

USB 2.0 Device 0x90B00000 + 0x08 phy_tms PHY Test Mode Selector Register: Test mode selector register for PHY.

USB 2.0 Device 0x90B00000 + 0x09 vnd_ctl Vendor Defined IO Control Register: Vendor defined control signals for PHY.

USB 2.0 Device 0x90B00000 + 0x0A vnd_sta Vendor Defined IO Status Register, which reports the status of vendor defined control.

USB 2.0 Device 0x90B00000 + 0x0B cx_csr CX Configuration and Status Register. USB 2.0 Device 0x90B00000 + 0x0C ep0_dp Endpoint 0 Data Port: For Endpoint 0 data access.

USB 2.0 Device 0x90B00000 + 0x10 int_mgrp Interrupt Group Mask Register: Interrupt mask register for masking interrupt source group.

USB 2.0 Device 0x90B00000 + 0x11 int_mskb0 Interrupt Mask Register Byte 0: Interrupt mask register for masking interrupt source byte 0 register.



USB 2.0 Device 0x90B00000 + 0x14 int_mskb3 Interrupt Mask Register Byte 3: Interrupt mask

AG101


Module Name Address Name Description register for masking interrupt source byte 3 register.





USB 2.0 Device 0x90B00000 + 0x19 rx0byte_epb0 Receive Zero-length Data Packet Register Byte 0: Indicates which endpoint among Endpoints 7 to Endpoint 1 receives a zero-length data packet

USB 2.0 Device 0x90B00000 + 0x1A rx0byte_epb1 Receive Zero-length Data Packet Register Byte 1: Indicates which endpoint among Endpoints 15 to Endpoint 8 receives a zero-length data packet

USB 2.0 Device 0x90B00000 + 0x1C fempt_b0 FIFO empty Byte 0: Indicates FIFO 0 ~ FIFO 7 are fully empty

USB 2.0 Device 0x90B00000 + 0x1D fempt_b1 FIFO empty Byte 1: Indicates FIFO 8 ~ FIFO 15 are fully empty

USB 2.0 Device 0x90B00000 + 0x20 int_grp Interrupt Group Register: Interrupt source group register that indicates the interrupt for a certain group of interrupts.

USB 2.0 Device 0x90B00000 + 0x21 int_srcb0 Interrupt Source Register Byte 0: Interrupt group register for recording the interrupt sources of the endpoint 0 interrupts.

USB 2.0 Device 0x90B00000 + 0x22 int_srcb1 Interrupt Source Register Byte 1: Interrupt group register for recording the interrupt sources of the FIFO0 ~ FIFO3 OUT interrupts.




USB 2.0 Device 0x90B00000 + 0x26 int_srcb5 Interrupt Source Register Byte 5: Interrupt group register for recording the interrupt sources of the FIFO0 ~ FIFO7 IN interrupts.

USB 2.0 Device 0x90B00000 + 0x27 int_srcb6 Interrupt Source Register Byte 6: Interrupt group register for recording the interrupt sources of the FIFO8 ~ FIFO15 IN interrupts.

USB 2.0 Device 0x90B00000 + 0x28 int_srcb7 Interrupt Source Register Byte 7

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Module Name Address Name Description

USB 2.0 Device 0x90B00000 + 0x29 iso_seq_errb0 Isochronous Sequential Error Register Byte 0: Indicates which endpoint among Endpoints 7 to Endpoint 1 receives an isochronous sequential error.

USB 2.0 Device 0x90B00000 + 0x2A iso_seq_errb1 Isochronous Sequential Error Register Byte 1: Indicates which endpoint among Endpoints 15 to Endpoint 8 receives an isochronous sequential error.

USB 2.0 Device 0x90B00000 + 0x2B iso_seq_abtb0 Isochronous Sequential Abort Register Byte 0: Indicates which endpoint among Endpoints 7 to Endpoint 1 receives an isochronous sequential abort.

USB 2.0 Device 0x90B00000 + 0x2C iso_seq_abtb1 Isochronous Sequential Abort Register Byte 1: Indicates which endpoint among Endpoints 15 to Endpoint 8 receives an isochronous sequential abort.

USB 2.0 Device 0x90B00000 + 0x2D tx0byteb0

Transfer Zero-length Data Packet Register Byte 0: Indicates which endpoint among Endpoints 7 to Endpoint 1 returns a zero-length data packet to USB host.

USB 2.0 Device 0x90B00000 + 0x2E tx0byteb1

Transfer Zero-length Data Packet Register Byte 1: Indicates which endpoint among Endpoints 15 to Endpoint 8 returns a zero-length data packet to USB host.

USB 2.0 Device 0x90B00000 + 0x2F idle_cnt

Idle Counter. When the “GO_SUSP” bit of main control register is set by AP, FUSB220 will wait for a period defined in this counter, and then turn off the u_clk (drive u_susp_n to low state).

USB 2.0 Device 0x90B00000 + 0x30 ep1_map Endpoint 1 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x31 ep2_map Endpoint 2 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x32 ep3_map Endpoint 3 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x33 ep4_map Endpoint 4 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x34 ep5_map Endpoint 5 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x35 ep6_map Endpoint 6 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x36 ep7_map Endpoint 7 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x37 ep8_map Endpoint 8 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x38 ep9_map Endpoint 9 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x39 ep10_map Endpoint 10 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x3A ep11_map Endpoint 11 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x3B ep12_map Endpoint 12 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x3C ep13_map Endpoint 13 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x3D ep14_map Endpoint 14 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x3E ep15_map Endpoint 15 FIFO Mapping Register. USB 2.0 Device 0x90B00000 + 0x3F hbf_cnt HBF data byte count. USB 2.0 Device 0x90B00000 + 0x40 iep1_xpsz IN Endpoint 1 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x42 iep2_xpsz IN Endpoint 2 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x44 iep3_xpsz IN Endpoint 3 MaxPacketSize Register

AG101


Module Name Address Name Description USB 2.0 Device 0x90B00000 + 0x46 iep4_xpsz IN Endpoint 4 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x48 iep5_xpsz IN Endpoint 5 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x4A iep6_xpsz IN Endpoint 6 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x4C iep7_xpsz IN Endpoint 7 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x4E iep8_xpsz IN Endpoint 8 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x50 iep9_xpsz IN Endpoint 9 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x52 iep10_xpsz IN Endpoint 10 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x54 iep11_xpsz IN Endpoint 11 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x56 iep12_xpsz IN Endpoint 12 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x58 iep13_xpsz IN Endpoint 13 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x5A iep14_xpsz IN Endpoint 14 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x5C iep15_xpsz IN Endpoint 15 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x60 oep1_xpsz OUT Endpoint 1 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x62 oep2_xpsz OUT Endpoint 2 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x64 oep3_xpsz OUT Endpoint 3 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x66 oep4_xpsz OUT Endpoint 4 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x68 oep5_xpsz OUT Endpoint 5 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x6A oep6_xpsz OUT Endpoint 6 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x6C oep7_xpsz OUT Endpoint 7 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x6E oep8_xpsz OUT Endpoint 8 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x70 oep9_xpsz OUT Endpoint 9 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x72 oep10_xpsz OUT Endpoint 10 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x74 oep11_xpsz OUT Endpoint 11 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x76 oep12_xpsz OUT Endpoint 12 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x78 oep13_xpsz OUT Endpoint 13 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x7A oep14_xpsz OUT Endpoint 14 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x7C oep15_xpsz OUT Endpoint 15 MaxPacketSize Register USB 2.0 Device 0x90B00000 + 0x7E fifo_dma_en DMA Mode Enable Register. USB 2.0 Device 0x90B00000 + 0x80 fifo0_map FIFO 0 Mapping Register USB 2.0 Device 0x90B00000 + 0x81 fifo1_map FIFO 1 Mapping Register USB 2.0 Device 0x90B00000 + 0x82 fifo2_map FIFO 2 Mapping Register USB 2.0 Device 0x90B00000 + 0x83 fifo3_map FIFO 3 Mapping Register USB 2.0 Device 0x90B00000 + 0x84 fifo4_map FIFO 4 Mapping Register USB 2.0 Device 0x90B00000 + 0x85 fifo5_map FIFO 5 Mapping Register USB 2.0 Device 0x90B00000 + 0x86 fifo6_map FIFO 6 Mapping Register USB 2.0 Device 0x90B00000 + 0x87 fifo7_map FIFO 7 Mapping Register USB 2.0 Device 0x90B00000 + 0x88 fifo8_map FIFO 8 Mapping Register

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Module Name Address Name Description USB 2.0 Device 0x90B00000 + 0x89 fifo9_map FIFO 9 Mapping Register USB 2.0 Device 0x90B00000 + 0x8A fifo10_map FIFO 10 Mapping Register USB 2.0 Device 0x90B00000 + 0x8B fifo11_map FIFO 11 Mapping Register USB 2.0 Device 0x90B00000 + 0x8C fifo12_map FIFO 12 Mapping Register USB 2.0 Device 0x90B00000 + 0x8D fifo13_map FIFO 13 Mapping Register USB 2.0 Device 0x90B00000 + 0x8E fifo14_map FIFO 14 Mapping Register USB 2.0 Device 0x90B00000 + 0x8F fifo15_map FIFO 15 Mapping Register USB 2.0 Device 0x90B00000 + 0x90 fifo0_config FIFO 0 Configuration Register USB 2.0 Device 0x90B00000 + 0x91 fifo1_config FIFO 1 Configuration Register USB 2.0 Device 0x90B00000 + 0x92 fifo2_config FIFO 2 Configuration Register USB 2.0 Device 0x90B00000 + 0x93 fifo3_config FIFO 3 Configuration Register USB 2.0 Device 0x90B00000 + 0x94 fifo4_config FIFO 4 Configuration Register USB 2.0 Device 0x90B00000 + 0x95 fifo5_config FIFO 5 Configuration Register USB 2.0 Device 0x90B00000 + 0x96 fifo6_config FIFO 6 Configuration Register USB 2.0 Device 0x90B00000 + 0x97 fifo7_config FIFO 7 Configuration Register USB 2.0 Device 0x90B00000 + 0x98 fifo8_config FIFO 8 Configuration Register USB 2.0 Device 0x90B00000 + 0x99 fifo9_config FIFO 9 Configuration Register USB 2.0 Device 0x90B00000 + 0x9A fifo10_config FIFO 10 Configuration Register USB 2.0 Device 0x90B00000 + 0x9B fifo11_config FIFO 11 Configuration Register USB 2.0 Device 0x90B00000 + 0x9C fifo12_config FIFO 12 Configuration Register USB 2.0 Device 0x90B00000 + 0x9D fifo13_config FIFO 13 Configuration Register USB 2.0 Device 0x90B00000 + 0x9E fifo14_config FIFO 14 Configuration Register USB 2.0 Device 0x90B00000 + 0x9F fifo15_config FIFO 15 Configuration Register USB 2.0 Device 0x90B00000 + 0xA0 fifo0_inst FIFO 0 Instruction Register USB 2.0 Device 0x90B00000 + 0xA1 fifo1_inst FIFO 1 Instruction Register USB 2.0 Device 0x90B00000 + 0xA2 fifo2_inst FIFO 2 Instruction Register USB 2.0 Device 0x90B00000 + 0xA3 fifo3_inst FIFO 3 Instruction Register USB 2.0 Device 0x90B00000 + 0xA4 fifo4_inst FIFO 4 Instruction Register USB 2.0 Device 0x90B00000 + 0xA5 fifo5_inst FIFO 5 Instruction Register USB 2.0 Device 0x90B00000 + 0xA6 fifo6_inst FIFO 6 Instruction Register USB 2.0 Device 0x90B00000 + 0xA7 fifo7_inst FIFO 7 Instruction Register USB 2.0 Device 0x90B00000 + 0xA8 fifo8_inst FIFO 8 Instruction Register USB 2.0 Device 0x90B00000 + 0xA9 fifo9_inst FIFO 9 Instruction Register USB 2.0 Device 0x90B00000 + 0xAA fifo10_inst FIFO 10 Instruction Register USB 2.0 Device 0x90B00000 + 0xAB fifo11_inst FIFO 11 Instruction Register USB 2.0 Device 0x90B00000 + 0xAC fifo12_inst FIFO 12 Instruction Register USB 2.0 Device 0x90B00000 + 0xAD fifo13_inst FIFO 13 Instruction Register USB 2.0 Device 0x90B00000 + 0xAE fifo14_inst FIFO 14 Instruction Register

AG101


Module Name Address Name Description USB 2.0 Device 0x90B00000 + 0xAF fifo15_inst FIFO 15 Instruction Register USB 2.0 Device 0x90B00000 + 0xB0 fifo0_bc FIFO 0 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xB1 fifo1_bc FIFO 1 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xB2 fifo2_bc FIFO 2 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xB3 fifo3_bc FIFO 3 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xB4 fifo4_bc FIFO 4 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xB5 fifo5_bc FIFO 5 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xB6 fifo6_bc FIFO 6 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xB7 fifo7_bc FIFO 7 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xB8 fifo8_bc FIFO 8 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xB9 fifo9_bc FIFO 9 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xBA fifo10_bc FIFO 10 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xBB fifo11_bc FIFO 11 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xBC fifo12_bc FIFO 12 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xBD fifo13_bc FIFO 13 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xBE fifo14_bc FIFO 14 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xBF fifo15_bc FIFO 15 Byte-Count Register. USB 2.0 Device 0x90B00000 + 0xC0 fifo0_dp FIFO 0 Data Port USB 2.0 Device 0x90B00000 + 0xC4 fifo1_dp FIFO 1 Data Port USB 2.0 Device 0x90B00000 + 0xC8 fifo2_dp FIFO 2 Data Port USB 2.0 Device 0x90B00000 + 0xCC fifo3_dp FIFO 3 Data Port USB 2.0 Device 0x90B00000 + 0xD0 fifo4_dp FIFO 4 Data Port USB 2.0 Device 0x90B00000 + 0xD4 fifo5_dp FIFO 5 Data Port USB 2.0 Device 0x90B00000 + 0xD8 fifo6_dp FIFO 6 Data Port USB 2.0 Device 0x90B00000 + 0xDC fifo7_dp FIFO 7 Data Port USB 2.0 Device 0x90B00000 + 0xE0 fifo8_dp FIFO 8 Data Port USB 2.0 Device 0x90B00000 + 0xE4 fifo9_dp FIFO 9 Data Port USB 2.0 Device 0x90B00000 + 0xE8 fifo10_dp FIFO 10 Data Port USB 2.0 Device 0x90B00000 + 0xEC fifo11_dp FIFO 11 Data Port USB 2.0 Device 0x90B00000 + 0xF0 fifo12_dp FIFO 12 Data Port USB 2.0 Device 0x90B00000 + 0xF4 fifo13_dp FIFO 13 Data Port USB 2.0 Device 0x90B00000 + 0xF8 fifo14_dp FIFO 14 Data Port USB 2.0 Device 0x90B00000 + 0xFC fifo15_dp FIFO 15 Data Port PMU 0x98100000 + 0x00 IDNMBR0 ID Number0 Register PMU 0x98100000 + 0x08 OSCCR OSC Control Register PMU 0x98100000 + 0x0C PMODE Power Mode Register PMU 0x98100000 + 0x10 PCR Power Manager Control Register

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Module Name Address Name Description PMU 0x98100000 + 0x14 PED Power Manager Edge Detect PMU 0x98100000 + 0x18 PEDSR Power Manager Edge Detect Status Register PMU 0x98100000 + 0x20 PMSR Power Manager Status Register PMU 0x98100000 + 0x24 PGSR Power Manager GPIO Sleep State Register PMU 0x98100000 + 0x28 MFPSR Multi-Function Port Setting Register PMU 0x98100000 + 0x2C MISC EBI Turn-Around Disable PMU 0x98100000 + 0x30 PDLLCR0 PLL/DLL Control Register 0 PMU 0x98100000 + 0x34 PDLLCR1 PLL/DLL Control Register 1 PMU 0x98100000 + 0x38 AHBMCLKOFF AHB Module Clock Off Control Register PMU 0x98100000 + 0x3C APBMCLKOFF APB Module Clock Off Control Register PMU 0x98100000 + 0x40 DCSRCR0 Driving Capability and Slew Rate Control Register0 PMU 0x98100000 + 0x44 DCSRCR1 Driving Capability and Slew Rate Control Register1 PMU 0x98100000 + 0x48 DCSRCR2 Driving Capability and Slew Rate Control Register2 PMU 0x98100000 + 0x4C SDRAMHTC SDRAM Signal Hold Time Control PMU 0x98100000 + 0x50 PSPR0 Power Manager Scratch Pad Register 0 PMU 0x98100000 + 0x54 PSPR1 Power Manager Scratch Pad Register 1 PMU 0x98100000 + 0x58 PSPR2 Power Manager Scratch Pad Register 2 PMU 0x98100000 + 0x5C PSPR3 Power Manager Scratch Pad Register 3 PMU 0x98100000 + 0x60 PSPR4 Power Manager Scratch Pad Register 4 PMU 0x98100000 + 0x64 PSPR5 Power Manager Scratch Pad Register 5 PMU 0x98100000 + 0x68 PSPR6 Power Manager Scratch Pad Register 6 PMU 0x98100000 + 0x6C PSPR7 Power Manager Scratch Pad Register 7 PMU 0x98100000 + 0x70 PSPR8 Power Manager Scratch Pad Register 8 PMU 0x98100000 + 0x74 PSPR9 Power Manager Scratch Pad Register 9 PMU 0x98100000 + 0x78 PSPR10 Power Manager Scratch Pad Register 10 PMU 0x98100000 + 0x7C PSPR11 Power Manager Scratch Pad Register 11 PMU 0x98100000 + 0x80 PSPR12 Power Manager Scratch Pad Register 12 PMU 0x98100000 + 0x84 PSPR13 Power Manager Scratch Pad Register 13 PMU 0x98100000 + 0x88 PSPR14 Power Manager Scratch Pad Register 14 PMU 0x98100000 + 0x8C PSPR15 Power Manager Scratch Pad Register 15

PMU 0x98100000 + 0x90 REQACKCFG AHB DMA REQ/ACK Connection Configuration Status

PMU 0x98100000 + 0x9C JPSET Jump Setting Status PMU 0x98100000 + 0xA0 CFC_REQACKCFG CFC REQ/ACK Connection Configuration PMU 0x98100000 + 0xA4 SSP1_REQACKCFG SSP1 REQ/ACK Connection Configuration PMU 0x98100000 + 0xA8 UART1_TX_REQACKCFG UART1 TX REQ/ACK Connection Configuration PMU 0x98100000 + 0xAC UART1_RX_REQACKCFG UART1 RX REQ/ACK Connection Configuration PMU 0x98100000 + 0xB0 UART2_TX_REQACKCFG UART2 TX REQ/ACK Connection Configuration

AG101


Module Name Address Name Description PMU 0x98100000 + 0xB4 UART2_RX_REQACKCFG UART2 RX REQ/ACK Connection Configuration PMU 0x98100000 + 0xB8 SDC_REQACKCFG SDC REQ/ACK Connection Configuration PMU 0x98100000 + 0xBC I2SAC97_REQACKCFG I2S/AC97 REQ/ACK Connection Configuration

PMU 0x98100000 + 0xC0 IrDA(SIR)_TX_REQACKCFG IrDA(SIR) TX REQ/ACK Connection Configuration

PMU 0x98100000 + 0xC8 USBD_REQACKCFG USB2.0 device REQ/ACK Connection Configuration

PMU 0x98100000 + 0xCC IrDA(SIR)_RX_REQACKCFG IrDA(SIR) TX REQ/ACK Connection Configuration

PMU 0x98100000 + 0xD0 IrDA(FIR)_REQACKCFG IrDA(FIR) REQ/ACK Connection Configuration

PMU 0x98100000 + 0xD4 External Device0 REQ External Device0 REQ/ACK Connection Configuration

PMU 0x98100000 + 0xD8 External Device1 REQ External Device1 REQ/ACK Connection Configuration

BTUART 0x98300000 + 0x00 RBR Receiver Buffer Register BTUART 0x98300000 + 0x00 THR Transmitter Holding Register

BTUART 0x98300000 + 0x00 DLL Baud Rate Divisor Latch Least Significant Byte (DLAB =1)

BTUART 0x98300000 + 0x04 IER Interrupt Enable Register

BTUART 0x98300000 + 0x04 DLM Baud Rate Divisor Latch Most Significant Byte (DLAB = 1)

BTUART 0x98300000 + 0x08 IIR Interrupt Identification Register BTUART 0x98300000 + 0x08 FCR FIFO Control Register BTUART 0x98300000 + 0x08 PSR Pre-scale Register (DLAB = 1) BTUART 0x98300000 + 0x0C LCR Line Control Register BTUART 0x98300000 + 0x10 MCR Modem Control Register BTUART 0x98300000 + 0x14 LSR Line Status Register BTUART 0x98300000 + 0x18 MSR Modem Status Register BTUART 0x98300000 + 0x1C SPR Scratch Pad Register TIMER 0x98400000 + 0x00 Tm1Counter Timer1 Counter TIMER 0x98400000 + 0x04 Tm1Load Timer1 Auto Reload Value TIMER 0x98400000 + 0x08 Tm1Match1 Timer1 Match Value TIMER 0x98400000 + 0x0C Tm1Match2 Timer1 Match Value TIMER 0x98400000 + 0x10 Tm2Counter Timer2 Counter TIMER 0x98400000 + 0x14 Tm2Load Timer2 Auto Reload Value TIMER 0x98400000 + 0x18 Tm2Match1 Timer2 Match Value TIMER 0x98400000 + 0x1C Tm2Match2 Timer2 Match Value TIMER 0x98400000 + 0x20 Tm3Counter Timer3 Counter TIMER 0x98400000 + 0x24 Tm3Load Timer3 Auto Reload Value TIMER 0x98400000 + 0x28 Tm3Match1 Timer3 Match Value

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Module Name Address Name Description TIMER 0x98400000 + 0x2C Tm3Match2 Timer3 Match Value TIMER 0x98400000 + 0x30 TmCR Timer1, Timer2, Timger3 Control Register TIMER 0x98400000 + 0x34 IntrState Interrupt State of TMR TIMER 0x98400000 + 0x38 IntrMask Interrupt Mask of TMR WDT 0x98500000 + 0x00 WdCounter Watch Dog Timer Counter Register WDT 0x98500000 + 0x04 WdLoad Watch Dog Timer Counter Auto Reload Register WDT 0x98500000 + 0x08 WdRestart Watch Dog Timer Counter Restart Register WDT 0x98500000 + 0x0C WdCR Watch Dog Timer Control Register WDT 0x98500000 + 0x10 WdStatus Watch Dog Timer Status WDT 0x98500000 + 0x14 WdClear Watch Dog Timer Clear WDT 0x98500000 + 0x18 WdIntrCter Watch Dog Timer Interrupt Length RTC 0x98600000 + 0x00 RtcSecond RTC Second Register RTC 0x98600000 + 0x04 RtcMinute RTC Minute Register RTC 0x98600000 + 0x08 RtcHour RTC Hour Register RTC 0x98600000 + 0x0C RtcDays RTC Day Count Register RTC 0x98600000 + 0x10 AlarmSecond RTC Second Alarm Register RTC 0x98600000 + 0x14 AlarmMinute RTC Minute Alarm Register RTC 0x98600000 + 0x18 AlarmHour RTC Hour Alarm Register RTC 0x98600000 + 0x1C RtcRecord RTC Record Register RTC 0x98600000 + 0x20 RtcCR RTC Control Register GPIO 0x98700000 + 0x00 GpioDataOut GPIO Data Output Register GPIO 0x98700000 + 0x04 GpioDataIn GPIO Data Input Register GPIO 0x98700000 + 0x08 PinDir GPIO Direction Register GPIO 0x98700000 + 0x10 GpioDataSet GPIO Data Bit Set Register GPIO 0x98700000 + 0x14 GpioDataClear GPIO Data Bit Clear Register GPIO 0x98700000 + 0x18 PinPullEnable GPIO Pull Up Register GPIO 0x98700000 + 0x1C PinPullType GPIO Pull High Pull Low Register GPIO 0x98700000 + 0x20 IntrEnable GPIO Interrupt Enable Register GPIO 0x98700000 + 0x24 IntrRawState GPIO Interrupt Raw Status Register GPIO 0x98700000 + 0x28 IntrMaskedState GPIO Interrupt Masked Status Register GPIO 0x98700000 + 0x2C IntrMask GPIO Interrupt Mask Register GPIO 0x98700000 + 0x30 IntrClear GPIO Interrupt Clear GPIO 0x98700000 + 0x34 IntrTrigger GPIO Interrupt Trigger Method Register GPIO 0x98700000 + 0x38 IntrBoth GPIO Interrupt Edge Trigger By Both GPIO 0x98700000 + 0x3C IntrRiseNeg GPIO Interrupt Trigger by Rising or Falling Edge

GPIO 0x98700000 + 0x40 BounceEnable GPIO Pre-scale Clock Enable. When enabled, PCLK will be divided by BouncePreScale clock.

GPIO 0x98700000 + 0x44 BouncePreScale GPIO Pre-scale, which is used to adjust different

AG101


Module Name Address Name Description PCLK frequencies.

INTC 0x98800000 + 0x00 IRQSR IRQ Source Register INTC 0x98800000 + 0x04 IRQMR IRQ Mask Register INTC 0x98800000 + 0x08 IRQICR IRQ Interrupt Clear Register INTC 0x98800000 + 0x0C IRQTMR IRQ Trigger Mode Register INTC 0x98800000 + 0x10 IRQTLR IRQ Trigger Level Register INTC 0x98800000 + 0x14 IRQSR IRQ Status Register INTC 0x98800000 + 0x20 FIQSR FIQ Source Register INTC 0x98800000 + 0x24 FIQMR FIQ Mask Register INTC 0x98800000 + 0x28 FIQICR FIQ Interrupt Clear Register INTC 0x98800000 + 0x2C FIQTMR FIQ Trigger Mode Register INTC 0x98800000 + 0x30 FIQTLR FIQ Trigger Level Register INTC 0x98800000 + 0x34 FIQSR FIQ Status Register INTC 0x98800000 + 0x50 RRVISION Revision Register INTC 0x98800000 + 0x54 FRIN Feature Register for Input Number INTC 0x98800000 + 0x58 FRIDL Feature Register for IRQ De-bounce Location INTC 0x98800000 + 0x5C FRFDL Feature Register for FIQ De-bounce Location I2C 0x98A00000 + 0x00 CR I2C Control Register I2C 0x98A00000 + 0x04 SR I2C Status Register I2C 0x98A00000 + 0x08 CDR I2C Clock Divided Register I2C 0x98A00000 + 0x0C DR I2C Data Register I2C 0x98A00000 + 0x10 SAR I2C Slave Address Register

I2C 0x98A00000 + 0x14 TGSR I2C Setup / Hold Time & Glitch Suppression Setting Register

I2C 0x98A00000 + 0x18 BMR I2C Bus Monitor Register SSP 0x98B00000 + 0x00 SSPCR0 SSP Control Register 0 SSP 0x98B00000 + 0x04 SSPCR1 SSP Control Register 1 SSP 0x98B00000 + 0x08 SSPCR2 SSP Control Register 2 SSP 0x98B00000 + 0x0C SSPSR SSP Status Register SSP 0x98B00000 + 0x10 SSPICR SSP Interrupt Control Register SSP 0x98B00000 + 0x14 SSPISR SSP Interrupt Status Register SSP 0x98B00000 + 0x18 SSPDR SSP Data Register SSP 0x98B00000 + 0x20 SSPVR AC-link Slot Valid Register CFC 0x98D00000 + 0x00 CFSR CF Host Status Register CFC 0x98D00000 + 0x04 CFCR CF Host Control Register CFC 0x98D00000 + 0x08 CFATCR Access Timing Configuration Register CFC 0x98D00000 + 0x0C CFABCR Active Buffer Controller Register CFC 0x98D00000 + 0x10 CFABDR Active Buffer Data Register

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Module Name Address Name Description CFC 0x98D00000 + 0x14 CFMSR Multi Sector Register CFC 0x98D00000 + 0x18 TSMER Transfer Size Mode2 Enable Register CFC 0x98D00000 + 0x1C TSMCR Transfer Size Mode2 Counter Register SDC 0x98E00000 + 0x00 SDCR Command Register SDC 0x98E00000 + 0x04 SDAR Argument Register SDC 0x98E00000 + 0x08 SDRR0 Response Register0 SDC 0x98E00000 + 0x0C SDRR1 Response Register1 SDC 0x98E00000 + 0x10 SDRR2 Response Register2 SDC 0x98E00000 + 0x14 SDRR3 Response Register3 SDC 0x98E00000 + 0x18 SDRCR Responded Command Register SDC 0x98E00000 + 0x1C SDDCR Data Control Register SDC 0x98E00000 + 0x20 SDDTR Data Timer Register SDC 0x98E00000 + 0x24 SDDLR Data Length Register SDC 0x98E00000 + 0x28 SDSR Status Register SDC 0x98E00000 + 0x2C SDCLR Clear Register SDC 0x98E00000 + 0x30 SDIMR Interrupt Mask Register SDC 0x98E00000 + 0x34 SDPCR Power Control Register SDC 0x98E00000 + 0x38 SDCCR Clock Control Register SDC 0x98E00000 + 0x3C SDBWR Bus Width Register SDC 0x98E00000 + 0x40 SDDWR Data Window Register PWM 0x99100000 + 0x00 PWM0CR PWM0 Control Registers for first clock output PWM 0x99100000 + 0x04 PWM0DCR PWM0 Duty Cycle Registers for first clock output PWM 0x99100000 + 0x08 PWM0PCR PWM0 Period Control Register for first clock outputPWM 0x99100000 + 0x10 PWM1CR PWM1 Control Registers for second clock PWM 0x99100000 + 0x14 PWM1DCR PWM1 Duty Cycle Registers for second clock outputPWM 0x99100000 + 0x18 PWM1PCR PWM1 Period Control Register for first clock outputI2S/AC97 0x99400000 + 0x00 SSPCR0 SSP Control Register 0 I2S/AC97 0x99400000 + 0x04 SSPCR1 SSP Control Register 1 I2S/AC97 0x99400000 + 0x08 SSPCR2 SSP Control Register 2 I2S/AC97 0x99400000 + 0x0C SSPSR SSP Status Register I2S/AC97 0x99400000 + 0x10 SSPICR SSP Interrupt Control Register I2S/AC97 0x99400000 + 0x14 SSPISR SSP Interrupt Status Register I2S/AC97 0x99400000 + 0x18 SSPDR SSP Data Register I2S/AC97 0x99400000 + 0x20 SSPVR AC-link Slot Valid Register STUART 0x99600000 + 0x00 RBR Receiver Buffer Register STUART 0x99600000 + 0x00 THR Transmitter Holding Register

STUART 0x99600000 + 0x00 DLL Baud Rate Divisor Latch Least Significant Byte (DLAB =1)

AG101


Module Name Address Name Description STUART 0x99600000 + 0x04 IER Interrupt Enable Register

STUART 0x99600000 + 0x04 DLM Baud Rate Divisor Latch Most Significant Byte (DLAB = 1)

STUART 0x99600000 + 0x08 IIR Interrupt Identification Register STUART 0x99600000 + 0x08 FCR FIFO Control Register STUART 0x99600000 + 0x08 PSR Pre-scale Register (DLAB = 1) STUART 0x99600000 + 0x0C LCR Line Control Register STUART 0x99600000 + 0x14 LSR Line Status Register STUART 0x99600000 + 0x1C SPR Scratch Pad Register

AG101


39

4 Power Management Unit General Descriptions

The Power Management Unit (PMU) provides fixed clocks for each peripheral unit. Many of the devices’

peripheral clocks can be disabled by using the AHB Module Clock Off Control Register (AHBMCLKOFF), the

APB Module Clock Off Control Register (APBMCLKOFF), or through bits in the peripheral’s control registers.

The clock of a unit not in operation is turned off to minimize the power consumption. The PMU also provides a

method to change the PLL frequency and various power modes.

Features

● Power-on Reset resets all modules and restores the system to its default state.

● Hardware Reset (X_rst_b asserted) initiates non-maskable total reset.

● Watchdog Reset is asserted through the Watchdog Timer, and resets the system except the PMU and RTC

units. This reset is used as a code monitor.

● Normal mode: All power supplies are enabled and all functionally enabled clocks are running.

● Turbo mode: Allows the user to clock the CPU core at a higher frequency during peak processing.

● Sleep mode: Only the contents of the RTC and PMU are preserved.

● FCS mode: Frequency Change Sequence (FCS) mode allows the user to change the core PLL settings, such

that the system can operate at variant frequencies.

AG101


Block Diagram

Figure 3. PMU Block Diagram.

Clock Manager

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The AG101’s clocking system incorporates five major clock sources:

● 32.768 KHz low-frequency crystal input

● 5.0 – 10.0 MHz high-frequency oscillator input

● Programmable Frequency Core PLL (PLL1)

● PLL reserved for internal use (PLL2)

● 150.0 MHZ Fixed Frequency PLL (PLL3)

4.1.1 Low Frequency Crystal Input

The low frequency crytal input is an optional crystal input that can be used to clock the RTC, WDT, TIMER and

PMU. It can be activated by writing “1” to the RTCSEL bit in the OSCCR. The OSCLSTABLE bit is set to 1 if the

low frequency crystal input is stable. In case the low frequency crystal input is disabled due to hardware reset, the

default high frequency oscillator input would clock the RTC, WDT, TIMER and PMU. This input may be used in

sleep mode for lower power consumption.. In less power-sensitive applications, the user may disable this low

frequency crystal input in the OSCCR register. If ther is no clock source attached to this input in a system, the

frequency of the RTC, WDT, TIMER and PMU can be divided from the high frequency oscillator input.

4.1.2 High Frequency Oscillator Input

The high frequency oscillator input is the primary clock source for AG101. The on-chip PLL frequency multipliers

and PWM rely on this clock source only; while this clock source also drives the RTC, WDT, TIMER and PMU in

case hardware resets. The low frequency crystal input may be activated again once it is stabilized. The high

frequency oscillator intput is disabled automatically during sleep mode if the low frequency crystal input is enabled

and the RTCSEL bit in the OSCCR register is set to “1”.

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4.1.3 Core Phase Locked Loop (PLL1)

The core PLL is the clock source for the AHB bus devices and APB bus devices. The core PLL uses the high

frequency oscillator input as a reference (recommending 5 – 10 MHz) and multiplies its frequency by

programming the PLL1NS bits in the PDLLCR0 register. The AHB bus clock frequency is half of the core PLL

frequency output, while the APB bus clock frequency is half of the AHB bus clock frequency. The core PLL is not

powered during Sleep Mode.

The output frequency of PLL1 can be set by the jumper setting pins through the memory address bits [21:19] after

power-on reset. The following table shows the jumper setting table for PLL1. The internal PLL1, PLL2 and PLL3

can also be disabled at the jumper setting pin through the memory address bit [15].

Table 5. Jumper Setting for the Output Frequency of PLL1.

Memory Address[21:19] Description 000 20 times 5.0 MHz. The output frequency of the PLL1 is 100.0 MHz. 001 40 times 5.0 MHz. The output frequency of the PLL1 is 200.0 MHz. 010 60 times 5.0 MHz. The output frequency of the PLL1 is 300.0 MHz. 011 70 times 5.0 MHz. The output frequency of the PLL1 is 350.0 MHz. 100 80 times 5.0 MHz. The output frequency of the PLL1 is 400.0MHz. 101 100 times 5.0 MHz.The output frequency of the PLL1 is 500.0 MHz. 110 120 times 5.0 MHz. The output frequency of the PLL1 is 600.0 MHz. 111 140 times 5.0 MHz. The output frequency of the PLL1 is 700 MHz.

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4.1.4 150.0 MHZ Peripheral Phase Locked Loop (PLL3)

The 150.0 MHZ PLL is the clock source for many of the peripheral block’s external interfaces. The required

interface frequency is at 18.75 MHz for UARTs, 25 MHz for AC97 and variant for I2S. These values are set

through the I2SCLKDIV bit in the PDLLCR1 register. The generated frequency may not exactly match the

required frequency due to the choice of crystal and the absence of a perfect Least Common Multiple between the

units. The chosen frequencies keep each unit’s clock frequency within its clock tolerance. If a crystal not at 5.0

MHz is used, the clock frequencies to the peripheral blocks’ interfaces may not yield the desired baud rates (or

other protocol’s rate). The PLL3 can be disabled individually by writing a “1” to the PLL3DIS bit in the PDLLCR1

register when these peripheral blocks are not used. If the PLL3STABLE bit in the PDLLCR1 register is set to “1”

while PLL3 is enabled, then PLL3 is stable.

4.1.5 Clock Gating

The PMU contains the AHBMCLKOFF and APBMCLKOFF registers. These registers contain configuration bits

that can disable the clocks of each individual unit. The configuration bits are used when a module is not in

operation. After hardware reset, any module that is not used must have its clock disabled.

Resets and Power Modes

The PMU determines the AG101 resets, power sequences and power modes. Each behaves differently during

operation and has specific entry and exit sequences. The resets and power modes are:

● Power-on Reset

● Hardware Reset

● Watchdog Reset

● Normal Mode

● Frequency Scaling Mode

● Frequency Change Sequence

● Sleep Mode

The following table shows the state of each unit after each type of reset.

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Table 6. Effect of Each Type of Reset on Internal Register State.

Unit POR Hardware Reset Watchdog Reset Sleep Mode Reset Power SupplyCPU Reset Reset Reset Reset 1.3V

AHBC Reset Reset Reset Reset 1.3V

Memory controller Reset Reset Reset Reset 1.3V

Ethernet MAC Reset Reset Reset Reset 1.3V

DMA Reset Reset Reset Reset 1.3V

APB Bridge Reset Reset Reset Reset 1.3V

USB 2.0 Reset Reset Reset Reset 1.3V

CFC Reset Reset Reset Reset 1.3V

SDC Reset Reset Reset Reset 1.3V

I2C Reset Reset Reset Reset 1.3V

PWM Reset Reset Reset Reset 1.3V

I2S / AC97 Reset Reset Reset Reset 1.3V

SPI Reset Reset Reset Reset 1.3V

UART Reset Reset Reset Reset 1.3V

INTC Reset Reset Reset Reset 1.3V

GPIO Reset Reset Reset Reset 1.3V

TIMER Reset Reset Reset Reset 1.3V

WDT Reset Reset Reset Reset 1.3V

RTC Reset Preserved Preserved Preserved 1.3 V Alive PMU Reset Reset Option Preserved 1.3 V Alive

4.1.6 Power-On Reset

The power-on reset is invoked when the X_por_b pin is pulled low by an external source. The X_reset_b and

X_hreset_b pins are asserted when the X_por_b is asserted.

During power-on reset, all internal registers and units are in their predefined reset conditions. While the X_por_b

pin is asserted, nothing inside the AG101 is active. The internal clocks are stopped and the chip is static. All pins

return to their reset conditions. Since the memory controller receives a full reset, all dynamic RAM contents are

lost during power-on reset.

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To complete power-on reset, de-assert the X_por_b pin. All power supplies must be stable before X_por_b is

de-asserted. After the X_por_b pin is de-asserted, the following sequence occurs:

User pushes the power enable button through the GPIO[0] pin.

1. An internal logic waits for stabilization of the high frequency oscillator input and internal PLL clock

generators.

2. The X_reset_b and X_hreset_b pins are de-asserted.

3. The normal boot-up sequence begins. All AG101 units return to their predefined reset conditions.

Software must examine the Power Manager Status Register (PMSR [SMR, WDR, HDR]) to determine

the cause of the boot-up.

Please refer to Table 6 for the relationship between the power-on reset and each unit state. Figure 4 shows the

timing of the power-on reset.

X_por_b (input)

X_pwren(output)

X_rst_b (input)

X_powerok (input)At least 100us

Alive power on Push GPIO0

Figure 4. Power-on Reset Timing.

4.1.7 Hardware Reset

Hardware reset is invoked when the X_rst_b pin is pulled low by an external source. The AG101 does not

provide a method for masking or disabling the propagation of the external pin value. When the X_rst_b pin is

asserted, hardware reset is invoked regardless of the mode of operation. The X_reset_b and X_hreset_b pins are

asserted when the X_rst_b pin is asserted.

During hardware reset, all internal registers and units except the RTC unit are held in their predefined reset

conditions. While the X_rst_b pin is asserted, nothing inside the AG101 is active except the high frequency clock

input and the RTC unit. This means that the RTC can keep on counting during hardware reset. However, since the

memory controller receives a full reset, all dynamic RAM contents are lost during hardware reset.

AG101


To complete hardware reset, de-assert the X_rst_b pin. After the X_rst_b pin is de-asserted, the following sequence occurs:

1. An internal logic waits for stabilization of the high frequency oscillator input and internal PLL clock generators.


3. The normal boot-up sequence begins. All AG101 units except the RTC unit return to their predefined

reset conditions. Software must examine the Power Manager Status Register (PMSR [SMR, WDR, HDR])

to determine the cause of the boot-up.

Please refer to Table 6 for the relationship between the hardware reset and each unit state.

Figure 5 shows the relationship among the X_rst_b, X_reset_b and X_hreset_b signals.

3.66ms 1.22ms

X_rst_b (input)

X_reset_b (output)

X_hreset_b (output)

Figure 5. Relationship Among the X_rst_b, X_reset_b and X_hreset_b.

4.1.8 Watchdog Reset

Watchdog Reset is invoked when software fails to properly prevent the watchdog time-out event from occurring.

By default, watchdog reset is engaged only if software is not executing properly to pet the watchdog by reseting its

counter value. Watchdog Reset asserts X_reset_b and X_hreset_b pins.

During Watchdog Reset, all units revert to their predefined reset conditions except for the RTC and parts of the

PMU. When the WDTCLR bit in the Power Manager Control Register (PMCR) is set to “1”, the MODE [1:0] bits

in the power mode register, the DLLFRANG, PLL1FRANG and PLL1NS bits in the PDLLCR0 register will be

reset by Watchdog Reset. This means that the rest status of the aforementioned registers depends on the WDTCLR

bit. All dynamic RAM contents are lost during Watchdog Reset because the memory controller receives a full

reset.

The sequence for completing Watchdog Reset is:

1. An internal logic wait for stabilization of the high frequency oscillator intput and internal PLL clock generators.


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3. The normal boot-up sequence begins. All AG101 units return to their predefined reset condition except

the RTC unit and parts of the PMU return to their predefined reset conditions. Software must examine the

Power Manager Status Register (PMSR [SMR, WDR, HDR]) to determine the cause of the boot-up.

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4.1.9 Normal Mode

Normal Mode refers to operating under typical conditions. All power supplies are enabled and all functionally

enabled clocks are running. Normal Mode is engaged after any power mode, power sequence, or reset completes its

sequence.

4.1.10 Frequency Scaling Mode

Frequency Scaling Mode is invoked when EFSF or EDIVAHBCLK bits of PMODE register have been set. CPU

executes the STANDBY instruction after software sets the EFSF and EDIVAHBCLK bits. Thereafter, CPU enters into

standby mode until all the instructions in the pipeline are completed. The value set in PMODE register would be updated into the Frequency Scaling Status register. The clock divider then starts to change frequency. The PMU issues

an interrupt to wait up CPU after completing the frequency scaling. After CPU is awake from the standby mode, it

resumes operation at the desired frequency and clock ratio.

The sequence for entering frequency switch mode is the following:

1. Set EFSF and EDIVAHBCLK bit in the Power Mode register. 2. Write STANDBY instruction. 3. CPU enters the standby mode and masks all the interrupts. CPU sends out core_standby signal

instructing PMU to start to do frequency scaling. 4. PMU sends back wakeup_ok signal to notify CPU that frequency scaling is done. CPU then

unmasks the interrupts. 5. PMU issues an interrupt to wait up CPU. 6. CPU enters interrupt subroutine. 7. CPU operates at the desired frequency and clock ratio.

4.1.11 Frequency Change Sequence (FCS)

The Frequency Change Sequence (FCS) is used to change the system clock frequency. While in the FCS, the

system clocks stop. This mode is intended for setting a different frequency to overwrite the default value at initial

boot-up. This can be used as a power-saving feature that allows the AG101 to run at the minimum required

frequency.

The initiation of FCS is as follows:

1. Initiate the interrupt controller and unmask the Clocks and Power Manager Unit interrupt. Software programs instruct the WAITPD bit in the PCR register. Select the CPU power down side band

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49

signal or a programmable time.

If necessary, disable AHB master peripherals to prevent events from entering the system.

Program a suitable value to the refresh interval counter of the SDRAMC.

Write a new frequency value to the PDLLCR0 [PLL1FRANG, PLL1NS].

Set the FCS bit in the PMODE register.

Block the requests of AHB master except for those from CPU.

Block the interrupts to CPU.

Write CPU Power down command.

Wait for CPU’s power down side band signal, or alternatively, wait for a programmable time.

To check HMASTER = 0x00. (No any transaction on the AHB bus).

Issue self-refresh command to SDRAM controller.

Wait for the acknowledgement of self-refresh.

Gate clocks. (pclk, hclk, then cpuclk)

Load the new frequency value to Core Phase Locked Loop (PLL1).

Wait for PLL1’s stable signal, or alternatively, wait for a programmable time. (Software programmable)

Allow clocks to free run. (cpuclk, then hclk, pclk)

Remove the gating of master requests, interrupts.

Clocks and Power Manager Unit issues an interrupt to CPU. CPU then enters interrupt subroutine.

Software must examine the Power Manager Status Register (PMSR [IntPwrLow, IntFCS, IntTurbo]) to

determine the cause for the waked up. Software must clear the FCS bit in the PMODE register.

Note the aforementioned steps in bold font are executed by software.

4.1.12 Sleep Mode

Sleep Mode offers lower power consumption at the expense of losing most of the internal function state. In Sleep

Mode, the AG101 goes through an orderly shut down sequence and power is withdrawn from the core. Thereafter,

the PMU monitors for a wake-up event. As it receives one, it re-establishes power supply and goes through a reset

sequence. During Sleep Mode, the RTC and PMU continue to work and external SDRAM is preserved because it is

in self-refresh mode.

Since all activities on the AG101, except the RTC, stop when Sleep Mode is engaged, peripherals must be disabled

to allow an orderly shut down. When Sleep Mode is released, the CPU state is reset and processing resumes in a

boot-up mode.

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To implement sleep mode in the simplest manner, the External Voltage Regulator (EVR) that powers the AG101’s

internal elements must have the following characteristics:

A power enable pin (X_pwren) that maintains the main voltage supplies output to V1, V2, VCC12A and

VCC12I.

The regulator output should be driven low when X_pwren is driven low.

The VCC3Alive and VCC12Alive are continuously driven power when X_pwren is driven low.

Software uses the MODE[0] bit in the PMODE register to enter sleep mode. If the external voltage regulator is at

fault or the main power is low or missing, the system must enter sleep mode promptly. When the X_powerlow_b is

asserted, the system is required to shut down immediately. There are three methods to enter sleep mode: software

instruction, GPIO trigger, and X_powerlow_b trigger.

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The sequence for entering Sleep Mode by software instructions is as follows:

1. OS calls the peripherals’ sleeping function to instruct all peripherals go to sleep. Hence, there is no transaction generated by masters. Cache is flushed. Critical settings are saved somewhere.

2. Disable the interrupts to CPU.

3. Set the MODE[0] bit in the PMODE register.

4. Block the requests of AHB master except CPU.

5. Block the interrupts to CPU.

6. Write CPU power down command.

7. Wait for the CPU power down side band signal, or alternatively wait for a programmable time.

8. Check if HMASTER = 0x00 (no transaction on the AHB bus).

9. Issue self-refresh command to SDRAM controller.

10. Wait for acknowledge of self-refresh.

11. Clocks and Power Manager Unit set the “PH” and “RDHold” to fix the output signal and disable the input

signal with respect to GPIO[15:0].

12. Turn off the high frequency oscillator input if the low frequency crystal input is enabled (defined by

registers).

13. Assert X_reset_b and X_hreset_b.

14. De-assert X_pwren pin. Then power is cut off.


The sequence for entering Sleep Mode by setting the GPIO trigger is as follows:

1. Initiate the Interrupt controller and unmask the GPIO, clocks and Power Manager Unit interrupt. 2. Trigger the GPIO by an external source.

3. Issue an interrupt to CPU to execute an interrupt service routine.

4. Follow the same steps 4 to 12 for entering Sleep Mode by implementing software instructions.


The sequence for entering Sleep Mode by setting the X_powerlow_b trigger is as follows:

1. Clear the PCR[PWRLOWMSK] bit to unmask the X_powerlow_b source. 2. Initiate the Interrupt controller. Unmask the clocks and Power Manager Unit interrupt.

3. When X_poserlow_b is asserted, issue an interrupt to CPU to execute an interrupt service routine.

4. Follow the same steps 4 to 12 for entering Sleep Mode by software instructions.

Note the aforementioned steps in bold font are executed by software. Sleep Mode is deactivated when hardware

AG101


reset is asserted. The entry and exit sequence of hardware reset take precedence over Sleep Mode. If hardware reset is

asserted during sleep mode, the SDRAM contents would be lost because all states, including memory controller

configuration and previous Sleep Mode settings are reset.

Normally, Sleep Mode is released in the following sequence:

1. Wait for pre-programmable RTC or GPIO[15:0] wake-up events. If X_powerlow_b is asserted, only GPIO[1:0] wake-up events are valid.

2. Assert the X_pwren pin.

3. Wait until the high frequency oscillator input is stable if it is turned off in sleep mode.

4. Wait for PLL1 stable.

5. Wait for DLL stable.

6. De-assert X_reset_b.

7. De-assert the internal sleep reset signal, and clear the PMODE register.

8. Unblock the requests of AHB master and interrupts.

9. CPU is about to perform a fetch from the Reset Vector.

10. Clear PMSR [PH] and PMSR [RDH].

11. Check PMSR [SMR, WDR, HDR], to determine what caused the reboot.

12. Recover all critical setting stored in PSPR15~PSPR0 for system (SDRAM setting, etc.).

13. Recover all setting / data stored in SDRAM.


4.1.13 Power Management

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The AG101 supports up to 6 levels of power down management. The frequency scaling factor can be set by programming bit[11:8] of PMODE register. The following table shows the supported scaling factor based on clock ratio.

Clock Ratio\Scaling Factor 1/1 1/2 1/3 1/4 1/5 1/6

1:1 Y Y Y Y Y Y

2:1 Y Y Y N N N

3:1 Y Y N N N N

4:1 Y N N N N N

5:1 Y N N N N N

6:1 Y N N N N N

8:1 Y N N N N N

10:1 Y N N N N N

12:1 Y N N N N N

14:1 Y N N N N N

15:1 Y N N N N N

18:1 Y N N N N N

20:1 Y N N N N N

Clock Ratio\Scaling Factor 1/1 1/2 1/3 1/4 1/5 1/6

3:2 Y Y N N N N

5:2 Y N N N N N

Note: The CPU clock would be half of the clock speed from the PLL output in 3:2 and 5:2 clock ratio with 1/1 scaling factor. Programming Model 4.1.14 Summary of the Clocks and Power Manager Registers

The following table shows a summary of the PMU registers.

Table 7. Summary of PMU Registers.

Address (Offset) Description Reset Value

AG101


Address (Offset) Description Reset Value +0x00 ID Number0 Register 0x01010001 +0x04 Frequency Scaling Status Register 0x00000000 +0x08 OSC Control Register 0x0000 a09 +0x0C Power Mode Register 0x0000 0000 +0x10 Power Manager Control Register 0x000A 0001 +0x14 Power Manager Edge Detect 0x0001 0001 +0x18 Power Manager Edge Detect Status 0x0000 0001 +0x20 Power Manager Status Register 0x0000 0104 +0x24 Power Manager GPIO Sleep State Register 0x0000 0000 +0x28 Multi-Function Port Setting Register 0x0000 0000 +0x2C Misc. 0x0000 0000 +0x30 PLL/DLL Control Register 0 0x0002 0002 +0x34 PLL/DLL Control Register 1 0x0006 0202 +0x38 AHB Module Clock Off Control Register 0x0000 0000 +0x3C APB Module Clock Off Control Register 0x0000 0000 +0x40 Driving Capability and Slew Rate Control Register0 0xAA55 5551 +0x44 Driving Capability and Slew Rate Control Register1 0x1111 1111 +0x48 Driving Capability and Slew Rate Control Register2 0x1111 1111 +0x4C SDRAM Signal Hold Time Control 0x7440 0000 +0x50 Power Manager Scratch Pad Register 0 0x0000 0000 +0x54 Power Manager Scratch Pad Register 1 0x0000 0000 +0x58 Power Manager Scratch Pad Register 2 0x0000 0000 +0x5C Power Manager Scratch Pad Register 3 0x0000 0000 +0x60 Power Manager Scratch Pad Register 4 0x0000 0000 +0x64 Power Manager Scratch Pad Register 5 0x0000 0000 +0x68 Power Manager Scratch Pad Register 6 0x0000 0000 +0x6C Power Manager Scratch Pad Register 7 0x0000 0000 +0x70 Power Manager Scratch Pad Register 8 0x0000 0000 +0x74 Power Manager Scratch Pad Register 9 0x0000 0000 +0x78 Power Manager Scratch Pad Register 10 0x0000 0000 +0x7C Power Manager Scratch Pad Register 11 0x0000 0000 +0x80 Power Manager Scratch Pad Register 12 0x0000 0000 +0x84 Power Manager Scratch Pad Register 13 0x0000 0000 +0x88 Power Manager Scratch Pad Register 14 0x0000 0000 +0x8C Power Manager Scratch Pad Register 15 0x0000 0000 +0x90 AHB DMA REQ/ACK Connection Configuration Status 0x0000 00fe +0x9c Jumper Setting Status Depend on jpset

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Address (Offset) Description Reset Value +0xA0 CFC REQ/ACK Connection Configuration 0x0000 0000 +0xA4 SSP1 REQ/ACK Connection Configuration 0x0000 0000 +0xA8 UART1 TX REQ/ACK Connection Configuration 0x0000 0000 +0xAC UART1 RX REQ/ACK Connection Configuration 0x0000 0000 +0xB0 UART2 TX REQ/ACK Connection Configuration 0x0000 0000 +0xB4 UART2 RX REQ/ACK Connection Configuration 0x0000 0000 +0xB8 SDC REQ/ACK Connection Configuration 0x0000 0000 +0xBC AC97 REQ/ACK Connection Configuration 0x0000 0000 +0xC8 USB device REQ/ACK Connection Configuration 0x0000 0000 +0xD4 External Device0 REQ/ACK Connection Configuration 0x0000 0008 +0xD8 External Device1 REQ/ACK Connection Configuration 0x0000 0009

4.1.15 Register Descriptions

The following sections describe the PMU registers in more detail.

The abbreviations below represent the access types used throughout the register descriptions:

● R/W: Read/Write

● RO: Read Only

● W1C: Write 1 Cleared

● HR: Power On Reset and Hardware Reset

● WR: Watchdog Reset

● WRo: Watchdog Reset Option. Depend on PCR[WDTCLR]

● SMR: Sleep Mode Reset

4.1.15.1 ID Number 0 Register (Offset == 0x00)

This register describes the device, system and version ID number.

Table 8. ID Register (IDNMBR0).

Bit Name Type Description Reset Value Reset Type 31-16 DeviceID RO Device ID number 0x0101 15-8 Reserved RO Reserved for future expansion 0x00 7-0 VER_NUM RO Version number 0x01

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4.1.15.2 Frequency Scaling Status Register (FSSR) (Offset == 0x04) 31 12 11 8 7 4

Resv FSF DIVAHBCLK Resv

Bit Name Type Description Reset Value Reset Type

31-12 Reserved

11-8 FSF RO Frequency Scaling Factor.

CPU clock frequency

against PLL1 output

frequency.

0000: 1

0001: 1/2

0010: 1/3

0011: 1/4

0100: 1/5

0101: 1/6

1xxx: Reserved

0x0 HR, WRo

7-4 DIVAHBCLK RO clock ratio: cpu:bus

0000: 1:1

0001: 2:1

0010: 3:1

0011: 4:1

0100: 5:1

0101: 6:1

0110: 3:2

0111: 5:2

1000: 8:1

1001: 10:1

1010: 12:1

1011: 14:1

1100: 15:1

1101: 18:1

1110: 20:1

1111: Reserved

[jpset,jpset,jpset,jpset]

[hmastlock,hamster[2:0]]

HR,WRo

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3-0 Reserved

AG101


4.1.15.3 OSC Control Register (Offset == 0x08)

Table 9. OSC Control Register (OSCC).

Bit Name Type Description Reset Value Reset Type 31-12 - - Reserved - -

11 OSCHTRI R/W Disable OSCH function GPIO[0] PR 10 Reserved

9 OSCHSTABLE RO

Indicate if the 5.0 MHz is ready. The stable time is about 26.67 ms. 1: The oscillator is stable. 0: The oscillator is not stable.

0x00 HR

8 OSCHOFF R/W 1: Disable the 5.0 MHz oscillator. 0: Enable the 5.0 MHz oscillator.

0x0 HR

7-4 - - Reserved - - 3 OSCLTRI R/W Disable OSCL function GPIO[0] PR

2 RTCLSEL R/W

The RTC, WDT, TIMER clock selection. 1: Select 32.768 KHz oscillator as the clock source. 0: Select 5.0 MHz oscillator divided by 2 as the clock source.

0 HR

1 OSCLSTABLE RO

Indicate if the 32.768 KHz is ready. The stable time is about 1.5s. 1: The oscillator is stable. 0: The oscillator is not stable.

0 HR

0 OSCHOFF R/W 1: Disable the 32.768 KHz oscillator. 0: Enable the 32.768 KHz oscillator.

0x1 HR

4.1.15.4 Power Mode Register (Offset == 0x0C)

Table 10. Power Mode Register (PMODE).

31 12 11 8 7 4 3 2 1 0

Resv EFSF EDIVAHBCLK Resv FCS MODE[1] MODE[0]


31-12 Reserved

11-8 EFSF R/W Enable Frequency Scaling

Factor.

CPU clock frequency against

PLL1 output frequency.

0000: 1

0x0 HR, WRo

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0001: 1/2

0010: 1/3

0011: 1/4

0100: 1/5

0101: 1/6

1xxx: Reserved

7-4 EDIVAHBCLK R/W Enable clock ratio: cpu:bus

0000: 1:1

0001: 2:1

0010: 3:1

0011: 4:1

0100: 5:1

0101: 6:1

0110: 3:2

0111: 5:2

1000: 8:1

1001: 10:1

1010: 12:1

1011: 14:1

1100: 15:1

1101: 18:1

1110: 20:1

1111: Reserved

[jpset,jpset,jpset,jpset]

{ hmastlock,

hamster[2:0] }

HR,WRo

3 Reserved

2 FCS R/W Enable frequency change

sequence.

1: Enter frequency change

sequence. When changing

frequency, user must write

CPU coprocessor instruction

(Power Down command)

after Power Mode instruction.

0: Do not enter frequency

change sequence.

0x0 HR, WRo,

SMR

AG101


1 MODE[1] R/W Enable frequency scaling

mode.

1: Enter frequency scaling

mode.

0: Do not enter frequency

scaling mode.

0x0

0 MODE[0] R/W Enable sleep mode.

1: Enter sleep mode.

0: Do not enter sleep mode.

0x0 HR, WRo,

SMR

4.1.15.5 Power Manager Control Register (Offset == 0x10) Table 11. Power Manager Control Register (PMCR).


19 PWRLOWMSK R/W X_powerlow_b pin mask bit. 1: Mask the X_powerlow_b pin source. 0: Unmask the X_powerlow_b pin source.

0x1 HR, WR, SMR

18 WAITPD R/W

1: Wait for the counter to reach zero, before CPU enters power down state. The counter value can be set by programming the MISC[PDCNT]. 0: Wait for the CPU power down side band signal, before entering power down state.

0x0 HR

17 WDTCLR R/W 1: The Reset Type with WRo label will be reset by the Watchdog. 0: No affect.

0x1 HR

16 WERTC R/W 1: Wake up from sleep mode as RTC alarm is enabled.0: Wake up from sleep mode as RTC alarm is disabled.

0x0 HR, WR

15-0 WEGPIO[15:0] R/W 1: Wake up from sleep mode as GPIOx is enabled. 0: Wake up from sleep mode as GPIOx is disabled.

0x1 HR, WR

4.1.15.6 Power Manager Edge Detect Register (Offset == 0x14)

The GPIORE [15:0] determines whether the GPIO pin would cause a wake up from Sleep Mode on the rising edge

of that GPIO pin while the GPIOFE [15:0] determine whether the GPIO pin would cause a wake up from Sleep

Mode on the falling edge of that GPIO pin.

Table 12. Power Manager Edge Detect (PED) Register.

AG101


61


31-16 GPIORE[15:0] R/W Sleep mode rising-edge wake up enable. 1: Wake up as GPIOx rising-edge detect is enabled 0: Wake up as GPIOx rising-edge detect is disabled

0x1 HR, WR

15-0 GPIOFE[15:0] R/W Sleep mode falling-edge wake up enable. 1: Wake up as GPIOx falling-edge detect is enabled 0: Wake up as GPIOx falling-edge detect is disabled

0x1 HR, WR

4.1.15.7 Power Manager Edge Detect Status Register (Offset == 0x18)

The Power Manager Edge Detect Status Register (PEDSR) indicates which of the GPIO pins caused a wake up

from Sleep Mode. The bits in PEDSR can only be set on a rising or falling edge on a given GPIO pin. To reset a bit

in PEDSR to zero, write a 1 to it.

Table 13. Power Manager Edge Detect Status Register (PEDSR).


15-0 GPIOED[15:0] R/W1CSleep mode edge detection status 1: Wake up as edge on GPIOx is detected. 0: Wake up as GPIOx is not detected.

0x0 HR, WR

4.1.15.8 Power Manager Status Register (Offset == 0x20)

Table 14. Power Manager Status Register (PMSR).

Bit Name Type Description Reset Value Reset Type Reserved.

19 PwrLowSts RO

Power low pin status. This bit reflects the status of the X_powerlow_b. 1: The X_powerlow_b is pulled low. 0: The X_powerlow_b is pulled high.

18 IntPwrLow R/W1CInterrupt status for power low detection. Cleared by hardware reset and by setting to a 1.

0x0 HR

17 IntFCS R/W1CInterrupt status for completing frequency change sequence. Cleared by hardware reset and by setting to a 1.

0x0 HR

16 IntFS R/W1CInterrupt status for completing frequency scaling mode.Cleared by hardware reset and by setting to a 1.

0x0 HR

15-11 - - Reserved - -

10 SMR R/W1C Wake up from sleep mode. 1: Sleep mode has occurred since the last time the CPU

0x0 HR

AG101


Bit Name Type Description Reset Value Reset Type or hardware reset cleared this bit. 0: Sleep mode has not occurred since the last time the CPU or hardware reset cleared this bit. Cleared by hardware reset and by setting to a 1.

9 WDT R/W1C

Reboot by watchdog reset. 1: Watchdog reset has occurred since the last time the CPU or hardware reset cleared this bit. 0: Watchdog reset has not occurred since the last time the CPU or hardware reset cleared this bit. Cleared by hardware reset and by setting to a 1.

0x0 HR

8 HWR R/W1C

Reboot by hardware reset. 1: Hardware reset has occurred since the last time the CPU cleared this bit. 0: Hardware reset has not occurred since the last time the CPU cleared this bit. Cleared by hardware reset and by setting to a 1.

0x1 HR

7-3 - - Reserved - -

2 RDH R/W1C

Read disable hold. 1: Receivers of the GPIO[15:0] pins that can act as inputs are disabled. Must be cleared by the CPU after the peripheral and GPIO[15:0] interfaces are configured but before they are used. 0: GPIO[15:0] pins are configured according to their configuration. Set by hardware reset, watchdog and sleep mode. Cleared by writing a 1.

0x1 HR, WR, SMR

1 PH R/W1C

Peripheral control hold. 1: GPIO[15:0] pins are being held in their Sleep Mode state. Set when sleep mode starts. Must be cleared by the CPU after the peripheral interfaces have been configured but before they are actually used by the CPU. 0: GPIO[15:0] pins are configured according to their configuration. Cleared by hardware reset, watchdog and by writing a 1.

0x0 HR, WR

0 CKEHLOW R/W1C

SDRAM clock enable (CKE) pin held low. 1: The CKE pin is forced to a low state. 0: The CKE pin is controlled by SDRAM controller. Set when SDRAM controller issues a self-refresh signal. Cleared by hardware reset, watchdog and by writing a 1.

0x0 HR, WR

AG101


63

4.1.15.9 Power Manager GPIO Sleep State Register (Offset == 0x24) Table 15. Power Manager GPIO Sleep State Register (PGSR).


16 SS[16] R/W

Output value of GPIO[15:0] when system enters sleep mode. 1: Use SS[15:0]. 0: Auto latch.

0x0 HR, WR

15-0 SS[15:0] R/W

If programmed as an output, refers to the sleep state of GPIOx 1: Pin is driven to a one during Sleep Mode. 0: Pin is driven to a zero during Sleep Mode.

0x00 HR, WR

4.1.15.10 Multi-Function Port Setting Register (Offset == 0x28) Table 16. Multi-Function Port Setting Register (MFPSR).


17 DebugSel R/W Select debug group signal. 1: Select group 1. 0: Select group 0.

Jumper setting Mem_addr[23]

HR, WR, SMR

16 Dma0PinSel R/W

This bit selects GPIO[12:10] alternate function. 1: GPIO[12] is dma_tc0 function (output). GPIO[11] is dma_ack0 function (output). GPIO[10] is dma_req0 function (input). 0: GPIO[12:10] are used as general purpose I/Os.

0x0 HR

15 Dma1PinSel R/W

This bit selects GPIO[15:13] alternate function. 1: GPIO[15] is dma_tc0 function (output). GPIO[14] is dma_ack0 function (output). GPIO[13] is dma_req0 function (input). 0: GPIO[15:13] are used as general purpose I/Os.

0x0 HR

14 ModemPinSel R/W Not support 0x0 HR

13 AC97ClkOutSel R/W This bit selects GPIO[26] alternate function. 1: GPIO[26] is used as an AC97 output clock. 0: GPIO[26] is used as a general purpose I/O.

0x0 HR

12 Reserved R/W 0x0 HR

11 Pwm1PinSel R/W This bit selects GPIO[31] alternate function. 1: GPIO[31] is used as PWM0 function (output). 0: GPIO[31] is used as a general purpose I/O.

0x0 HR

10 Pwm0PinSel R/W This bit selects GPIO[30] alternate function. 1: GPIO[30] is used as PWM0 function (output).

0x0 HR

AG101


Bit Name Type Description Reset Value Reset Type 0: GPIO[30] is used as a general purpose I/O.

9 IrdaClkSel R/W This bit selects IrDA clock source. 1: Select external frequency input (use GPIO[24]). 0: Select the 48 MHz generated by internal PLL.

0x0 HR

8 UartClkSel R/W

This bit selects FFUART, BTUART and STUART clock source. 1: Select external frequency input (use GPIO[23]). 0: Select the 18.432 MHz generated by internal PLL.

0x0 HR

7 - - Reserved - -

6 SspClkSel R/W This bit selects SSP main clock source. 1: Select external frequency input (use GPIO[25]). 0: Select the 24.576 MHz generated by internal PLL.

0x0 HR

5 I2SClkSel R/W This bit selects I2S clock source. 1: Select external frequency input (use GPIO[22]). 0: Select the clock generated by internal PLL.

0x0 HR

4 AC97ClkSel R/W This bit selects AC97 clock source. 1: Select external frequency input (use GPIO[22]). 0: Select the 24.576 MHz generated by internal PLL.

0x0 HR

3 AC97PinSel R/W

This bit selects X_I2Ssclkout or X_ac97_resetn pin multiplexer and the source of the main clock. 1: Select the AC97 reset function and 49.152 MHz as the main clock 0: Select the I2S serial clock output and output clock of the divider as the main clock. The divider can be set by programming PDLLCR1[I2SCLKDIV] bits.

0x0 HR

2 Reserved R/W 0x0 HR

1 TriAHBDis R/W

This bit disables AHB bus to avoid output signal transient for power saving. 1: Disable AHB bus function. 0: Enable AHB bus function.

0x0 HR

0 TriAHBDbg R/W

This bit disables original AHB bus function and enables the debug function. 1: Output debug signals by AHB bus. 0: Enable original AHB bus function.


HR

AG101


65

4.1.15.11 Misc (Offset == 0x2C)

Table 17. Misc.


14-8 PDCNT[6:0] R/W If the PCR[WAITPD] bit is set to be 1, wait for the counter to reach zero, before CPU enters power down state.

0x01 HR, WR, SMR


0 TURNDIS R/W 1: EBI turn-around function disable. 0: EBI turn-around function enable.

0x0 HR, WR, SMR

4.1.15.12 PLL/DLL Control Register 0 (Offset == 0x30)

Table 18. PLL/DLL Control Register 0 (PDLLCR0).


24-21 HCLKOUTDIS R/W These bits disable the SDRAM clock output (X_sdclk[3:0]). 0x0 HR

20-19 DLLFRANG R/W

DLL output frequency range. 3: 200 ~ 400MHz 2: 100MHz ~ 200MHz 1: 50 MHz ~ 100 MHz. 0: 25 MHz ~ 50 MHz.

Jumper setting Mem_addr

[13:12] HR, WRo

18 DLLSTSEL R/W Select the method for waiting DLL stability. 1: Wait for the stable signal provided by DLL. 0: Wait 1.22ms.

0x0 HR

17 DLLSTABLE RO DLL meets lock-in time stability. Cleared when FCS starts. Set when DLL is stable. 0x0 HR, WR, SMR

16 DLLDIS R/W 1: Enable DLL. 0: Disable DLL.


HR

15-14 - - Reserved - -

13-12 PLL1FRANG R/W

PLL1 output frequency range. 11: 500+ ~700MHz. 10: 300 ~500MHz. 01: 200 MHz. 00: 100 MHz.

Jumper setting (automatic

hardwire by other jumper

setting)

HR, WRo

11-3 PLL1NS R/W

Indicate the N value of embedded PLL1 to control the PLL1 frequency output. Output frequency of PLL1 = N * 5.0 MHz 100MHz: 20 (decimal) 200MHz: 40 (decimal)

Jumper setting Mem_addr

[21:19] HR, WRo

AG101


Bit Name Type Description Reset Value Reset Type 300MHz: 60 (decimal) 350MHz: 70 (decimal) 400MHz: 80 (decimal) 500MHz: 100 (decimal) 600MHz: 120 (decimal) 700MHz: 140 (decimal)

2 PLL1STSEL R/W Select the method for waiting PLL1 stability. 1: Wait for the stable signal provided by PLL1. 0: Wait 1.22ms.

0x0 HR

1 PLL1STABLE RO PLL1 meets lock-in time stability. Cleared when FCS starts. Set when PLL1 is stable. 0x0 HR, WR, SMR

0 PLL1DIS R/W 1: Disable PLL1 0: Enable PLL1


HR

AG101


67

4.1.15.13 PLL/DLL Control Register 1 (Offset == 0x34) Table 19. PLL/DLL Control Register 1 (PDLLCR1).


23-20 PWMCLKDIV R/W PWM clock is generated with 5.0 MHz divided by (PWMCLKDIV + 1) 0x00 HR

19-16 I2SCLKDIV R/W

The I2S main clock is the clock that PLL3 divided by the I2SCLKDIV counter. 0000: 2.08 MHz 0001: 2.87MHz 0010: 4.17 MHz 0011: 5.74 MHz 0100: 8.33 MHz 0101: 11.48 MHz 0110: 12.5 MHz 0111: 16.7 MHz 1000: 25 MHz Other: Reserved

0x6 HR

15-11 - - Reserved - -


0x0 HR




HR



0x0 HR




HR

4.1.15.14 AHB Module Clock Off Control Register (Offset == 0x38) Table 20. AHB Module Clock Off Control Register (AHBMCLKOFF).


14 USBDOFF R/W Turn off the clock of the USB 2.0 device controller. 0x0 HR, WR

AG101


Bit Name Type Description Reset Value Reset Type 13 - - Reserved - - 12 MACOFF R/W Turn off the clock of the Ethernet MAC controller. 0x0 HR, WR

11-8 - - Reserved - - 7 DMAOFF R/W Turn off the clock of the DMA controller. 0x0 HR, WR 6 - - Reserved - - 5 SDRAMOFF R/W Turn off the clock of the SDRAM controller. 0x0 HR, WR 4 EBIOFF R/W Turn off the clock of the external bus interface module. 0x0 HR, WR 3 SMCOFF R/W Turn off the clock of the SRAM controller. 0x0 HR, WR 2 - - Reserved - - 1 APBBRGOFF R/W Turn off the clock of the AHB to APB Bridge module. 0x0 HR, WR 0 - - Reserved - -

4.1.15.15 APB Module Clock Off Control Register (Offset == 0x3C) Table 21. APB Module Clock Off Control Register (APBMCLKOFF).


23 PWMOFF R/W Turn off the clock of the PWM controller. 0x0 HR, WR 22 I2COFF R/W Turn off the clock of the I2C controller. 0x0 HR, WR 21 INTCOFF R/W Turn off the clock of the internal controller. 0x0 HR, WR 20 GPIOOFF R/W Turn off the clock of the GPIO module. 0x0 HR, WR 19 RTCOFF R/W Turn off the clock of the RTC module. 0x0 HR, WR 18 WDTOFF R/W Turn off the clock of the WDT module. 0x0 HR, WR 17 TIMEROFF R/W Turn off the clock of the TIMER module. 0x0 HR, WR

16-12 - - Reserved - - 11 Reserved R/W 0x0 HR, WR

10-9 - - Reserved - - 8 STUART R/W Turn off the clock of the STUART controller. 0x0 HR, WR 7 - - Reserved - - 6 I2S/AC97OFF R/W Turn off the clock of the I2S/AC97 controller. 0x0 HR, WR 5 SDCOFF R/W Turn off the clock of the SD controller. 0x0 HR, WR 4 BTUART R/W Turn off the clock of the BTUART controller. 0x0 HR, WR 3 Reserved R/W 0x0 HR, WR 2 SSPOFF R/W Turn off the clock of the SSP controller. 0x0 HR, WR 1 CFCOFF R/W Turn off the clock of the CF controller 0x0 HR, WR 0 - - Reserved - -

AG101


69

AG101


4.1.15.16 Driving Capability and Slew Rate Control Register 0 (Offset == 0x40) Table 22. Driving Capability and Slew Rate Control Register 0 (DCSRCR0).


31-28 EBICTRL_DCSR R/W Fine-tune the output driving capability of the

X_memaddr[14:0]. 0xA HR, WR

27-24 EBIDATA_DCSR R/W Fine-tune the output driving capability of the

X_memdata[31:0]. 0xA HR, WR

23-20 SDRAMCS_DCSR R/W Fine-tune the output driving capability of the

SDRAMC’s chip select pins. 0xA HR, WR

19-16 SDRAMCTL_DCSR R/W Fine-tune the output driving capability of the

SDRAMC’s control pins. 0xA HR, WR

15-12 CKE_DCSR R/W Fine-tune the output driving capability of the SDRAMC’s CKE pin. 0xA HR, WR

11-8 DQM_DCSR R/W Fine-tune the output driving capability of the SDRAMC’s DQM pins. 0xA HR, WR

7-4 SDCLK_DCSR R/W Fine-tune the output driving capability of the SDRAMC’s clock output pins. 0xA HR, WR

3-0 SRAM_DCSR R/W

Control the slew rate and output driving capability of the X_memaddr[24:15], X_smc_be_b[3:0], X_smc_we_b, X_smc_cs_b[3:0] and X_smc_oe_b pins. SRAM_DCSR[3] controls the slew rate 1: Slow. 0: Fast. SRAM_DCSR[2:0] control the output driving capability. 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR



31-28 TRIAHB_DCSR R/W

Control the slew rate and driving capability of the AMBA bus output pins. TRIAHB_DCSR[3] controls the slew rate 1: Slow. 0: Fast. TRIAHB_DCSR[2:0] control the output driving capability. 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

AG101


71


27-24 USBDEV_DCSR R/W

Control the slew rate and driving capability of the TM&T output pins. USBDEV_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. USBDEV_DCSR[2:0] control the output driving capability. 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

23-20 Reserved

19-16 I2C_DCSR R/W

Control the slew rate and driving capability of the CPU ICE output pins and I2C output pins. I2S_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. I2S_DCSR[2:0] control the output driving capability 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

15-12 MAC_DCSR R/W

Control the slew rate and driving capability of the Ethernet MAC controller output pins. MAC_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. MAC_DCSR[2:0] control the output driving capability111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

11-8 CFC_DCSR R/W

Control the slew rate and driving capability of the CF controller output pins. CFC_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. CFC_DCSR[2:0] control the output driving capability 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

7-4 GPIO_DCSR R/W

Control the slew rate and driving capability of the GPIO output pins. GPIO_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. GPIO_DCSR[2:0] control the output driving capability111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

3-0 INTC_DCSR R/W

Control the slew rate and driving capability of the X_int_irqn and X_int_fiqn. INTC_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. INTC_DCSR[2:0] control the output driving capability111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

AG101




31-28 SD_DCSR R/W

Control the slew rate and driving capability of the SD controller output pins. SD_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. SD_DCSR[2:0] control the output driving capability 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

27-24 SSP_DCSR R/W

Control the slew rate and driving capability of the SSP controller output pins. SSP_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. SSP_DCSR[2:0] control the output driving capability 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

23-20 I2SAC97_DCSR R/W

Control the slew rate and driving capability of the I2S / AC97 controller output pins. I2SAC97_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. I2SAC97_DCSR[2:0] control the output driving capability 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

19-16 PMU_DCSR R/W

Control the slew rate and driving capability of the X_reset_b and X_pwren pins. PMU_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. PMU_DCSR[2:0] control the output driving capability111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

15-12 FFUART_DCSR R/W

Control the slew rate and driving capability of the FFUART controller output pins. FFUART_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. FFUART_DCSR[2:0] control the output driving capability 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

AG101


73


11-8 BTUART_DCSR R/W

Control the slew rate and driving capability of the BTUART controller output pins. BTUART_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. BTUART_DCSR[2:0] control the output driving capability 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

7-4 Reserved R/W 0x1 HR, WR

3-0 STUART_DCSR R/W

Control the slew rate and driving capability of the STUART controller output pins. STUART_DCSR[3] controls the slew rate. 1: Slow. 0: Fast. STUART_DCSR[2:0] control the output driving capability 111: 16mA, 110: 14mA, 101: 12mA, 100: 10mA 011: 8mA, 010: 6mA, 001: 4mA, 000: 2mA

0x1 HR, WR

4.1.15.19 SDRAM Signal Hold Time Control (Offset == 0x4C) Table 25. SDRAM Signal Hold Time Control (SDRAMHTC).


31-28 RCLK_DLY R/W

These bits control the delay value of the SDRAMC clock to latch “X_memdata”. 0000: lead 2.4ns, 0001: lead 1.8ns, 0010: lead 1.2ns 0011: lead 0.6ns, 0100: same phase, 0101: lag 0.6ns 0110: lag 1.2ns, 0111: lag 1.8ns.

0x4 HR, WR

27-24 CTL_WCLK_DLY R/W

These bits control the delay value of the SDRAMC clock to clock out the CKE, CSB, RASB, CASB, WEB, OEB, BA, ADDR and DQM. 0000: lead 2.4ns, 0001: lead 1.8ns, 0010: lead 1.2ns 0011: lead 0.6ns, 0100: same phase, 0101: lag 0.6ns 0110: lag 1.2ns, 0111: lag 1.8ns.

0x4 HR, WR

23-20 DAT_WCLK_DLY R/W

These bits control the delay value of the SDRAMC clock to clock out the X_memdata. 0000: lead 2.4ns, 0001: lead 1.8ns, 0010: lead 1.2ns 0011: lead 0.6ns, 0100: same phase, 0101: lag 0.6ns 0110: lag 1.2ns, 0111: lag 1.8ns.

0x4 HR, WR

19 - - Reserved - -

18 EBICTRL_DCSR[4] R/W

Control the slew rate of the X_memaddr[14:0] 1: Slow. 0: Fast.

0x0 HR, WR

17 EBIDATA_DCSR[4] R/W

Control the slew rate of the X_memdata[31:0] 1: Slow. 0: Fast.

0x0 HR, WR

AG101



16 SDRAMCS_DCSR[4] R/W

Control the slew rate of the SDRAM chip select signal pins. 1: Slow. 0: Fast.

0x0 HR, WR

15 SDRAMCTL_DCSR[4] R/W

Control the slew rate of the SDRAM control pins. 1: Slow. 0: Fast.

0x0 HR, WR

14 CKE_DCSR[4] R/W Control the slew rate of the SDRAM CKE pin. 1: Slow. 0: Fast.

0x0 HR, WR

13 DQM_DCSR[4] R/W Control the slew rate of the SDRAM DQM pins. 1: Slow. 0: Fast.

0x0 HR, WR

12 SDCLK_DCSR[4] R/W

Control the slew rate of the SDRAM clock pins. 1: Slow. 0: Fast.

0x0 HR, WR

11-0 - - Reserved - - 4.1.15.20 Power Manager Scratch Pad Register 0 ~ 15 (Offset == 0x50 ~ 0x8C)

The Clocks and Power Manager Unit contain 16 32-bit registers that can be used to save processor configuration

information in any desired format. The PSPR 0 ~ 15 are holding registers that are powered during Sleep Mode and

are reset by Hardware Reset and Watchdog.

Table 26. Power Manager Scratch Pad Register (PSPR).

Bit Name Type Description Reset Value Reset Type 31-0 PSPR R/W Scratch Pad Register. Keep contents in Sleep Mode. 0x0000 0000 HR, WR

4.1.15.21 AHB DMA and APB DMA Routing Control

FIAG101CA0 provides two DMA controllers; one is an AHB component and the other is embedded in the APB

Bridge. The AHB DMA controller provides eight (8) channels, while the APB Bridge DMA controller provides

four (4) channels.

There are fifteen (15) request/grant pairs to select from for each DMA channel in the APB DMA controller. When

using the APB DMA channels, users should program the APB Bridge DMA controller to select the DMA request

source and DMA grant destination. Please refer to Chapter 15 on AHB to APB Bridge (APB Bridge) for

programming the registers whose offsets are 0x8C, 0x9C, 0xAC, and 0xBC.

AG101


75

The following mapping table shows the APB Bridge DMA channels and the device DMA request/grant. For

example, the CFC can use APB Bridge DMA channel A/B/C/D for DMA transfer, and its DMA request/grant is

arranged in pair number 1. The UART1 can employ APB Bridge DMA channels C and D for the data transmission,

and its DMA request/grant is arranged in pair number 3.

Table 27. Mapping of the AHB/APB DMA channels and the Device DMA REQ/GNT.

AHB DMA REQ/GNT Num

Device Controller REQ/GND Pair

APB DMA Channel Alternative

Routing Control Register Offset

(1) 0x0001 CFC 0x1 Channel D/C/B/A 0xa0 (2) 0x0010 SSP I 0x2 Channel D/C/B/A 0xa4 (3) 0x0011 UART1 (TX) 0x3 Channel D/C 0xa8 (4) 0x0100 UART1 (RX) 0x4 Channel B/A 0xac (5) 0x0101 UART2 (TX) 0x5 Channel D/C 0xb0 (6) 0x0110 UART2 (RX) 0x6 Channel B/A 0xb4 (7) 0x0111 SDC 0x7 Channel D/C/B/A 0xb8 (8) 0x1000 AC97 0x8 Channel D/C/B/A 0xbc (9) 0x1001 Reserved 0x9 Channel D 0xc0 (10) 0x1010 Reserved Reserved (11) 0x1011 USB2.0 Device 0xb Channel D/C/B/A 0xc8 (12) 0x1100 Reserved 0xc Channel C 0xcc (13) 0x1101 Reserved 0xd Channel B/A 0xd0 (14) 0x1110 EXT REQ0 0xe Channel D/C/B/A 0xd4 (15) 0x1111 EXT REQ1 0xf Channel D/C/B/A 0xd8 Not supported UART4 (TX) Channel D/C Not supported UART4 (RX) Channle B/A

The device controller depicted in the above table can also utilize the AHB DMA for the DMA transfers. There are

several registers used to control the routing of the device DMA request/grant, to and from the two DMA controllers.

Column five (5) of the above table depicts the associated registers for each device.

The above table shows the control bits for each routing control register. For example, to utilize channel 3 of the

AHB DMA controller for CFC DMA transfer, you should program the control register, at offset 0xA0, with the

value of 0x0C (4’b1011). 4.1.15.22 AHB DMA REQ/ACK Connection Configuration Status (Offset == 0x90)

The register records which device is using the AHB DMAC channel. The following table shows the relationship

between devices and AHB DMAC req/ack pair number.

AG101


AG101


77

Table 28. AHB DMA REQ/ACK Connection Configuration Status.


31-28 CH7_REQACK_PAIR RO

0000: Unconnected 0001 ~ 1111: Device req/ack number

0x0000 0000 HR, WR



0x0000 0000 HR, WR



0x0000 0000 HR, WR



0x0000 0000 HR, WR



0x0000 0000 HR, WR



0x0000 0000 HR, WR



0x0000 0000 HR, WR



0x0000 0000 HR, WR

4.1.15.23 Jumper Setting Status (Offset == 0x9C)

This register records the values of the external jumper setting.

Table 29. Table of Jumper Setting Status.


16-15 DLLSETTING RO

DLL output frequency range. 11: 200 ~ 400MHz 10: 100MHz ~ 200MHz 01: 50 MHz ~ 100 MHz. 00: 25 MHz ~ 50 MHz.

Depend on Jumper Set Mem_addr

[13:12]

14-11 DIVAHBCLK RO

Clock ratio: cpu:bus 0000: 1:1 0001: 2:1 0010: 3:1 0011: 4:1 0100: 5:1 0101: 6:1 0110: 3:2 0111: 5:2 1000: 8:1

Depend on Jumper Set

{ hmastlock, hmaster[2:0]

}

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Bit Name Type Description Reset Value Reset Type 1001: 10:1 1010: 12:1 1011: 14:1 1100: 15:1 1101: 18:1 1110: 20:1 1111: Reserved

10 ENDIAN R) Endian setting 1: big endian 0: little endian


[14]

9 TIMER_TEST RO Timer test

Depend on Jumper Set- Mem_addr

[24]

8 DEBUG_SEL RO Debug selection


[23]

7 DEBUG_EN RO Debug enable


[22]

-

6-4 PLL1SETTING RO

000: PLL1’s frequency is 20 times OSC (100.0 MHz) 001: PLL1’s frequency is 40 times OSC (200.0 MHz) 010: PLL1’s frequency is 60 times OSC (300.0 MHz) 011: PLL1’s frequency is 70 times OSC (350.0 MHz) 100: PLL1’s frequency is 80 times OSC (400.0 MHz) 101: PLL1’s frequency is 100 times OSC (500.0 MHz) 110: PLL1’s frequency is 120 times OSC (600.0 MHz) 111: PLL1’s frequency is 140 times OSC (700.0 MHz)


[21:19]

3 INTCPUOFF RO 1: Turn off the internal CPU


[18]

2-1 INI_MBW RO Indicate ROM/Flash data bus width 00/01/10/11 : 8/16/32/reserved


[17:16]

0 PLLDIS RO 1: PLL/DLL disabled. System clock is OSC.


[15]

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4.1.15.24 CFC REQ/ACK Connection Configuration (Offset == 0xA0)

Table 30. CFC REQ/ACK Connection Configuration.


3 DMACUSED R/W 1: Use AHB DMA 0: Use APB DMA

0 HR, WR

2:0 CHANNEL R/W Indicate which channel is used in DMAC 000: CH0 ~ 111:CH7

000 HR, WR

4.1.15.25 SSP1 REQ/ACK Connection Configuration (Offset == 0xA4)

The SSP1 can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA controller, it is

only necessary to set bit 3 to “1” and program bits [2:0] to indicate which channel is used.

Table 31. SSP1 REQ/ACK Connection Configuration.



0 HR, WR


000 HR, WR

4.1.15.26 UART1 TX REQ/ACK Connection Configuration (Offset == 0xA8)

The UART1 TX can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA controller,

it is only necessary to set bit 3 to “1” and program bits [2:0] to indicate which channel is used.

Table 32. UART1 TX REQ/ACK Connection Configuration.



0 HR, WR


000 HR, WR

4.1.15.27 UART1 RX REQ/ACK Connection Configuration (Offset == 0xAC)

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The UART1 RX can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA controller,


Table 33. UART1 RX REQ/ACK Connection Configuration.



0 HR, WR


000 HR, WR

4.1.15.28 UART2 TX REQ/ACK Connection Configuration (Offset == 0xB0)

The UART2 TX can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA controller,


Table 34. UART2 TX REQ/ACK Connection Configuration.



0 HR, WR


000 HR, WR

4.1.15.29 UART2 RX REQ/ACK Connection Configuration (Offset == 0xB4)

The UART2 RX can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA controller,


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Table 35. UART2 RX REQ/ACK Connection Configuration.



0 HR, WR


000 HR, WR

4.1.15.30 SDC REQ/ACK Connection Configuration (Offset == 0xB8)

The SD can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA controller, it is only

necessary to set bit 3 to “1” and program bits [2:0] to indicate which channel is used.

Table 36. SDC REQ/ACK Connection Configuration.



0 HR, WR


000 HR, WR

4.1.15.31 AC97/I2S REQ/ACK Connection Configuration (Offset == 0xBC)

The AC97/I2S can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA controller, it

is only necessary to set bit 3 to “1” and program bits [2:0] to indicate which channel is used.

Table 37. AC97 REQ/ACK Connection Configuration.



0 HR, WR


000 HR, WR

4.1.15.32 USB2.0 Device REQ/ACK Connection Configuration (Offset == 0xC8)

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The USB2.0 device can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA

controller, it is only necessary to set bit 3 to “1” and program bits [2:0] to indicate which channel is used. Table 38. USB2.0 Device REQ/ACK Connection Configuration.



0 HR, WR


000 HR, WR

4.1.15.33 External Device0 REQ/ACK Connection Configuration (Offset == 0xD4)

The external device0 can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA

controller, it is only necessary to set bit 3 to “1” and program bits [2:0] to indicate which channel is used.

Table 39. External Device0 REQ/ACK Connection Configuration.



1 HR, WR


000 HR, WR

4.1.15.34 External Device1 REQ/ACK Connection Configuration (Offset == 0xD8)

The external device1 can use the AHB/APB DMA function. If the user wishes to implement the AHB DMA

controller, it is only necessary to set bit 3 to “1” and program bits [2:0] to indicate which channel is used.

Table 40. External Device1 REQ/ACK Connection Configuration.



1 HR, WR

2:0 CHANNEL R/W Indicate which channel is used in DMAC 001 HR, WR

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000: CH0 ~ 111:CH7

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5 N1213 General Descriptions

The N1213 is a general-purpose 32-bit embedded RISC processor. It includes separate instruction/data caches,

separate instruction/data scratchpad, a memory management unit, and a JTAG ICE interface. The CPU core is

eight stage pipeline. To improve the overall performance, the N1213 CPU core also contains dynamic branch

prediction to reduce branch penalties.

The N1213 CPU core 16/32 allows mixed instruction sets and uses the AMBA AHB interface to communicate

with external devices. The N1213 CPU core is suitable for a wide range of applications, including personal, home

and office applications.

Block Diagram

The block diagram of the N1213 CPU core is shown below. Detailed description of each functional block can be

found in the following sections.

External Bus Interface

AHB

Instruction LM

Instruction Cache

Data LM

Data Cache

MMU

N12 Execution Core

JTAG/ICE Embedded program tracer I/F

DTLB ITLB

HSMP

DMA

Figure 6. N1213 Functional Blocks.

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5.1.1 N12 Execution core

The N1213 processes 16/32bit mixed instruction with eight stage pipeline structure. There are thirty two (32)

general purpose registers in total. The N1213 supports user and super-user mode.

5.1.2 Dynamic branch prediction

N1213 supports a dynamic branch prediction mechanism with 128-entry brancn BTB. With an accurate branch

prediction, the BTB can resolve control dependency and reduce branch penalty.

5.1.3 Instruction Cache (ICache)

The ICache makes use of a program’s locality to improve the processor’s performance. It stores the most recently

used instructions in a fast local memory. As a result, the next time the instructions are executed, the processor can

access the instructions from the ICache, instead of taking the long access latency to fetch the instruction from

external slow memory. The ICache is at 32KB with 4-way set-associativity. The least recently used (LRU)

algorithm is used as the replacement strategy.

5.1.4 Data Cache (DCache)

The DCache also utilizes the program’s locality to improve the processor’s performance. It stores the most recently

used data in a fast local memory. To retrieve the stored data, the processor can access them from the DCache

instead of taking the long latency in accessing the data from external slow memory. The DCache is 32KB with

4-way associativity.

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5.1.5 Memory Management Unit (MMU)

The MMU provides address translation and permission check mechanism for memory management. The N1213

MMU has a 4-entry fully associate iTLB, 8-entry fully associate dTLB and 128-entry 4-way set-associative main

TLB. It caches the most recently used page descriptors for address translation which leads to a greater overall

performance. A hardware page table walking logic is provided optional to handle TLB replacement upon

TLB-miss.

5.1.6 Local memory

The local memory is a fast on-chip SRAM located near the processor core. Performance-critical code or data can

be pre-fetched to local memory and executed at full CPU speed. This is particularly useful for embedded

applications. N1213 has 16Kbytes for instruction and 16kbytes for data.

5.1.7 Bus Interface Unit (BIU)

The bus interface unit accepts memory access requests from the CPU core, executes instruction, and access data

through the external system bus. The bus request can be issued either by the ICache or DCache where the ICache

has the higher priority.

The N1213 bus interface unit implements the AMBA AHB 2.0 interface protocol. The AHB is a pipelined bus

protocol which uses a single phase clocking methodology. This enables designers to easily employ it for SoC

integration. For more details on AHB specifications, please refer to AMBA 2.0 specification.

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5.1.8 ICE

N1213 processor core provides an embedded In-Circuit-Emulator (ICE) for debugging. The ICE is the basic debugging component. The following figure shows the basic Andes debug environment. There are three devices: Debug Host, protocol converter and Andes core with embedded ICE

Debug

Host protocol

converter

TAP

Andes core

ICE

Debug Host: A debug host is a machine which runs debug software (debugger). The programmer manipulates it to control the embedded ICE. Typically, the debug host is a personal computer (PC). Protocol converter: The protocol converter is the interface between the TAP and the debug host. It converts the command received from debug host to a series of JTAG instruction. The protocol converter uses these JTAG instructions to access processor information through embedded ICE and responds the result to the debug host. ICE: The ICE aids the programmer/hardware engineer to identify software/hardware bugs by allowing access to information on the processor through the ICE.

5.1.9 Power Saving Control Unit

The Power Saving Control Unit controls the overall chip clocking to reduce operating power consumption. When

the software program detects that CPU is idle for a predefined time interval, it instructs the processor to go into

power saving modes. The processor supports two (2) power saving modes: IDLE and SLEEP. In IDLE mode, the

clocks of all the processor’s internal circuits except power saving control module are stopped. In SLEEP mode, the

clocks of all the processor’s internal circuits including PLL are stopped. While in the power saving modes, the

processor can be awakened through either an interrupt or an ICE activity. The start-up time is sixteen (16) cycles if

the processor is awoken from IDLE mode, and approximately 5µs when it is awoken from SLEEP mode.

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6 AHB Controller General Description

The AHB Controller serves as a mechanism to control the device priority in accessing the Advanced

High-performance Bus (AHB). This mechanism provides a highly configurable arbiter and decoder with a flexible

programming model to save SoC integration efforts. The mechanism contains three (3) components:

1. Arbiter

2. Decoder

3. Multiplexer

Features

● AMBA 2.0 compliance

● Multi-level arbitration

● Round-robin arbitration

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89

Block Diagram

AHB Master 1 AHB Master 2 .......... AHB Master 9

Arbiter

Decoder

Multiplexer

AHB Slave 1 AHB Slave 2 .......... AHB Slave 22

Request Grant

Select

default slave 0&

default master 0

Figure 7. Block Diagram of AHB Controller.

The following sections contain detailed descriptions for each of the AHB Controller’s main building block.

6.1.1 Arbiter

The arbiter prioritzes data access requests from the AHB Master. The arbiter supports both multi-level and round

robin functions. The multi-level function supports a two-level algorithm, level 1 and level 0. Level 1 is assigned a

higher priority than level 0. When masters on level 1 and masters on level 0 simultaneously request the bus, the bus

would always grant the bus to masters on level 1 first. The round robin algorithm assigns the masters currently

accessing the bus the lowest priority master in the next arbitration on the same level. All masters can be

programmed and assigned to either level 1 or level 0.

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6.1.2 Decoder

The decoder in an AMBA system is used to perform a centralized address decoding function. It generates each

AHB device’s select signal when the arbiter grants the bus to a master. The decoder decodes the master’s address

command and then sends a select signal to the device the master is currently accessing.

6.1.3 Multiplexer

All AHB masters’ signals grant multiplex to AHB slaves, and all AHB slaves’ response signals also select

multiplex to AHB.

Programming Model 6.1.4 Summary of the AHB Controller Registers Table 41. Summary of the AHB Controller Registers.

Address (Offset) Type Description Reset Value +0x00 R/W AHB Slave 0 Base/Size Register 0x9010_0000 +0x04 R/W AHB Slave 1 Base/Size Register 0x9050 0000 +0x08 R/W AHB Slave 2 Base/Size Register 0x9807 0000 +0x0C R/W AHB Slave 3 Base/Size Register 0x9020 0000 +0x10 R/W AHB Slave 4 Base/Size Register 0x0008 0000 +0x14 R/W AHB Slave 5 Base/Size Register 0x9030 0000 +0x18 R/W AHB Slave 6 Base/Size Register 0x100B 0000 +0x1C R/W AHB Slave 7 Base/Size Register 0x9040 0000 +0x24 R/W AHB Slave 9 Base/Size Register 0x9060 0000 +0x30 R/W AHB Slave 12 Base/Size Register 0x9090 0000 +0x34 R/W AHB Slave 13 Base/Size Register 0x90A0 0000 +0x38 R/W AHB Slave 14 Base/Size Register 0x90B0 0000 +0x3C R/W AHB Slave 15 Base/Size Register 0x90C0 0000 +0x40 Reserved +0x44 R/W AHB Slave 17 Base/Size Register 0x90E0 0000 +0x48 R/W AHB Slave 18 Base/Size Register 0x90F0 0000 +0x4C R/W AHB Slave 19 Base/Size Register 0x9200 0000 +0x50 Reserved +0x54 R/W AHB Slave 21 Base/Size Register 0xA008 0000

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91

Address (Offset) Type Description Reset Value +0x58 R/W AHB Slave 22 Base/Size Register 0xB007 0000 +0x80 R/W Priority Control Register 0x0000 0000 +0x84 R/W Transfer Control Register 0x0000 0000 +0x88 R/W Interrupt Control Register 0x0000 0000


The following subsections describe the AHB controller registers in more detail.

6.1.5.1 AHB Slave n Base/Size Register (Offset == 0x00 ~ 0x58) Table 42. AHB Slave 0 Base/Size Register.

Bit Name Type Description 31-20 BaseAddr R/W Base Address [31:20]

19-16 SizeAddr R/W

Size of Address Space [19:16] 0000: 1M 0001: 2M 0010: 4M 0011: 8M 0100: 16M 0101: 32M 0110: 64M 0111: 128M 1000: 256M 1001: 512M 1010: 1G 1011: 2G 1100-1111: Reserved.

15-0 -- -- Reserved Notes:

The Base/Size register for all the slaves has the same format and the same definitions of the bit fields.

The setting value of the base address is multiple of the setting value of the space size. For example, if base address [31:20] is set to 0x002, which means the base address is 2M, then the space size must be 1M or 2M. That is to say, space size [19:16] must be 0 or 1.

6.1.5.2 Priority Control Register (Offset == 0x80)

The arbiter supports a two-level mechanism to arbitrate master requests. Each master can be programmed to higher

level or lower level. Table 43 shows the bit assignment of the priority control register.

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Table 43. Priority Control Register.

Bit Name Type Description 31-10 -- -- Reserved

9-1 PLevel R/W Bit n represents the level of master n. 1: Higher level 0: Lower level

0 -- -- Reserved

The AHB Controller provides nine (9) Request/Grant signal pairs. The following table lists the mappings of AHB

masters and Request/Grant pairs.

Table 44. AHB Master Request Routing Table.

Request No. AHB Master 6 External Master (X_hm6_hbusreq) 5 External Master (X_hm5_hbusreq) 4 Ethernet MAC 3 DMA 2 N1213 1 APB Bridge 0 Dummy Master

6.1.5.3 Transfer Control Register (Offset == 0x84)

Table 45 shows the bit assignment of this register.

Table 45. Transfer Control Register.

Bit Name Type Description 31-2 -- -- Reserved.

1 TransCtl R/W

Burst transfer interrupt. 0: Burst transfer is never interrupted except when receiving Error/Split/Retry response. 1: Burst transfer is always interrupted.

0 -- -- Reserved

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6.1.5.4 Interrupt Control Register (Offset == 0x88)

Table 46 shows the bit assignment of this register.

Table 46. Interrupt Control Register.

Bit Name Type Description 31-25 -- -- Reserved

24 IntrSts R/W

Interrupt Status 0: Interrupt does not occur 1: Interrupt occurs The interrupt is cleared by writing zero to the register bit.

23-22 -- -- Reserved

21-20 Response R/W

Response Status When decoder receives a non-existing address, the decoder responds to the register. 00: OK response 01: ERROR response 10: RETRY response 11: SPLIT response

19-17 -- -- Reserved

16 IntsMask R/W Interrupt Mask 0: Disable 1: Enable

15-14 Reserved

0 Remap R/W

Remap function When writing a ‘1’ to this bit, the base/size configuration of AHB slaves 4 and 6 will be interchanged. This bit can only be programmed once.

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7 DMA Controller Please refer to ATFDMAC020_DS_v1.8.pdf.

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95

8 Ethernet MAC 10/100 Controller General Description

The Ethernet MAC 10/100 controller is a high quality 10/100 Ethernet controller with DMA function. It includes

AHB wrapper, DMA engine, on-chip memory (TX FIFO and RX FIFO), MAC, and MII interface.

The MAC controller is an ethernet controller that provides AHB master capability and full compliance with IEEE

802.3 100Mb/s and 10Mb/s specification with MII interface. The DMA controller handles all data transfers

between system memory and on-chip memory. With the DMA engine, it can reduce CPU loading, maximize

performance and minimize FIFO size. The MAC controller has on-chip memory for buffering, so external local

buffer memory is not needed. The MII interface can support two specific data rates, 10 Mb/s and 100 Mb/s. The

functionality is identical at both data rates, as are the signal timing relationships; with the only difference being

their distinct nominal clock frequencies.

Features of the MAC controller are described in the following feature list.

Features

● Support a DMA engine for transmitting and receiving packets

● Support a programmable AHB burst size

● Support transmit and receive interrupt mitigation

● Contain two (2) independent TX/RX FIFO (2K bytes each)

● Support half and full duplex modes

● Support flow control for full duplex and backpressure for half duplex

● Support MII interface

● Support little-endian

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Block Diagram

MII

TXMAC

(TXMAC)

RXMAC

(RXMAC)

REGIST(REG)

TXFIFO

RXFIFO

TXDMA

(TXD)

RXDMA

(RXD)

(AHBM)

AHBBus

AHB_SLAVE

(AHBS)

DMA_ARBITER(DARB)

PWR_MANAGE

(PM)

AHB_MASTER

Figure 8. MAC Block Diagram.

Functional Block Description 8.1.1 AHB_MASTER

The AHB_MASTER implements the AHB master function of the MAC controller.

When the TXDMA move transmit packets from the transmit buffer into the TX FIFO, the TXDMA would request

the DMA_ARBITER to use the DMA channel. After the DMA_ARBITER grants the DMA channel to the

TXDMA, it would initiate a burst transfer to the AHB_MASTER through the DMA_ARBITER, while the

AHB_MASTER would initiate a read operation to AHB bus. The AHB_MASTER would then pass the transmit

packet data from the transmit buffer to the TXDMA.

When the RXDMA wants to move receive packets from the RX FIFO to the receive buffer, the RXDMA would

request the DMA_ARBITER to use the DMA channel. After the DMA_ARBITER grants the DMA channel to the

RXDMA, it would initiate a burst transfer to the AHB_MASTER through the DMA_ARBITER, while the

AHB_MASTER would initiate a write operation to AHB bus. The AHB_MASTER would then pass the receive

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97

packet data from the RXDMA to the receive buffer.

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8.1.2 AHB_SLAVE

The AHB_SLAVE implements the AHB slave function of the MAC controller.

When other AHB master requires writing data to the registers in the MAC controller, it would initiate a write

operation to AHB bus, and the AHB_SLAVE would respond to the operation. Thereafter the AHB_SLAVE would

pass the write data to the REGIST. If other AHB master requires reading data from the registers in the MAC

controller, it would initiate a read operation to AHB bus, and the AHB_SLAVE would respond to the operation.

Thereafter the AHB_SLAVE would pass the read information to the REGIST and get the read data. Finally it

passes the read data to AHB bus and the read operation is finished.

The AHB_SLAVE responds to the AHB bus with an OKAY message under normal conditions, while an Error

message is issued if an error in the AHB transction is detected.

8.1.3 DMA_ARBITER

The DMA_ARBITER acts as the bridge between the 2 sets of control signals from the TXDMA and the RXDMA,

while serving as the control signal to the AHB_MASTER. It acts as the arbiter to decide whether the TXDMA or

the RXDMA is entitled to use the AHB_MASTER.

8.1.4 TXDMA

The 3 main functions of the TXDMA are: (1) reading the transmit descriptor and writing transmit status back to the

transmit descriptor, (2) moving the transmit packet data from the transmit buffer to the TX FIFO, and (3)

controlling the read / write action of the TX FIFO.

When there is a packet to be transmitted to Ethernet, the TXDMA would first fetch the transmit descriptor to get

the descriptor’s information and transmit buffer base address and size. Secondly, the TXDMA would move the

transmit packet data from the corresponding transmit buffer to the TX FIFO. Thirdly, the TXDMA would request

the TXMAC to send the packet to the network. Fourthly, the TXMAC would read the transmit packet data with the

help of the TXDMA, and send it to the network. After finishing the transmission of the packet, the TXMAC would

send the transmit status to the TXDMA. The TXDMA would then write the transmit status back to the transmit

descriptor.

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8.1.5 RXDMA

The 3 main functions of the RXDMA are: (1) reading the receive descriptor and writing the receive status to the

receive descriptor, (2) moving the receive packet data from the RX FIFO to the receive buffer, and (3) controlling

the read/write action of the RX FIFO.

When there is a packet to be sent to the MAC controller, it would first be received by the RXMAC and saved in the

RX FIFO. Thereafter, the RXDMA would detect there are packets in the RX FIFO, and move the received packets

from the RX FIFO to the receive buffer. Finally, the RXDMA would write the receive status to the receive

descriptor.

8.1.6 TXMAC

The TXMAC would transmit packets from TX FIFO to Ethernet. The TXMAC includes CRC, preamble, jam

generator and transmit state machine.

When there is a packet to be transmitted, the TXMAC would detect the Ethernet’s status, and would not start the

transmission until the Ethernet is idle. Then the TXMAC would add preamble and CRC to this packet, and send the

packet to Ethernet. If the TXMAC detects collision when transmitting the packet, it would send the jam to Ethernet,

and wait back off time to retransmit the packet. Figure 9 is the transmit frame control flow of the TXMAC.

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Transmit Enable ?

Transmit frame

Assemble Frame

Ethernet busy?

yes

no

yes

Start Transmission

no

CollisionDetect?

TransmissionDone ?

no

no

yes

Send Jam

Increment collisioncounter

Collisioncounter>=16?

Compute backoff

Wait backoff time

yes

no

yes

Done:Excessive Collision

Error

Done:Transmit OK

Done:Transmit Disable

Delay to start of next slot

Figure 9. Transmit Frame Control Flow of TXMAC.

8.1.7 RXMAC

The RXMAC receives packets from Ethernet to RX FIFO. The RXMAC includes address recognition circuit, CRC

check circuit, and receive state machine.

When there is a packet incoming from Ethernet, the RXMAC would acknowledge the RXDMA and the RXDMA

would pass the received packet data to RX FIFO from RXMAC. After the RXMAC finishes receiving the packet, it

would check if the receive packet address is correct and if CRC check is successful or not. If the result is correct, it

would acknowledge the RXDMA to save the packet in RX FIFO; otherwise the packet would be discarded.

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101

Figure 10 is the receive frame control flow of the RXMAC.

Receive Frame

Receive Enable ?

Start Receive

RecognizeAddress ?

Check Frame toolong or short ?

no

yes

no

yes

Check CRC ?

no

no

Check CRC ?

yes

Done:Report Frame

message

Done:Receive OK

yes yes

no

Done:Report CRC

message

Done:Report CRC andFrame message

Done:Receive Disabled

Figure 10. Receive Frame Control Flow of RXMAC.

8.1.8 REGIST

The REGIST stores the registers of the MAC controller. Other AHB masters could read/write these registers with

the help of the AHB_SLAVE.

8.1.9 PWR_MANAGE

The PWR_MANAGE manages the power control logic of the MAC controller. In normal mode, the

PWR_MANAGE would turn on AHB bus clock, transmit clock and receive clock. If software forces the MAC

controller into power down mode, the PWR_MANAGE would turn off the AHB bus clock, the transmit clock and

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the receive clock to some modules to reduce power consumption.

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103

Function Descriptions 8.1.10 Half-Duplex (CSMA/CD Access Protocol)

Half-Duplex Ethernet is the traditional form of Ethernet that uses the CSMA/CD (Carrier Sense Multiple Access

with Collision Detection) protocol with two or more CSMA/CD stations sharing a common transmission medium.

To transmit a frame, a station must wait for an idle period on the medium when no other station is transmitting. It

transmits the frame by broadcasting it over the medium so that it is "heard" by all other stations on the network. If

another device tries to send data at the same time, a "collision" is said to occur. The transmitting station then

intentionally transmits a "jam sequence" to ensure all stations are notified of the frame transmission failure due to a

collision. The station then remains silent for a random period of time before attempting to transmit again. This

process is repeated until the frame is eventually transmitted successfully.

The basic rules for transmitting a frame are the following. The network is monitored for a "carrier", or the presence

of a transmitting station. This process is known as "carrier sense". If an active carrier is detected, then transmission

is deferred. The station continues to monitor the network until the carrier ceases. If an active carrier is not detected

and the period of absence of carrier is equal to or greater than the interframe gap, then the station immediately

begins transmission of the frame.

If a collision is detected while sending the frame, the transmitting station stops sending the frame data and sends a

32-bit "jam sequence". If the collision is detected while transmitting the frame preamble, the transmitting station

will complete sending the frame preamble before starting the transmission of the jam sequence. The jam sequence

is transmitted to ensure that the length of the collision is sufficient to be noticed by the other transmitting stations.

After sending the jam sequence, the transmitting station waits a random period of time that is chosen using a

random number generator before starting the transmission process. This process is called "back off".

Having the colliding stations wait a random period of time before retransmitting reduces the probability of a

repeated collision. If repeated collisions occur, the transmission is then repeated; but the random delay is increased

with each attempt. This further reduces the probability of another collision. This process repeats until a station

transmits a frame without collision. Once a station successfully transmits a frame, it clears the collision counter

used to increase the back off time after each repeated collision.

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8.1.11 Full-Duplex Ethernet

The IEEE 802.3x standard defines a second mode of operation for Ethernet called the "full-duplex", which

bypasses the CSMA/CD protocol. The CSMA/CD protocol is "half-duplex". This implies that a station may either

transmit data or receive data, but never executing both at the same time. Full-duplex mode allows two stations to

simultaneously exchange data over a point-to-point link that provides independent transmit and receive paths.

Since each station can simultaneously transmit and receive data, the aggregate throughput of the link is effectively

doubled. A 10 Mb/s station operating in full-duplex mode provides a maximum bandwidth of 20 Mb/s while a

full-duplex 100 Mb/s station provides 200 Mb/s of bandwidth.

Full-duplex operation is restricted to links which meet the following criteria:

1. The physical medium must be capable of supporting simultaneous transmission and reception without

interference. Media specifications which meet this requirement are 10BASE-T, 10BASE-FL,

100BASE-TX, 100BASE-FX, 100BASE-T2, 1000BASE-CX, 1000BASE-SX, 1000BASE-LS, and

1000BASE-T. The following media specifications do not support full duplex: 10BASE5, 10BASE2,

10BASE-FP, 10BASE-FB, and 100BASET4.

Full-duplex operation is restricted to point-to-point links. Since there is no contention for a shared medium,

collisions would not occur and the CSMA/CD protocol becomes unnecessary, frames may be transmitted

back-to-back with the interval of the minimum interframe gap.

Both stations on the link must be capable of, and be configured for, full-duplex operation.

Full-duplex operation offers several major advantages:

1. Throughput is doubled by permitting simultaneous transmission and reception. The efficiency of the link is

improved by eliminating the potential for collisions.

Segment lengths are no longer limited by the timing requirements of half-duplex Ethernet which ensure

collisions are propagated to all stations within the required 512 bit times. For example, 100BASE-FX is

limited to 412-meter segment length in half-duplex mode, but may support segment lengths as long as 2

km in full-duplex mode.

8.1.12 Loop Back

When the MAC controller is configured in the “Loop Back” mode, the MAC controller would loop the transmit

data back through MII interface; the MAC controller would then receive the data it transmits. Users can test the

control circuit and data path in this mode.

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8.1.13 Transmit Descriptors and Data Buffers

The MAC controller uses the descriptor ring to manage the transmit buffers. The transmit descriptors and buffers

are all in system memory. The MAC controller moves the transmit packet data from the transmit buffers in system

memory to the TX FIFO inside the MAC controller and then transmits the packet to Ethernet. The transmit

descriptors that reside in the system memory act as pointers to the transmit buffers.

There is one descriptor ring for transmission. The base address of the transmit ring is in the Transmit Ring Base

Address Register (TXR_BADR, offset: 20h ~ 23h). Each transmit descriptor contains a transmit buffer. A transmit

buffer consists of either an entire frame or part of a frame, but it cannot exceed a single frame. The transmit

descriptor contains transmit buffer status and the transmit buffer can only contain the transmit data.

System Memory

Tx Buffer

Tx buffer size

:

:

:

:

:

Descriptor 1

Descriptor n

MAC register

TXR_BADR(Transmit RingBase Address)

EDOTR=1(EndDescriptor of

Transmit Ring)

Transmit Ring

Tx Buffer base address

Control Tx buffer size

TXDMA-OWN Status

Figure 11. Transmit Ring Descriptor Structure.

The transmit descriptor structure is as follows.

Note that the start address of each transmit descriptor must be 16-byte alignment.

TXDES0 TXDMA_OWN Status TXDES1 Control TX buffer size

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TXDES2 TX buffer base address

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TXDES0: contains the transmit frame status and descriptor ownership information.

Bit Name Description

31 TXDMA_OWN

TXDMA_OWN - TXDMA ownership bit When set, it indicates that the descriptor is owned by the MAC controller. When reset, it indicates that the software owns the descriptor. The MAC controller clears this bit when it completes the frame transmission.

30-2 Reserved

1 TXPKT_EXSCOL TXPKT_EXSCOL When set, it indicates that the frame transmission is aborted after 16 collisions. It is valid only when FTS = 1.

0 TXPKT_LATECOL TXPKT_LATECOL When set, it indicates that the frame transmission is aborted due to late collision. It is valid only when FTS = 1.

TXDES1: contains the control bits and transmit buffer size.


31 EDOTR EDOTR - End Descriptor of Transmit Ring When set, it indicates that the descriptor is the last descriptor of the transmit ring.

30 TXIC

TXIC - Transmit Interrupt on Completion. When set, the MAC controller would assert transmit interrupt after the present frame has been transmitted. It is valid only when FTS = 1 and bits 8 ~ 14 (TXINT_THR, TXINT_CNT) of Interrupt Timer Control Register = 0.

29 TX2FIC TX2FIC - Transmit to FIFO Interrupt on Completion. When set, the MAC controller would assert transmit interrupt after the present frame has been moved into the TX FIFO. It is valid only when FTS = 1.

28 FTS FTS - First Transmit Segment descriptor. When set, it indicates that this is the first descriptor of a TX packet.

27 LTS LTS - Last Transmit Segment descriptor. When set, it indicates that this is the last descriptor of a TX packet.

26-11 Reserved 10-0 TXBUF_SIZE Transmit buffer size in byte. When the size is 0, the descriptor is discarded.

TXDES2: contains transmit buffer base address.

Bit Name Description 31-0 TXBUF_BADR Transmit buffer base address

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8.1.14 Receive Descriptors and Data Buffers

The MAC controller uses a descriptor ring to manage the receive buffers. The receive descriptors and buffers are

all in system memory. The MAC controller first stores the packet received from the network in the RX FIFO and

then moves the received packet data to the receive buffers in system memory. The receive descriptors that reside in

the system memory act as pointers to the receive buffers.

There is one descriptor ring for reception. The base address of the receive ring is in the Receive Ring Base Address

Register (RXR_BADR, offset: 24h ~ 23h). Each receive descriptor contains a receive buffer. A receive buffer

consists of either an entire frame or part of a frame, but it cannot exceed a single frame. The receive descriptor

contains receive buffer status and the receive buffer can only contain the receive packet data.

System Memory

Rx Buffer

Rx buffer size

:

:

:

:

:

Descriptor 1

Descriptor n

MAC register

RXR_BADR(Receive RingBase Address)

EDORR=1(EndDescriptor ofReceive Ring)

Receive Ring

Rx Buffer base address

Control Rx buffer size

RXDMA_OWN Status

Figure 12. Receive Ring Descriptor Structure.

The receive descriptor structure is as follows:

Note that the start address of each receive descriptor must be 16-byte alignment.

RXDES0 RXDMA_OWN Status RXDES1 Control RX buffer size (DW boundary) RXDES2 RX buffer base address (DW boundary)

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RXDES0: contains the receive frame status and descriptor ownership information.


31 RXDMA_OWN

RXDMA_OWN - RXDMA ownership bit When set, it indicates that the descriptor is owned by the MAC controller. When reset, it indicates that the descriptor is owned by the software. The MAC controller clears this bit when it completes the frame reception or when the receive buffer of the receive descriptor is full.

30 Reserved

29 FRS FRS - First Receive Segment descriptor. When set, it indicates that this is the first descriptor of a received packet.

28 LRS LRS - Last Receive Segment descriptor. When set, it indicates that this is the last descriptor of a received packet.

27-23 Reserved

22 RX_ODD_NB RX_ODD_NB - Receive Odd Nibbles When set, it indicates receiving a packet with odd nibbles.

21 RUNT RUNT - Runt packet. When set, it indicates that the received packet length is less than 64 bytes. Bits 23 ~ 0 are valid only when the FRS = 1.

20 FTL FTL - Frame Too Long When set, it indicates that the received packet length exceeds 1518 bytes.

19 CRC_ERR CRC_ERR - CRC error When set, it indicates that a CRC error occurs on the received packet.

18 RX_ERR RX_ERR - Receive error When set, it indicates that a receive error happens when receiving a packet.

17 BROADCAST BROADCAST - Broadcast frame. When set, it indicates that the received packet is a broadcast frame.

16 MULTICAST MULTICAST - Multicast frame. When set, it indicates that the received packet is a multicast frame.

15-11 Reserved 10-0 RFL - Receive Frame Length

RXDES1: contains the control bits and receive buffer size.


31 EDORR EDORR - End Descriptor of Receive Ring When set, it indicates that the descriptor is the last descriptor of the receive ring.

30-11 Reserved

10-0 RXBUF_SIZE Receive buffer size. The unit is 1 byte. Receive buffer size must be double-word boundary (4-byte aligned).

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RXDES2: contains receive buffer base address.


31-0 RXBUF_BADR Receive buffer base address. Receive buffer base address must be double-word boundary (4-byte aligned).

8.1.15 Transmitting Packets

As the software transmits a packet to Ethernet, it would move the packet data into the transmit buffer first. The

software then writes the packet's length and position into the transmit descriptor and triggers the MAC controller to

send the packet. After the entire packet has been moved into the TX FIFO, the MAC controller begins to transmit it

to Ethernet. While the packet has been transmitted, the MAC controller would assert an interrupt to notify software

that the packet has been transmitted successfully.

8.1.16 Receiving Packets

When there is an incoming packet, the MAC controller would first save the received packet in the RX FIFO if both

CRC result and address check result are correct. After the incoming packet is successfully saved in RX FIFO, the

MAC controller would initiate Direct Memory Access (DMA) function to move the received packet data from the

RX FIFO to the system memory. Then the MAC controller would assert an interrupt to notify software that the

packet has been received successfully.

8.1.17 Ethernet Address Filtering

The MAC controller can be set up to recognize any one of the Ethernet receive address groups described in the

following table.

RX_BROADPKT: bit 17 of MAC Control Register (offset: 88h)

RX_MULTIPKT: bit 16 of MAC Control Register (offset: 88h)

RCV_ALL: bit 12 of MAC Control Register (offset: 88h)

HT_MULTI_EN: bit 9 of MAC Control Register (offset: 88h)

RCV_ ALL

RX_ MULTIPKT

RX_ BROADPKT

HT_ MULTI_EN

Group Description

0 0 0 0 A The MAC controller receives the following frame: The frame’s destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller.

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RCV_ ALL

RX_ MULTIPKT

RX_ BROADPKT

HT_ MULTI_EN

Group Description

0 0 0 1 B

The MAC controller receives the following frames: The frame’s destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller.The frame’s destination address is a multicast address. Pass the address filtering of the multicast address hash table in the MAC controller.

0 0 1 0 C

The MAC controller receives the following frames: The frame’s destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller. The frame’s destination address is a broadcast address.

0 0 1 1 D

The MAC controller receives the following frames: The frame’s destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller. The frame’s destination address is a multicast address. Pass the address filtering of the multicast address hash table in the MAC controller. The frame’s destination address is a broadcast address.

0 1 X X E

The MAC controller receives the following frames: The frame’s destination address exactly matches the MAC_ADR (offset: 08h ~ 0Fh) of the MAC controller. The frame’s destination address is a multicast address.

1 X X X F The MAC controller supports reception of all frames on the network regardless of their destination address.

8.1.18 DMA Arbitration Scheme

The DMA arbitration scheme is decided by RX_THR_EN (bit 9 of DMA Burst Length and Arbitration Control

Register, offset: 30h ~ 33h). When RX_THR_EN = 0, the DMA arbitration scheme would do a fair arbitration

between the TXDMA and RXDMA. The last one using the DMA channel has lower priority to get the DMA

channel when both TXDMA and RXDMA request the DMA channel at the same time.

When RX_THR_EN is set and if the used space in the RX FIFO is larger than or equal to the RXFIFO_HTHR

(bits 8 ~ 6 of DMA Burst Length and Arbitration Control Register, offset: 30h ~ 33h), the RXDMA would be

assigned the higher priority over the TXDMA for using the DMA channel. The RXDMA maintains its higher

priority status until the used space in the RX FIFO is less than or equal to the RXFIFO_LTHR (bits 5 ~ 3 of DMA

Burst Length and Arbitration Control Register, offset: 30h ~ 33h). Thereafter, the TXDMA receives the higher

priority over the RXDMA. Hence software must set RXFIFO_HTHR to be greater than RXFIFO_LTHR to keep

the MAC controller work correctly.

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8.1.19 Flow Control

The MAC controller implements flow control function. It supports IEEE802.3x flow control for full-duplex mode

and backpressure for half-duplex mode.

The IEEE802.3x flow control is used in full-duplex mode. Suppose A and B are transmitting and receiving packets

from each other in full-duplex mode, if the RX FIFO in B is nearly full, B would send a pause frame to A in order

to avoid received packet loss. Then A would be inhibited from transmitting packets for a specified period of time.

B would consume the received data during the specified period of time. A would continue to send packets to B

after the pause time has lapsed. Features of the flow control in full-duplex mode are briefly stated as follows:

1. The software could configure the pause time of the pause frame.

2. The MAC controller could send the pause frame according to the low / high threshold of RX FIFO.

3. The software could send the pause frame by writing the register.

The back pressure mode is used in half-duplex mode. Suppose A is transmitting and receiving packets in

half-duplex mode, if the RX FIFO in A is nearly full, A would send a jam pattern to generate collisions to avoid

packets from being saved into the RX FIFO when there are incoming packets. A would consume the received data

as soon as possible during the period of time. A would not send a jam pattern to receive packets again when the RX

FIFO is not nearly full. Features of the back pressure mode are briefly stated as follows:

1. The software could configure the length of the jam.

2. The MAC controller could send the jam according to the low/high threshold of RX FIFO.

Programming Model 8.1.20 Summary of the MAC Controller Registers

Table 47 lists the MAC controller registers.

Table 47. MAC controller Register Summary.

Address (Offset) Register Name Reset Value +0x00 Interrupt Status Register 0x0000_0010 +0x04 Interrupt Mask Register 0x0000_0000 +0x08 MAC Most Significant Address Register 0x0000_0000 +0x0C MAC Least Significant Address Register 0x0000_0000 +0x10 Multicast Address Hash Table 0 Register 0x0000_0000

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Address (Offset) Register Name Reset Value +0x14 Multicast Address Hash Table 1 Register 0x0000_0000 +0x18 Transmit Poll Demand Register 0x0000_0000 +0x1C Receive Poll Demand Register 0x0000_0000 +0x20 Transmit Ring Base Address Register 0x0000_0000 +0x24 Receive Ring Base Address Registe 0x0000_0000 +0x28 Interrupt Timer Control Register 0x0000_0000 +0x2C Automatic Polling Timer Control Register 0x0000_0000 +0x30 DMA Burst Length and Arbitration Control Register 0x0000_2edf +0x34

| +0x84

Reserved

+0x88 MAC Control Register 0x0000_0000 +0x8C MAC Status Register 0x0000_1000 +0x90 PHY Control Register 0x0000_0002 +0x94 PHY Write Data Register 0x0000_0000 +0x98 Flow Control Registe 0x0000_0000 +0x9C Back Pressure Register 0x0000_0000 +0xA0

| +0xC0

Reserved

+0xC4 Test Seed Register 0x0000_0000 +0xC8 DMA/FIFO State Register 0x0000_0000 +0xCC Test Mode Register 0x0000_0000 +0xD0 Reserved +0xD4 TX_MCOL and TX_SCOL Counter Register 0x0000_0000 +0xD8 RPF and AEP Counter Register 0x0000_0000 +0xDC XM and PG Counter Register 0x0000_0000 +0xE0 RUNT_CNT and TLCC Counter Register 0x0000_0000 +0xE4 CRCER_CNT and FTL_CNT Counter Register 0x0000_0000 +0xE8 RLC and RCC Counter Register 0x0000_0000 +0xEC BROC Counter Register 0x0000_0000 +0xF0 MULCA Counter Register 0x0000_0000 +0xF4 RP Counter Register 0x0000_0000 +0xF8 XP Counter Register 0x0000_0000

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The following abbreviations are used for register definitions:

● R/W: Read/Write

● RC: Read Clear

● RO: Read Only

● R/W1C: Read/Write 1 Clear

8.1.21.1 Interrupt Status Register (Offset == 0x00) Table 48. Interrupt Status Register.

Bit RW Type Default Value Name Description

31-10 Reserved 9 RC 1’h0 PHYSTS_CHG PHY link status change 8 RC 1’h0 AHB_ERR AHB error 7 RC 1’h0 RPKT_LOST Received packet lost due to RX FIFO full 6 RC 1’h0 RPKT_SAV Packets received into RX FIFO successfully

5 RC 1’h0 XPKT_LOST Packets transmitted to Ethernet lost due to late collision or excessive collision

4 RC 1’h0 XPKT_OK Packets transmitted to Ethernet successfully 3 RC 1’h0 NOTXBUF Transmit buffer unavailable 2 RC 1’h0 XPKT_FINISH TXDMA has moved data into the TX FIFO 1 RC 1’h0 NORXBUF Receive buffer unavailable 0 RC 1’h0 RPKT_FINISH RXDMA has received packets into RX buffer successfully

8.1.21.2 Interrupt Mask Register (Offset == 0x04) Table 49. Interrupt Mask Register.


31-10 Reserved 9 R/W 1’h0 PHYSTS_CHG_M Interrupt mask of ISR [9] 8 R/W 1’h0 AHB_ERR_M Interrupt mask of ISR [8] 7 R/W 1’h0 RPKT_LOST_M Interrupt mask of ISR [7] 6 R/W 1’h0 RPKT_SAV_M Interrupt mask of ISR [6] 5 R/W 1’h0 XPKT_LOST_M Interrupt mask of ISR [5]

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4 R/W 1’h0 XPKT_OK_M Interrupt mask of ISR [4] 3 R/W 1’h0 NOTXBUF_M Interrupt mask of ISR [3] 2 R/W 1’h0 XPKT_FINISH_M Interrupt mask of ISR [2] 1 R/W 1’h0 NORXBUF_M Interrupt mask of ISR [1] 0 R/W 1’h0 RPKT_FINISH_M Interrupt mask of ISR [0]

8.1.21.3 MAC Most Significant Address Register (Offset == 0x08) Table 50. MAC Most Significant Address Register.


31-16 Reserved 15-0 R/W 16’h0 MAC_MADR The most significant 2 bytes of MAC address

8.1.21.4 MAC Least Significant Address Register (Offset == 0x0C) Table 51. MAC Least Significant Address Register.


31-0 R/W 32’h0 MAC_LADR The least significant 4 bytes of MAC address 8.1.21.5 Multicast Address Hash Table 0 Register (Offset == 0x10) Table 52. Multicast Address Hash Table 0 Register.


31-0 R/W 32’h0 MAHT0 Multicast address hash table bytes 3 ~ 0 (Hash table 31:0) 8.1.21.6 Multicast Address Hash Table 1 Register (Offset == 0x14) Table 53. Multicast Address Hash Table 1 Register.


31-0 R/W 32’h0 MAHT1 Multicast address hash table bytes 3 ~ 0 (Hash table 63:32)

AG101


8.1.21.7 Transmit Poll Demand Register (Offset == 0x18) Table 54. Transmit Poll Demand Register.


31-0 WO 32’h0 TXPD

When writing any value to the register, the MAC controller would read transmit descriptor process and check the txdma_own bit. If txdma_own = 1, then transmit buffer data is moved into the TX FIFO. The read value of the register is always 0.

8.1.21.8 Receive Poll Demand Register (Offset == 0x1C) Table 55. Receive Poll Demand Register.


31-0 WO 32’h0 RXPD

When writing any value to the register, the MAC controller would read receive descriptor process and check the rxdma_own bit, if rxdma_own = 1, then the receive packet data is moved from the RX FIFO into the receive buffer in the system memory. The read value of the register is always 0.

8.1.21.9 Transmit Ring Base Address Register (Offset == 0x20) Table 56. Transmit Ring Base Address Register.


31-0 R/W 32’h0 TXR_BADR Base address of the transmit ring. The base address must be 16-byte aligned. The MAC controller would treat base address bits 3 ~ 0 as 0 when reading descriptors if bits 3 ~ 0 are not zero.

8.1.21.10 Receive Ring Base Address Register (Offset == 0x24) Table 57. Receive Ring Base Address Register.


31-0 R/W 32’h0 RXR_BADR Base address of the receive ring. The base address must be 16-byte aligned. The MAC controller would treat base address bits 3 ~ 0 as 0 when reading descriptors if bits 3 ~ 0 are not zero.

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8.1.21.11 Interrupt Timer Control Register (Offset == 0x28) Table 58. Interrupt Timer Control Register.


31-16 Reserved

15 R/W 1’h0 TXINT_TIME_SEL

This field defines the period of TX cycle time. When set, TX cycle time is 100Mbps mode 81.92 µs 10Mbps mode 819.2 µs When cleared, TX cycle time is 100Mbps mode 5.12 µs 10Mbps mode 51.2 µs

14-12 R/W 3’h0 TXINT_THR

This field defines the maximum number of transmit interrupts that can be pending before an interrupt is generated. When TXINT_THR is not equal to 0, the MAC controller would issue a transmit interrupt if the transmit packet number transmitted by the MAC controller reaches TXINT_THR. When TXINT_THR = 0 and TXINT_CNT = 0, whether a transmit interrupt is issued or not depends on TXIC in TXDES1.

11-8 R/W 4’h0 TXINT_CNT

This field defines the maximum wait time to issue transmit interrupt after a packet has been transmitted by the MAC controller. The time unit is 1 TX cycle time. When TXINT_CNT = 0, the function would be disabled. When TXINT_THR = 0 and TXINT_CNT = 0, whether a transmit interrupt is issued or not depends on TXIC in TXDES1.

7 R/W 1’h0 RXINT_TIME_SEL

This field defines the period of RX cycle time. When set, RX cycle time is 100Mbps mode 81.92 µs 10Mbps mode 819.2 µs When cleared, RX cycle time is 100Mbps mode 5.12 µs 10Mbps mode 51.2 µs

6-4 R/W 3’h0 RXINT_THR

This field defines the maximum number of receive interrupts that can be pending before an interrupt is generated. When RXINT_THR is not equal to 0, the MAC controller would issue a receive interrupt when the receive packet number received by the MAC controller reaches RXINT_THR. If RXINT_THR = 0 and RXINT_CNT = 0, a receive interrupt will be issued when the MAC controller finishes receiving a receive packet.

3-0 R/W 4’h0 RXINT_CNT

This field defines the maximum wait time to issue receive interrupt after a packet has been received by the MAC controller. The time unit is 1 RX cycle time. When RXINT_CNT = 0, the function would be disabled. If RXINT_THR = 0 and RXINT_CNT = 0, a receive interrupt will be issued when a packet is received by the MAC controller.

AG101


Recommended value = 32’h0000_1010

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The Interrupt Timer Control Register allows the software driver to reduce the number of transmit interrupt (ISR[4])

and receive interrupt (ISR[0]) by setting the register. This could lower CPU utilization for handling a large number

of interrupts.

The register defines 2 threshold values for the receive packet number and transmit packet number, and two

associated timers. The threshold value defines the maximum number of receive or transmit interrupts that can be

pending before an interrupt is generated. The timer defines the maximum wait time to issue transmit/receive

interrupt after a packet has been transmitted/received by the MAC controller. The threshold value and timer

combination allow for the batching of several packets into a single interrupt with a limit on how long it can be

pending. This can prevent throughput from being impeded in heavy traffic, while the time limit prevents resources

from being held for too long in low traffic.

The mitigation mechanism is similar for both receive and transmit interrupts. A counter (TXPKT_CNT) resides in

the MAC controller to count the packets transmitted by the MAC controller. When the counter reaches

TXINT_THR while TXINT_THR is not 0, the MAC controller would issue transmit interrupt. There is also a

counter (RXPKT_CNT) in the MAC controller that counts the packets received by the MAC controller. When the

counter reaches RXINT_THR while RXINT_THR is not 0, the MAC controller would issue a receive interrupt.

TXPKT_CNT is cleared when transmit interrupt is issued. RXPKT_CNT is cleared when receive interrupt is

issued.

The MAC controller would issue a transmit interrupt under the following conditions:

TXINT_THR = 0 TXINT_CNT = 0 MAC Controller Action

True True Issues transmit interrupt after packet is transmitted and TXIC of the packet is set.Clears TXPKT_CNT.

True False Issues transmit interrupt after a packet is transmitted and timer reaches the value of TXINT_CNT. Clears TXPKT_CNT.

False True Issues transmit interrupt if TXPKT_CNT = TXINT_THR. Clears TXPKT_CNT.

False False

Issues transmit interrupt if the following condition holds: TXPKT_CNT = TXINT_THR TXPKT_CNT = 1 and timer reaches the value of TXINT_CNT Clears TXPKT_CNT.

AG101


The MAC controller issues a receive interrupt under the following conditions:

RXINT_THR = 0 RXINT_CNT = 0 MAC Controller Action

True True Issues receive interrupt after packet is received by the MAC controller. Clears RXPKT_CNT.

True False Issues receive interrupt after packet is received by the MAC controller and timer reaches the value of RXINT_CNT. Clears RXPKT_CNT.

False True Issues receive interrupt if RXPKT_CNT = RXINT_THR. Clears TXPKT_CNT.

False False

Issues receive interrupt if the following condition holds: RXPKT_CNT = RXINT_THR RXPKT_CNT = 1 and timer reaches the value of RXINT_CNT Clears RXPKT_CNT.

8.1.21.12 Automatic Polling Timer Control Register (Offset == 0x2C)

The Automatic Polling Timer Control Register allows the MAC controller to automatically poll the descriptors,

hence lowering the CPU occupancy. When the transmit automatic poll function is enabled, the MAC controller

would automatically poll the transmit descriptor as the transmit automatic poll timer expires. If the function is

disabled, software needs to write Transmit Poll Demand Register (Offset: 18h ~ 1Bh) to trigger the MAC

controller to read transmit descriptors after software prepared the transmit packets in transmit buffers.

When the receive automatic poll function is enabled, the MAC controller would automatically poll the receive

descriptor as the receive automatic poll timer expires. If the function is disabled, software needs to write Receive

Poll Demand Register (Offset: 1Ch ~ 1Fh) to trigger the MAC controller to read receive descriptors after software

released the receive descriptors to the MAC controller

Table 59. Automatic Polling Timer Control Register.

Bit RW Type

Default Value Name Description

31-13 -- -- -- Reserved

12 R/W 1’h0 TXPOLL_TIME_SEL

This field defines the period of TX poll time. When set, TX poll time is 100Mbps mode 81.92 µs 10Mbps mode 819.2 µs When cleared, TX poll time is 100Mbps mode 5.12 µs 10Mbps mode 51.2 µs

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123

Bit RW Type


11-8 R/W 4’h0 TXPOLL_CNT

This field defines the period of transmit automatic polling time. The unit is 1 TX poll time. When TXPOLL_CNT is not equal to 0, the MAC controller would poll the transmit descriptor automatically. If TXPOLL_CNT = 0, the MAC controller would not poll the transmit descriptor automatically.

7-5 -- -- -- Reserved

4 R/W 1’h0 RXPOLL_TIME_SEL

This field defines the period of RX poll time. When set, RX poll time is 100Mbps mode 81.92 µs 10Mbps mode 819.2 µs When cleared, RX poll time is 100Mbps mode 5.12 µs 10Mbps mode 51.2 µs

3-0 R/W 4’h0 RXPOLL_CNT

This field defines the period of receive automatic polling time. The unit is 1 RX poll time. When RXPOLL_CNT is not equal to 0, the MAC controller would poll the receive descriptor automatically. If RXPOLL_CNT = 0, the MAC controller would not poll the receive descriptor automatically.

Recommended value = 32’h0000_0001 8.1.21.13 DMA Burst Length and Arbitration Control Register (Offset == 0x30) Table 60. DMA Burst Length and Arbitration Control Register.

Bit RW Type


31-10 -- -- -- Reserved 9 R/W 1’h0 RX_THR_EN Enable RX FIFO threshold arbitration.

8-6 R/W 3’h0 RXFIFO_HTHR

The RX FIFO high threshold value for arbitration. When the used space in the RX FIFO is larger than or equal to the RX FIFO high threshold value, the RXDMA has higher priority than the TXDMA when using the DMA channel. The RXDMA keeps the higher priority until the used space in the RX FIFO is less than or equal to the RX FIFO low threshold value. Then the TXDMA gets higher priority than the RXDMA. So software must set RXFIFO_HTHR larger than RXFIFO_LTHR to keep the MAC controller work correctly. The unit is 256 bytes. 3’d0: Threshold = 0 3’d1: Threshold = 1/8 space of RX FIFO, 256 bytes 3’d2: Threshold = 2/8 space of RX FIFO, 512 bytes 3’d3: Threshold = 3/8 space of RX FIFO, 768 bytes 3’d4: Threshold = 4/8 space of RX FIFO, 1024 bytes 3’d5: Threshold = 5/8 space of RX FIFO, 1280 bytes 3’d6: Threshold = 6/8 space of RX FIFO, 1536 bytes 3’d7: Threshold = 7/8 space of RX FIFO, 1792 bytes

AG101


Bit RW Type


5-3 R/W 3’h0 RXFIFO_LTHR

The RX FIFO low threshold value for arbitration. When the used space in the RX FIFO is less than or equal to the RX FIFO low threshold value, the TXDMA has higher priority than the RXDMA when using the DMA channel. The unit is 256 bytes. 3’d0: Threshold = 0 3’d1: Threshold = 1/8 space of RX FIFO, 256 bytes 3’d2: Threshold = 2/8 space of RX FIFO, 512 bytes 3’d3: Threshold = 3/8 space of RX FIFO, 768 bytes 3’d4: Threshold = 4/8 space of RX FIFO, 1024 bytes 3’d5: Threshold = 5/8 space of RX FIFO, 1280 bytes 3’d6: Threshold = 6/8 space of RX FIFO, 1536 bytes 3’d7: Threshold = 7/8 space of RX FIFO, 1792 bytes

2 R/W 1’h0 INCR16_EN This field defines whether the MAC controller could use INCR16 burst command in AHB bus.



Recommended value = 32’h0000_0390

There are some limitations for use of INCR4, INCR8, and INCR16. The user must observe these limitations, as follows:

AHB Bus Clock Range Limitation on AHB Bus Side of SDRAM Controller

25MHz (25MHz not included) ~ 15MHz hready must assert low at least 1 AHB bus clock during every 3 data phases.





133MHz ~ 125MHz hready must assert low at least 1 AHB bus clock during every 39 data phases.

Because the MAC controller always uses WORD as the transfer size on AHB bus, the above limitation on the data

phases applies only to WORD-size transfer. If the system cannot meet the limitation, INCR4 / INCR8 / INCR16

will not be enabled while using the MAC controller. In that case, the MAC controller can only use INCR to

transfer data in such systems. The user must ensure that the above limitation is met in the system before enabling

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INCR4 / INCR8 / INCR16 while using the MAC controller.

AG101


8.1.21.14 MAC Control Register (Offset == 0x88) Table 61. MAC Control Register.

Bit RW Type


31-18 -- -- -- Reserved 17 R/W 1’h0 RX_BROADPKT Receive broadcast packet. 16 R/W 1’h0 RX_MULTIPKT Receive all multicast packets. 15 R/W 1’h0 FULLDUP Full duplex 14 R/W 1’h0 CRC_APD Append CRC to transmitted packet. 13 -- -- -- Reserved 12 R/W 1’h0 RCV_ALL Not check incoming packet’s destination address 11 R/W 1’h0 RX_FTL Store incoming packet even if its length is great than 1518 bytes. 10 R/W 1’h0 RX_RUNT Store incoming packet even if its length is less than 64 bytes.

9 R/W 1’h0 HT_MULTI_EN Enable storing incoming packet if the packet passes hash table address filtering and is a multicast packet.

8 R/W 1’h0 RCV_EN Receiver enable 7 -- 1’h0 -- Reserved

6 R/W 1’h0 ENRX_IN_ HALFTX

Enable packet reception when transmitting packet in half duplex mode.

5 R/W 1’h0 XMT_EN Transmitter enable 4 R/W 1’h0 CRC_DIS Disable CRC check when receiving packets. 3 R/W 1’h0 LOOP_EN Internal loop-back.

2 R/W 1’h0 SW_RST Software reset. Writing 1 to this bit would enable software reset. Software reset would last 64 AHB bus clocks, and then activate auto-clear.

1 R/W 1’h0 RDMA_EN Enable receive DMA channel. If this bit is zero, reception is stopped immediately.

0 R/W 1’h0 XDMA_EN Enable transmit DMA channel. If this bit is zero, transmission is stopped immediately.

8.1.21.15 MAC Status Register (Offset == 0x8C) Table 62. MAC Status Register.

Bit RW Type


31-12 -- -- -- Reserved 11 RC 1’h0 COL_EXCEED Collision amount exceeds 16. 10 RC 1’h0 LATE_COL Transmitter detects late collision.

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Bit RW Type


9 RC 1’h0 XPKT_LOST Packets transmitted to Ethernet lost due to late collision or excessive collision.

8 RC 1’h0 XPKT_OK Packets transmitted to Ethernet successfully. 7 RC 1’h0 RUNT Receiver detects a runt packet. 6 RC 1’h0 FTL Receiver detects a frame that is too long.

5 RC 1’h0 CRC_ERR Incoming packet’s CRC check result is invalid, unless the CRC_DIS bit is set.

4 RC 1’h0 RPKT_LOST Received packets lost due to RX FIFO full. 3 RC 1’h0 RPKT_SAVE Packets received into RX FIFO successfully. 2 RC 1’h0 COL Incoming packet dropped due to collision. 1 RC 1’h0 BROADCAST Incoming packet for broadcast address. 0 RC 1’h0 MULTICAST Incoming packet for multicast address.

8.1.21.16 PHY Control Register (Offset == 0x90) Table 63. PHY Control Register.

Bit RW Type


31-28 -- -- -- Reserved

27 R/W 1’h0 MIIWR Initialize a write sequence to PHY by setting this bit to 1. This bit would be auto cleared after the write operation is finished.

26 R/W 1’h0 MIIRD Initialize a read sequence to PHY by setting this bit to 1. This bit would be auto cleared after the read operation is finished.

25-21 R/W 5’h0 REGAD PHY register address 20-16 R/W 5’h0 PHYAD PHY address 15-0 RO 16’h0 MIIRDATA Read data from PHY.

8.1.21.17 PHY Write Data Register (Offset == 0x94) Table 64. PHY Write Data Register.

Bit RW Type


31-16 -- -- -- Reserved 15-0 R/W 16’h0 MIIWDATA Write data to PHY.

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8.1.21.18 Flow Control Register (Offset == 0x98) Table 65. Flow Control Register.

Bit RW Type


31-16 R/W 15’h0 PAUSE_TIME

Pause time in pause frame. The unit is 512 bit times. The 512 bit times is 100Mbps mode 5.12µs 10Mbps mode 51.2µs

15-12 R/W 4’hA FC_HIGH

RX FIFO free space high threshold. Send a pause frame with pause time = 32’h0000 when RX FIFO free space is larger than the high threshold. The unit is 128 bytes. Default value is 4’hA.

11-8 R/W 4’h4 FC_LOW

RX FIFO free space low threshold. Send a pause frame with pause time set in bits 31 ~ 16 when RX FIFO free space is lower than the low threshold. The unit is 128 bytes. Default value is 4’h4.

7-5 -- -- -- Reserved 4 RC 1’h0 RX_PAUSE Receive pause frame. 3 RO 1’h0 TXPAUSED Packet transmission is paused due to receive pause frame.

2 R/W 1’h0 FCTHR_EN Enable flow control threshold mode. Enable transmit pause frame for high / low threshold.

1 R/W 1’h0 TX_PAUSE Transmit pause frame. Software can set this bit to send pause frame. Auto cleared after pause frame has been transmitted.

0 R/W 1’h0 FC_EN Flow control mode enable 8.1.21.19 Back Pressure Register (Offset == 0x9C) Table 66. Back Pressure Register.

Bit RW Type


31-12 -- -- -- Reserved

11-8 R/W 4’h4 BK_LOW

RX FIFO free space low threshold. MAC would generate the jam pattern when RX FIFO free space is lower than the low threshold while packets are incoming. The unit is 128 bytes. Default value is 4’h4.

7-4 R/W 4’h0 BKJAM_LEN

Back pressure jam length. 4’h0: 4 bytes 4’h6: 256 bytes 4’h1: 8 bytes 4’h7: 512 bytes 4’h2: 16 bytes 4’h8: 1024 bytes 4’h3: 32 bytes 4’h9: 1518 bytes 4’h4: 64 bytes 4’hA: 2048 bytes

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Bit RW Type


4’h5: 128 bytes Other: 4 bytes 3-2 -- -- -- Reserved

1 R/W 1’h0 BK_MODE Back pressure address mode. 1: Generate jam pattern when packet address matches. 0: Generate jam pattern when any packet is incoming.

0 R/W 1’h0 BK_EN Back pressure mode enable 8.1.21.20 Test Seed Register (Offset == 0xC4) Table 67. Test Seed Register.

Bit RW Type


31-14 -- -- -- Reserved 13-0 R/W 14’h0 Test_seed Test seed

8.1.21.21 DMA/FIFO State Register (Offset == 0xC8) Table 68. DMA/FIFO State Register.

Bit RW Type


31 RO 1’h0 TXD_REQ TXDMA request 30 RO 1’h0 RXD_REQ RXDMA request 29 RO 1’h0 DARB_TXGNT TXDMA grant 28 RO 1’h0 DARB_RXGNT RXDMA grant 27 RO 1’h1 TXFIFO_EMPTY TX FIFO is empty 26 RO 1’h1 RXFIFO_EMPTY RX FIFO is empty

25-15 -- -- -- Reserved 14-12 RO 3’h0 TXDMA2_SM TXDMA 2 state machine 11-8 RO 4’h0 TXDMA1_SM TXDMA 1 state machine

7 -- -- -- Reserved 6-4 RO 3’h0 RXDMA2_SM RXDMA 2 state machine 3-0 RO 4’h0 RXDMA1_SM RXDMA 1 state machine

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8.1.21.22 Test Mode Register (Offset == 0xCC) Table 69. Test Mode Register.

Bit RW Type


31-27 -- -- -- Reserved

26 R/W 1’h0 SINGLE_PKT Single packet mode. The TXDMA would only move a packet into the TX FIFO at one time.

25 R/W 1’h0 PTIMER_TEST Automatic polling timer test mode 24 R/W 1’h0 ITIMER_TEST Interrupt timer test mode 23 -- -- -- Reserved

22 R/W 1’h0 TEST_SEED_SEL Test seed select. When set, the least significant 14 bits of MAC_LADR (0Ch ~ 0Fh) are used as the seed. When cleared, Test_seed in TS register (C4h ~ C7h) is used as the seed.

21 R/W 1’h0 SEED_SEL Seed select. When set, internal counter is used as the seed. When cleared, external data are used as the seed.

20 R/W 1’h0 TEST_MODE Transmission test mode 19-10 R/W 10’h0 TEST_TIME Transmission back off time test 9-5 R/W 5’h0 TEST_EXCEL Excessive collision test for transmission 4-0 -- -- -- Reserved

8.1.21.23 TX_MCOL and TX_SCOL Counter Register (Offset == 0xD4) Table 70. TX_MCOL and TX_SCOL Counter Register.

Bit RW Type


31-16 RO 16’h0 TX_MCOL Counter for counting packets transmitted OK with 2 ~ 15 collisions

15-0 RO 16’h0 TX_SCOL Counter for counting packets transmitted OK with single collision. 8.1.21.24 RPF and AEP Counter Register (Offset == 0xD8) Table 71. RPF and AEP Counter Register.

Bit RW Type


31-16 RO 16’h0 RPF Receive pause frame counter.

15-0 RO 16’h0 AEP Counter for counting packets with alignment error. The counter is to count packets with CRC error and no-octet-boundary discarded by the MAC controller.

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8.1.21.25 XM and PG Counter Register (Offset == 0xDC) Table 72. XM and PG Counter Register.

Bit RW Type


31-16 RO 16’h0 XM Counter for counting packets failed in transmission (due to late collision or collision count >=16)

15-0 RO 16’h0 PG Counter for counting packets failed in transmission (due to collision count >=16)

8.1.21.26 RUNT_CNT and TLCC Counter Register (Offset == 0xE0) Table 73. RUNT_CNT and TLCC Counter Register.

Bit RW Type


31-16 RO 16’h0 RUNT_CNT Counter for counting received runt packets. 15-0 RO 16’h0 TLCC Late collision counter.

8.1.21.27 CRCER_CNT and FTL_CNT Counter Register (Offset == 0xE4) Table 74. CRCER_CNT and FTL_CNT Counter Register.

Bit RW Type


31-16 RO 16’h0 CRCER_CNT CRC error packet counter. The counter counts the number of octet-boundary frames discarded because of a CRC error.

15-0 RO 16’h0 FTL_CNT Counter for counting received FTL (packet length >1518 bytes) packets.

8.1.21.28 RLC and RCC Counter Register (Offset == 0xE8) Table 75. RLC and RCC Counter Register.

Bit RW Type


31-16 RO 16’h0 RLC Counter for counting loss of received packets (due to RX FIFO full)

15-0 RO 16’h0 RCC Receive collision counter

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8.1.21.29 BROC Counter Register (Offset == 0xEC)

Table 76. BROC Counter Register.

Bit RW Type


31-0 RO BROC Counter for counting received broadcast packets 8.1.21.30 MULCA Counter Register (Offset == 0xF0)

Table 77. MULCA Counter Register.

Bit RW Type


31-0 RO MULCA Counter for counting received multicast packets 8.1.21.31 RP Counter Register (Offset == 0xF4)

Table 78. RP Counter Register.

Bit RW Type


31-0 RO 32’h0 RP Counter for counting packets received successfully 8.1.21.32 XP Counter Register (Offset == 0xF8)

Table 79. XP Counter Register.

Bit RW Type


31-0 RO XP Counter for counting packets transmitted successfully Programming Guide 8.1.22 Frame Transmitting Procedure

The frame transmitting procedure is as follows:

Initialization:

1. Allocate system memory for the transmit descriptor ring and transmit buffer.

2. Initialize the transmit descriptor ring.

3. Set Transmit Ring Base Address Register (offset: 20h) to the base address of the transmit descriptor ring in

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the system memory.

4. Set Interrupt Mask Register (offset: 04h).

5. Set MAC Address Register (offset: 08h).

6. Set Multicast Address Hash Table Register (offset: 10h).

7. Set Interrupt Timer Control Register (offset: 28h) to select the manner of the transmit interrupt.

8. Set Automatic Polling Timer Control Register (offset: 2Ch) to select the manner of transmit poll.

9. Set MAC Control Register (offset: 88h) to set valid configuration for the MAC controller and enable

transmit channel.

Transmit procedures:

1. The software checks if the remainder of the transmit descriptors is enough for the next packet transmission.

If not enough, the software needs to wait until the transmit descriptors are enough.

2. Prepare the transmit packet data to the transmit buffer.

3. Set the transmit descriptor.

4. Write Transmit Poll Demand Register (offset: 18h) to trigger the MAC controller to poll the transmit

descriptor if necessary.

5. Wait for interrupt.

When interrupt occurs, the software checks if it is a transmit interrupt. If ISR [4] = 1, it means the packet has been

transmitted to network successfully. If ISR [5] = 1, it means the packet has been aborted during transmission due to

late collision or excessive collision.

Note:

When setting the transmit descriptor, TXDES0 must be set last. Thus, the setting procedure should be either of the following two:

Procedure A

Set TXDES2

Set TXDES1

Set TXDES0

Procedure B

Set TXDES1

Set TXDES2

Set TXDES0

When preparing a transmit packet which contains more than one transmit descriptors, the first transmit descriptor must be the last set

descriptor of the transmit packet.

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8.1.23 Frame Receiving Procedure

The receiving frame procedure is as follow:

Initialization:

1. Allocate system memory for the receive descriptor ring and receive buffer.

2. Initialize the receive descriptor ring.

3. Set Receive Ring Base Address Register (offset: 24h) to the base address of the receive descriptor ring in

the system memory.

4. Set Interrupt Mask Register (offset: 04h).

5. Set MAC Address Register (offset: 08h).

6. Set Multicast Address Hash Table Register (offset: 10h).

7. Set Interrupt Timer Control Register (offset: 28h) to select the manner of the receive interrupt.

8. Set Automatic Polling Timer Control Register (offset: 2Ch) to select the manner of receive poll.

9. Set MAC Control Register (offset: 88h) to set valid configuration for the MAC controller and enable

receive channel.

10. Write Receive Poll Demand Register (offset: 1Ch) to trigger the MAC controller to poll the receive

descriptor.

Receive procedures:

1. Wait for interrupt.

2. When interrupt occurs, the software checks if it is a receive interrupt. If ISR [0] = 1, it means the packet

has been moved to the receive buffer successfully. Software then needs to fetch the receive descriptor to

get the received packet until the owner bit of the next receive descriptor does not belong to the software.

3. The software needs to release the receive descriptors to the MAC controller after accessing the received

packet.

4. If the receive automatic poll function is disabled, software needs to write Receive Poll Demand Register

(offset: 1Ch) to trigger the MAC controller to poll the receive descriptor.

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9 Static Memory Controller (SMC)

Please refer to ATFSMC020_DS_v1.7.pdf.

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10 SDRAM Controller (SDRAMC)

Please refer to ATFSDMC021_DS_v1.3.pdf.

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11 LCD Controller (LCDC) Description

The FTLCDC100 is a TFT LCD controller compliant with the Advanced Micro-controller Bus Architecture

(AMBA) 2.0 protocol. The module is a reusable soft-IP block, providing all the necessary control signals for

various TFT LCD panels. This module is especially useful for the portable market that includes personal digital

assistants (PDAs), smart-phones, and hand-held and portable color game terminals.

Features

AHB Bus:

● AMBA 2.0 specification compliance

LCD Panel Interface:

● Thin Film Transistor (TFT) color displays with up to 24-bit bus interface

● Resolution programmable up to 1024x768

● Pixel clock rate up to 75 MHz

● Programmable polarity/duration for output enable, vertical sync, horizontal sync, and pixel clock

● Data/Synchronization on/off control

● Swap function for red and blue channels

Input Mode:

● RGB 16 (5:6:5)/24 (8:8:8) bits per pixel

● Palette (8/4/2/1 bits per pixel)

● YCbCr422 (16 bits per pixel)

● YCbCr420 (separate memory location)

Data Format:

● Little-endian, big-endian, and Windows CE

Palette:

● 256-entry 16-bit RGB color palette RAM

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Interrupt Control:

● Master bus error

● Frame status

● FIFO under-run

● Memory base update

On Screen Display:

● RAM based programmable 12x16 font

● Font varieties up to 256

● Maximal window font number is 512

● Flexible dimension for both horizontal and vertical directions

● Programmable window position

● Up-scaling function with factors of 1, 2, 3, and 4

● Transparency of 25%, 50%, 75%, and 100%

● 4-entry, 8-bit color palette for foreground, and 3-entry, 8-bit color palette for background (1 entry reserved for

transparency)

General Purpose Input/Output:

● 4 input ports and 4 output ports for general purpose applications

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Design Block Diagram

AMBADMAC

DMAArbiter

AMBASlave Register files Synchronization

timing generator

Linebuffer

OSD RAM accesscontroller

OSD RAM

Fontgenerator

FIFO

FIFO

FIFOFIFOController

FIFOController

FIFOController

FormatConverter

ColorPalette

PaletteRAM

OSD windowsynchronizer

Font colorpalettizer

Transparencycontroller

LCD interfaceformatter

Color spaceconverter

LCDpanel

Auxiliaryoutput

InterruptGeneration

Interrupt Outputs

GPIOAMBA AHB

Figure 13. FTLCDC100 Design Block Diagram.

Application Block Diagram

The following figure illustrates an example application for FTLCDC100. The LCD controller reads image data

from SDRAM via SDRAM controller for display on the TFT panel. CPU controls the whole system including

programming registers of each controller and updating the frame buffer content of SDRAM. By transforming the

output data stream of the auxiliary port, this system can also provide video signals for TV associated terminals.

FTLCDC100

Slave AHB0

Slave AHB_register

Slave AHB1

Master AHB

TFT Output

Auxiliary Output

Slave AHB_register

AHB1

SDRAM ControllerSDRAM

AHB0

CPU

TFTPANEL

Video DisplayController TV

Figure 14. Example of FTLCDC100 Application Block Diagram.

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Architecture Overview 11.1.1 AHB Slave Interface

The AHB slave interface connects the FTLCDC100 to AMBA AHB bus and allows the AHB master on AMBA

system to access the control registers and palette RAM. The AHB slave interface accepts all AMBA AHB

read/write accesses using WORD size transfer and issues an OK response only.

11.1.2 AHB Master Interface

The AMBA AHB master interface fetches image data from frame buffer and puts them into the FIFO inside the

LCD controller. It can assert fixed-length bursts (INCR4, INCR8) and undefined bursts. It asserts master error

interrupt if an error occurs during the accessing process. When a retry response is received, a retry procedure will

be asserted.

11.1.3 FIFO Controllers and FIFOs

Data fetched from external memory by AHB master interface are placed into FIFO. Only one controller/FIFO will

be required unless the YCbCr420 mode is enabled. The YCbCr420 mode required three channels for Y, Cb and Cr

components, respectively, and each component belongs to a different memory location. The FIFO is 32 bits wide

and the depth is configurable. The input port of the FIFO is connected to the AMBA AHB master output and its

output port is connected to the pixel data unpack controller. If the bus bandwidth capability cannot match the pixel

rate, some unpredictable image distortion would occur. To account for this, the FIFO controller provides an

interrupt signal called “under-run interrupt”. This signal notifies the micro-controller to solve the bus congestion

problem.

11.1.4 Pixel Data Unpack

The data stored in the FIFO are 32-bit and can be packed in 1-, 2-, 4-, 8-, 16- or 24-bit pixel format depending on

the pixel format setting. When YCbCr420 or YCbCr422 mode is enabled, fixed packing format is preset and

cannot be changed. The pixel data can be used to address color palette RAM or to form the raw color value that can

be directly applied to the LCD panel, depending on the operation mode. The following tables show a simple

example to describe the format of packed data. The FTLCDC100 provides 1, 2, 4, 8, 16 and 24 bits per pixel (BPP)

formats that can be big-endian byte and big-endian pixel, little-endian byte and big-endian pixel, or little-endian

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byte and little-endian pixel.

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Table 80. Little Endian Byte, Little Endian Pixel.

FIFO Bit Number BPP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

1BPP pix31

pix30

pix29

pix28

pix27

pix26

pix25

pix24

pix23

pix22

pix21

pix20

pix19

pix18

pix17

Pix16

Bit# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2BPP pixel 15 pixel 14 pixel 13 pixel 12 pixel 11 Pixel 10 pixel 9 pixel 8 Bit# 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4BPP pixel 7 pixel 6 pixel 5 pixel 4 Bit# 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8BPP pixel 3 pixel 2 Bit# 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 16BPP pixel 1 Bit# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24BPP pixel 0 Bit# x x x x x x x x 23 22 21 20 19 18 17 16


1BPP pix0 pix1 pix2 pix3 pix4 pix5 pix6 pix7 pix8 pix9 pix10

pix11

pix12

pix13

pix14

pix15

Bit# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2BPP pixel 0 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 Pixe6 pixel 7 Bit# 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4BPP pixel 0 pixel 1 pixel 2 pixel 3 Bit# 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8BPP pixel 0 pixel 1 Bit# 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 16BPP pixel 0 Bit# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24BPP pixel 0 Bit# x x x x x x x x 23 22 21 20 19 18 17 16

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Table 81. Little Endian Byte, Little Endian Pixel.


1BPP pix16

pix17

pix18

pix19

pix20

pix21

pix22

pix23

pix24

pix25

pix26

pix27

pix28

pix29

pix30

pix31

Bit# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2BPP pixel 8 pixel 9 pixel 10 pixel 11 pixel 12 Pixel 13 pixel 14 pixel 15 Bit# 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4BPP pixel 4 pixel 5 pixel 6 pixel 7 Bit# 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8BPP pixel 2 pixel 3 Bit# 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 16BPP pixel 1 Bit# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24BPP pixel 0 Bit# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


1BPP pix24

pix25

pix26

pix27

pix28

pix29

pix30

pix31

pix16

pix17

pix18

pix19

pix20

pix21

pix22

pix23

Bit# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2BPP pixel 12 pixel 13 pixel 14 pixel 15 pixel 8 pixel 9 pixel 10 pixel 11 Bit# 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4BPP pixel 6 pixel 7 pixel 4 pixel 5 Bit# 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8BPP pixel 3 pixel 2 Bit# 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 16BPP pixel 1 Bit# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24BPP pixel 0 Bit# x x x x x x x x 23 22 21 20 19 18 17 16

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Table 82. Little Endian Byte, Big Endian Pixel.


1BPP pix8 pix9 pix10

pix11

pix12

pix13

pix14

pix15 pix0 pix1 pix2 pix3 pix4 pix5 pix6 pix7

Bit# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2BPP pixel 4 pixel 5 pixel 6 pixel 7 pixel 0 pixel 1 pixel 2 pixel 3 Bit# 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4BPP pixel 2 pixel 3 pixel 0 pixel 1 Bit# 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8BPP pixel 1 pixel 0 Bit# 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 16BPP pixel 0 Bit# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24BPP pixel 0 Bit# 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

11.1.5 Data Mode

11.1.5.1 Raw RGB Mode

Raw data RGB mode supports 16 and 24 BPP. The data stream does not require transformation but reordering for

different panel resolutions is necessary. A simple mapping table is shown below:

Table 83. Mapping for Raw RGB Mode.

16 BPP 24 BPP

B G R B G R 24-bit panel D15-11,000 D10-5,00 D4-0,000 D23-16 D15-8 D7-0 18-bit panel D15-11,0 D10-5 D4-0,0 D23-18 D15-10 D7-2

11.1.5.2 YCbCr422 Mode

The BPP value is 16 and cannot be changed when YCbCr422 mode is enabled. The pixel sequence is given in the

following table.

Table 84. Pixel Sequence for YCbCr422 Mode.

Y Cb Cr Pixle 2N D(2N )15-8 D(2N) 7-0 -----

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Y Cb Cr Pixel 2N+1 D(2N+1)15-8 ---- D(2N)7-0 Pixle 2N+2 D(2N+2 )15-8 D(2N+2) 7-0 ----- Pixel 2N+3 D(2N+3)15-8 ---- D(2N+2)7-0 ………. ………. ……….. ……….

11.1.5.3 YCbCr420 Mode

Under the YCbCr420 operation mode, the BPP value must be 8. In addition, the memory locations for storing the

three (3) components Y, Cb and Cr are separate. An example of the component location/sequence is shown in the

following table. The offset value is relative to the frame buffer base, which is a programmable register. When

YCbCr420 data are read out from each individual FIFO, it is necessary to recover the chrominance values at each

missed line. A line buffer is employed to store previous data and interpolate vertically to estimate the absent

chrominance value. Thereafter, a converted YCbCr422 data stream is outputted to the next stage.

Table 85. Component Location/Sequence for YCbCr420 Mode.

Component Address Offset Sequence Y00, Y01, Y02, Y03, Y04, Y05,………. Y10, Y11, Y12, Y13, Y14, Y15,………. Y20, Y21, Y22, Y23, Y24, Y25,……….

Y 0

………………………………. Cb00, Cb02 Cb04, Cb06, Cb08,…………… Cb20, Cb22 Cb24, Cb26, Cb28,…………… Cb 8000H …………………………………… Cr00, Cr02, Cr04, Cr06, Cr08,…………… Cr20, Cr22, Cr24, Cr26, Cr28,…………… Cr A000H …………………………………

11.1.5.4 RGB Palette Mode

To enhance application flexibility, the controller provides a remapping operation mode. The following figure

depicts the basic concept. This scheme allows for trade-off between color variety and bandwidth or memory space

requirement. There are 4 types available: 1, 2, 4 and 8 BPP, and a palette RAM is utilized to store the look-up table

to regenerate the preferred RGB components. The palette RAM holds up to 256x16-bit color values. It is

physically structured as 128x32-bit. The following table describes the palette RAM entries. The pixel data from the

FIFO are used to address an individual palette location: 1-bit pixel data address the first 2 entries, 2-bit pixel data

address the first 4 entries, 4-bit pixel data address the first 16 entries, and 8-bit pixel data can select any one of the

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256 palette entries. In 16-bit or 24-bit pixel mode, the palette RAM is not used and can be removed to reduce

hardware cost.

8Pixel raw data stream

16Pixel RGB data stream

LUT entry 0

LUT entry 1

LUT entry 255

LUT entry 254

……

…

Figure 15. Palette Remapping Operation.

Table 86. Palette RAM Data Structure (for Entry 0).

Bit Content Description 31-27 B[4:0] Blue palette data for index 1 26-21 G[5:0] Green palette data for index 1 20-16 R[4:0] Red palette data for index 1 15-11 B[4:0] Blue palette data for index 0 10-5 G[5:0] Green palette data for index 0 4-0 R[4:0] Red palette data for index 0

11.1.6 On-Screen Display (OSD) 11.1.6.1 Font Based Architecture

OSD window is composed of fonts. These fonts are generated from the database preloaded into the dedicated RAM.

Each font database entry contains a 12x16 matrix describing the font dot appearance. Since these databases are

stored in RAM, they can be modified easily to meet different requirements, such as for icons and multi-language

applications. The RAM size for storing font database is 4Kx12, so it can provide up to 256 fonts.

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Figure 16. Font Structure (12x16 Dots Per Font).

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11.1.6.2 Attribute Description

Each displayed font in the OSD window owns a unique attribute description. It is a 12-bit-wide entry and can be

programmed based on the user’s preference. The following table shows the font attribute structure. The value I7-0

specifies which font is selected among the 256 to be displayed on the window. The value F1-0 selects the

foreground color from the 4-entry 8-bit color palette. The value B1-0 is used to handle background color in a

manner similar to the foreground color selection. However, when B is equal to zero, it implies that a transparent

operation is enabled. In this case, no more color mapping is necessary; the font background makes the original

image partially visible on the screen, hence only 3 palette color entries are utilized to control the background color.

The transparency level could be 25%, 50%, 75% and 100% for the original image.

Table 87. Font Attribute Structure.

Font Index Foreground Color Background Color I7 I6 I5 I4 I3 I2 I1 I0 F1 F0 B1 B0

11.1.6.3 OSD Window Control

The OSD engine also provides some functions to enhance the application flexibility. The window position of the

screen is fully programmable, for both horizontal and vertical directions. An up-scaling function is implemented to

control the font size. This is achieved by independently duplicating the font dot horizontally and vertically, based

on the values of the control register. The up-scaling factor could be 1, 2, 3 or 4. The window dimensions can also

be programmed to meet user requirements.

OSD MENUBRIGHTNESSCONTRASTPOSITION

LCD screen

OSDposition

OSD X dimension

OSD Ydimension

OSD font

Figure 17. OSD Basic Operation Description.

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11.1.7 TFT Panel Interface

The following figure shows the basic timing of the TFT interface. The relationship between horizontal and vertical

signals is fully programmable. The user can adjust these parameters to meet different panel requirements. The table

below explains the pin ordering difference between 18-bit and 24-bit panels.

Frame timingLC_VS //LC_HS //LC_DE //LC_DATA //

Line timingLC_HS //LC_DE //LC_CLK //LC_DATA //

Figure 18. Basic TFT Interface Timing Diagram.

Table 88. LCD 18-Bit and 24-Bit Interface.

Panel Interface Blue Green Red 24 bit LC_DATA23-16 LC_DATA15-8 LC_DATA7-0 18 bit LC_DATA17-12 LC_DATA11-6 LC_DATA5-0

11.1.8 Interrupt Controller

The interrupt controller receives four internal interrupt signals: AHB master error interrupt, FIFO under-run

interrupt, vertical duration interrupt and frame base address updated interrupt. It then combines those signals to

generate a global interrupt signal. The four interrupt signals can be enabled or disabled via programming the enable

bit of the interrupt enable register. The combined interrupt is asserted if any of the four interrupts is enabled and

brought to occur.

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Programming Model 11.1.9 Summary of FTLCDC100 Control Registers Table 89. Control Register Summary.

Address Type Width Reset Value Name Description 000H R/W 30 00000000H LCDTiming0 LCD horizontal timing control 004H R/W 32 00000000H LCDTiming1 LCD vertical timing control 008H R/W 16 0000H LCDTiming2 LCD clock and signal polarity control 010H R/W 30 00000000H LCDFrameBase LCD panel frame base address 018H R/W 4 0H LCDIntEnable LCD interrupt enable mask 01CH R/W 19 00000H LCDControl LCD panel pixel parameters 020H W 4 -- LCDIntClr LCD interrupt clear 024H R 4 0H LCDInterrupt LCD masked interrupts 034H R/W 16 0000H OSDControl0 OSD scaling and dimension control 038H R/W 20 00000H OSDControl1 OSD position control 03CH R/W 32 00000000H OSDControl2 OSD foreground color control 040H R/W 26 0000000H OSDControl3 OSD background color control 044H R,W 8 --/0H GPIOControl GPI/GPO control

200H~3FCH W 32 -- PaletteWritePort LCD palette RAM write accessing port

8000H~BFFCH W 12 -- OSDFontWritePort OSD font database write accessing port C000H~C7FCH W 12 -- OSDAttributeWritePort OSD window attribute write accessing port

11.1.10 Register Description 11.1.10.1 LCD Horizontal Timing Control (Offset == 0x00) Table 90. LCD Horizontal Timing Control.

Bit Name Type Reset Value Description

31-24 HBP R/W 00H

Horizontal back porch: The number of LC_PCLK periods between the falling edge of LC_PCLK and the start of active data, which is programmed with the value minus 1. The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the LC_HS for the previous line has been de-asserted, the value in HBP is used to count the number of pixel clocks to wait before starting the next display line. HBP can generate a delay of 1 to 256 pixel clock cycles.

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23-16 HFP R/W 00H

Horizontal front porch: The number of LC_PCLK periods between the end of active data and the rising edge of LC_HS, which is programmed with the value minus 1. The 8-bit HFP field sets the number of pixel clock intervals at the end of each line or row of pixels, before the LCD LC_HS is pulsed. Once a complete line of pixels is transmitted to the LCD driver, the value in HFP is used to count the number of pixel clocks to wait before asserting the LC_HS. HFP can generate a period of 1 to 256 pixel clock cycles.

15-8 HW R/W 00H Horizontal synchronization pulse width: The width of the LC_HS signal in the LC_PCLK periods, which is programmed with the value minus 1. The 8-bit HW field specifies the pulse width of LC_HS.

7-2 PL R/W 00H

Pixels-per-line. Actual pixels-per-line = 16*(PL+1). The PL bit field specifies the number of pixels in each line or row of the screen. PL is a 6-bit value that represents 16 to 1024 pixels-per-line. PL is used to count the number of pixel clocks that occur before the HFP is applied. (Program the value required divided by 16, minus 1.)

11.1.10.2 LCD Vertical Timing Control (Offset == 0x04) Table 91. LCD Vertical Timing Control.


31-24 VBP R/W 00H

Vertical back porch: The number of inactive lines at the start of a frame, after the vertical synchronization period. The 8-bit VBP field is used to specify the number of LC_HS inserted at the beginning of each frame. The VBP count starts just after the LC_VS for the previous frame has been negated. After this has occurred, the count value in VBP sets the number of LC_HS periods inserted before the next frame. VBP generates 0 to 255 extra LC_HS cycles.

23-16 VFP R/W 00H

Vertical front porch: The number of inactive lines at the end of a frame, before the LC_VS period. The 8-bit VFP field is used to specify the number of line clocks to be inserted at the end of each frame. Once a complete frame of pixels is transmitted to the LCD display, the value in VFP is used to count the number of LC_HS periods to wait. After the count has elapsed, the LC_VS signal is asserted. VFP generates 0 to 255 line clock cycles.

15-10 VW R/W 00H

LC_VS pulse width: The number of LC_HS, which is programmed to the number of lines required minus 1. The 6-bit VW field is used to specify the pulse width of the LC_VS. This register is programmed with the number of LC_HS in the LC_VS period minus 1.

9-0 LF R/W 000H Lines-per-frame: The number of LC_DE per frame, which is programmed to the number of lines required minus 1. LF is a 10-bit value allowing 1 to 1024 lines. This register is programmed with the number of lines per LCD panel minus 1.

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11.1.10.3 LCD Clock and Signal Polarity Control (Offset == 0x08) Table 92. LCD Clock and Signal Polarity Control


15 ADPEN R/W 0H

Adaptive pixel rate control (available only when DivNo > 0) 0 = Disable 1 = Enable This function will reduce the pixel rate when bandwidth congestion occurs. It may avoid distortion appearing on the LCD screen, but when an unstable frequency operation is applied, some unpredictable situations might happen. So a safe margin must be considered between bandwidth and pixel rate. This is the fundamental solution for such a problem.

14 IDE R/W 0H 0 = LC_DE output pin is active HIGH 1 = LC_DE output pin is active LOW This bit is used to select the active polarity of the output enable signal.

13 ICK R/W 0H

0 = Data are driven on the LCD data lines on the rising edge of LC_PCLK 1 = Data are driven on the LCD data lines on the falling edge of LC_PCLK This bit is used to select the edge of the panel clock on which pixel data are driven out onto the LCD data lines.

12 IHS R/W 0H 0 = LC_CLK pin is active HIGH and inactive LOW 1 = LC_CLK pin is active LOW and inactive HIGH This bit is used to select the active polarity of the horizontal sync signal.

11 IVS R/W 0H 0 = LC_CLK pin is active HIGH and inactive LOW 1 = LC_CLK pin is active LOW and inactive HIGH This bit is used to select the active polarity of the vertical sync signal.

10-6 -- R/W -- Reserved 5-0 DivNo R/W 00H LCD panel clock divisor control. The actual divisor value is equal to (DivNo+1).

11.1.10.4 LCD Panel Frame Base Address (Offset == 0x10) Table 93. LCD Panel Frame Base Address


31-6 LCDFrameBase R/W 0000000H

LCD frame base address. This is the start address of the frame data in memory. The six LSB bits are fixed to 0. When YCbCr420 format is enabled, the value will be used to define the base address of component Y.

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5-2 Frame420Size R/W 00H

Frame buffer size selection for YCbCr420 mode. All values are valid except 0. The user can adjust this register to optimize memory utilization. The total memory address range occupied is described below: Starting address: {LCDFrameBase,0,0,0,0,0,0} Ending address: Starting address + 1.5 * {Frame420Size, 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}

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11.1.10.5 LCD Interrupt Enable Mask (Offset == 0x18) Table 94. LCD Interrupt Enable Mask

11.1.10.6 LCD Panel Pixel Parameters (Offset == 0x1C) Table 95. LCD Panel Pixel Parameters


18 EnYCbCr R/W 0H YCbCr input mode control 0 = Disable 1 = Enable

17 EnYCbCr420 R/W 0H

YCbCr420 input mode control 0 = Disable 1 = Enable This mode only functions when EnYCbCr is set to 1.

16 FIFOThresh R/W 0H

LCD DMA FIFO threshold level 0 = HBUSTREQM is raised when DMA FIFO has four or more empty locations 1 = HBUSTREQM is raised when DMA FIFO has eight or more empty locations

15 PanelType R/W 0H TFT panel color depth selection 0 = 6-bit per channel 1 = 8-bit per channel

13-12 Vcomp R/W 0H

Generate interrupt at: 00 = start of vertical sync 01 = start of vertical back porch 10 = Start of vertical active image 11 = Start of vertical front porch


4 IntBusErrEn R/W 0H AHB master error interrupt enable 1 = Enable 0 = Disable

3 IntVstatusEn R/W 0H Vertical duration comparison interrupt enable 1 = Enable 0 = Disable

2 IntNxtBaseEn R/W 0H Next frame base address updated interrupt enable 1 = Enable 0 = Disable

1 IntFIFOUdnEn R/W 0H FIFO under-run interrupt enable 1 = Enable 0 = Disable

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11 LCDon R/W 0H LCD screen on/off control 0 = Screen disable (all data output pins are forced to 0) 1 = Screen enable (normal operation)

10-9 Endian RW 0H

Frame buffer data endian control 00 = Little endian byte, little endian pixel 01 = Big endian byte, big endian pixel 10 = Little endian byte, big endian pixel (WinCE)

8 BGR R/W 0H RGB of BGR format selection 0 = RGB normal output 1 = BGR red and blue swapped

7-6 -- R/W -- Reserved

5 TFT R/W 0H 0 = Disable TFT panel 1 = Enable TFT panel

3-1 BPP R/W 0H

Frame buffer pixel format 000 = 1 BPP 001 = 2 BPP 010 = 4 BPP 011 = 8 BPP 100 = 16 BPP 101 = 24 BPP

0 LCDen R/W 0H

LCD controller enable control 0 = Disable controller and force all LCD signals including synchronization and data to zero. 1 = Enable controller (normal operation)

11.1.10.7 LCD Interrupt Status Clear (Offset == 0x20) Table 96. LCD Interrupt Status Clear


4 StatusBusErr W -- Setting this bit to 1 will clear AHB master error interrupt status, and setting it to 0 will take no effect.

3 StatusVstatus W -- Setting this bit to 1 will clear the interrupt status of vertical duration comparison, and setting it to 0 will take no effect.

2 StatusNxtBase W -- Setting this bit to 1 will clear the frame buffer base address updated interrupt status, and setting it to 0 will take no effect.

1 StatusFIFOUdn W -- Setting this bit to 1 will clear the FIFO under-run interrupt status, and setting it to 0 will take no effect.

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11.1.10.8 LCD Interrupt Status (Offset == 0x24) Table 97. LCD Interrupt Status


4 IntBusErr R 0H AHB master error status, set when the AMBA AHB master encounters a bus error response from a slave.

3 IntVstatus R 0H Vertical duration comparison, set when one of the four vertical durations, selected via the LCDControl registers, is reached.

2 IntNxtBase R 0H

Frame buffer base address update, set when the current base address registers have been successfully updated by the new address value. This bit can be set only if the host has previously asserted a write access to the frame base address register.

1 IntFIFOUdn R 0H FIFO under-run, set when FIFO being read is not ready. This may arise as a result of bus congestion.

11.1.10.9 OSD Scaling and Dimension Control (Offset == 0x34) Table 98. OSD Scaling and Dimension Control


15-10 OSDHdim R/W 00H Specify the horizontal dimension of the OSD window, that is, the total font number of each row.

9-5 OSDVdim R/W 00H Specify the vertical dimension of the OSD window, that is, the total row number of the window.

4-3 OSDHScal R/W 0H

Define the horizontal up-scaling factor. This will duplicate the dot several times based on the set value below. 00 = Original horizontal size 01 = Enlarge the window 2 times horizontally 10 = Enlarge the window 3 times horizontally 11 = Enlarge the window 4 times horizontally

2-1 OSDVScal R/W 0H

Define the vertical up-scaling factor. This will duplicate the line several times based on the set value below. 00 = Original vertical size 01 = Enlarge the window 2 times vertically 10 = Enlarge the window 3 times vertically 11 = Enlarge the window 4 times vertically

0 OSDen R/W 0H Control the on/off of the OSD window 0 = OSD window off 1 = OSD window on

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11.1.10.10 OSD Position Control (Offset == 0x38) Table 99. OSD Position Control


19-10 OSDHPos R/W 000H

Specify the horizontal position of the OSD window. The reference original position is the left boundary of the LCD screen. The valid value range is from 1 to 1023. However, there is a fixed offset value of 3 between OSDHPos and the actual window position.

9-0 OSDVPos R/W 000H Specify the vertical position of the OSD window. The reference original position is the upper boundary of the LCD screen. The valid value range is from 1 to 1023.

11.1.10.11 OSD Foreground Color Control (Offset == 0x3C) Table 100. OSD Foreground Color Control


31-24 OSDFrPal3 R/W 00H

OSD foreground color palette entry 3. The format is as follows: RGB mode: D31-29 forms the MSB of the blue component and the remaining LSB will be filled with 0. D28-26 forms the MSB of the green component and the remaining LSB will be filled with 0. D25-24 forms the MSB of the red component and the remaining LSB will be filled with 0. YCbCr mode: D31-30 forms the MSB of the Y component and the remaining LSB will be filled with 0. D29-27 forms the MSB of the Cb component and the remaining LSB will be filled with 0. D26-24 forms the MSB of the Cr component and the remaining LSB will be filled with 0.

23-16 OSDFrPal2 R/W 00H OSD foreground color palette entry 2. The operation is similar to that of entry 3. 15-8 OSDFrPal1 R/W 00H OSD foreground color palette entry 1. The operation is similar to that of entry 3. 7-0 OSDFrPal0 R/W 00H OSD foreground color palette entry 0. The operation is similar to that of entry 3.

11.1.10.12 OSD Background Color Control (Offset == 0x40) Table 101. OSD Background Color Control


31-24 OSDBgPal3 R/W 00H

OSD background color palette entry 3. The format is as follows: RGB mode: D31-29 forms the MSB of the blue component and the remaining LSB will be filled with 0. D28-26 forms the MSB of the green component and the remaining LSB will be filled with 0. D25-24 forms the MSB of the red component and the remaining LSB will be filled with 0.

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YCbCr mode: D31-30 forms the MSB of the Y component and the remaining LSB will be filled with 0. D29-27 forms the MSB of the Cb component and the remaining LSB will be filled with 0. D26-24 forms the MSB of the Cr component and the remaining LSB will be filled with 0.

23-16 OSDBgPal2 R/W 00H OSD foreground color palette entry 2. The operation is similar to that of entry 3. 15-8 OSDBgPal1 R/W 00H OSD foreground color palette entry 1. The operation is similar to that of entry 3.

5-4 OSDTrans R/W 0H

OSD background transparency control. 00 = 25 % transparency 01 = 50 % transparency 10 = 75 % transparency 11 = 100 % transparency

11.1.10.13 GPI/GPO Control (Offset == 0x44) Table 102. GPI/GPO Control

Bit Name Type Reset Value Description 7-4 LCDGPO W 0H Directly drive the level of the four general purpose output ports. 3-0 LCDGPI R -- Return the status of the four general purpose input ports.

11.1.10.14 LCD Palette RAM Accessing Port (Offset == 0x200 ~ 0x3FC)

Example for address 0200H (for index values 0 and 1)

Table 103. LCD Palette RAM Accessing Port


31-16 PaletteEty1 W --

Not available for YCbCr mode, since the data in the frame buffer represent raw YCbCr components and cannot be remapped. This 16-bit value is used to remap color when the index value is equal to 1. The format is as below: D31-27 forms the MSB of the blue component and the remaining LSB will be filled with 0. D26-21 forms the MSB of the green component and the remaining LSB will be filled with 0. D20-16 forms the MSB of the red component and the remaining LSB will be filled with 0.

15-0 PaletteEty0 W --

This 16-bit value is used to remap color when the index value is equal to 0. The operation is similar to that of entry 1. D15-11 forms the MSB of the blue component and the remaining LSB will be filled with 0. D10-5 forms the MSB of the green component and the remaining LSB will be filled with 0. D4-0 forms the MSB of the red component and the remaining LSB will be filled with 0.

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11.1.10.15 OSD Font Database Write Accessing Port (Offset == 0x8000 ~ 0xBFFC)

Each font’s database is stored as a 12x16 matrix in font RAM. The RAM is organized as 12-bit in width, hence it

requires 16 entries (192-bit) to record the font content. A bit equaling 1 refers to the foreground and a bit equaling

0 refers to the background. The total size of font memory is 4Kx12, so the total number of fonts that can be loaded

is 256. There is an example for a font “1” at the location 8000H~803CH.

Table 104. OSD Font Database Write Accessing Port

Description Address Offset Bit Type

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 8000H 11-0 W 0 0 0 0 0 0 0 0 0 0 0 0

8004H 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

8008H 11-0 W 0 0 0 0 1 1 1 0 0 0 0 0

800CH 11-0 W 0 0 0 1 1 1 1 0 0 0 0 0

8010H 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

8014H 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

8018H 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

801CH 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

8020H 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

8024H 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

8028H 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

802CH 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

8030H 11-0 W 0 0 0 0 0 1 1 0 0 0 0 0

8034H 11-0 W 0 0 0 1 1 1 1 1 1 0 0 0

8038H 11-0 W 0 0 0 1 1 1 1 1 1 0 0 0

803CH 11-0 W 0 0 0 0 0 0 0 0 0 0 0 0 11.1.10.16 OSD Window Attribute Write Accessing Port (Offset == 0xC000 ~ 0xC7FC)

Fonts are used to build an OSD window. The font dimension can be defined by programming the associated

registers. Each font in the window owns a unique attribute to describe its behavior. The format is a 12-bit-wide

entry as mentioned earlier. These attributes are saved in an attribute RAM, and are sequentially placed from the

up-left corner, left to right, and row by row. The offset address of the first attribute entry is C000H and the last one

is C7FCH. So it is possible to display an OSD window with up to 512 fonts regardless of the window aspect. Since

the total font variety is 256, some fonts will be reused to build larger windows.

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Table 105. OSD Window Attribute Write Accessing Port

Description Address Bit Type

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

C000H 11-0 W Font index of first font foreground palette index of first font

background palette index of first font

| | | | | |

C7FCH 11-0 W Font index of last font foreground palette index of last font

background palette index of last font

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12 USB 2.0 Device Controller General Description

Andes’s FUSB220 is a universal serial bus (USB) device controller in compliance with Universal Serial Bus 2.0

specifications. It can be easily integrated with other intellectual properties such as the DMA controller and the

AHB master in a USB device. The FUSB220 supports high-speed signaling environment of 480 Mb/s, and

full-speed signaling environment of 12 Mb/s. It links to USB cable via USB2.0 Transceiver Macrocell Tester

Interface (T&MT), which is a specification for USB2.0 physical layer transceiver defined by Intel. The application

bus of FUSB220 is an AMBA2.0 AHB bus whose frequency runs up to 133MHz. Each endpoint, except endpoint

0, can be easily programmed for isochronous, bulk, or interrupt transfer. FUSB220 provides a GUI utility

(EZ-CON) for easy configuration and programming of the endpoints.

Features

● Compliant with USB Specification Revision 2.0

● Compliant with AMBA AHB2.0 SPLIT-capable slave

● Compatible with high-speed, full-speed and low-speed devices

● T&MT compliant transceiver

● Automatic generation and check of CRC5 and CRC16

● Maintenance of data toggling on data packets

● Chirp Sequences support

● Suspend Mode, Host Resume and Device Remote Wake-up

● Easy endpoint configuration (EZ-CON)

● Hardware configurable FIFO number (from 1 to 16)

● Hardware configurable Endpoint number (from 1 to 15)

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Block Diagram

PIE

(ParallelInterfaceEngine)

PWE

(PowerManagement)

u_clk

PAM

(ProgrammableMemory)

RGF

(Register File)

CXF

(ControlTransfer)

BFC

(BufferController)

sync

hron

izat

ion HBS

(AHB SPLIT-Capable Slave)

HCLK

AMB

AA

HB

T&M

T

HBF

(AHBBuffer)

FUSB220

Figure 19. FUSB220 Block Diagram.

Architecture Overview

FUSB220 is composed of eight major sub-blocks:

● Parallel Interface Engine (PIE)

● Control Transfer FIFO (CXF)

● Programmable Memory (PAM)

● Register Files (RGF)

● Power Management and Speed Emulation (PWE)

● AMBA AHB SPLIT-capable slave (HBS)

● AHB buffer (HBF)

● AHB buffer controller (BFC)

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12.1.1 Parallel Interface Engine (PIE)

The block diagram for PIE is shown in Figure 20. PIE operates in 16-bit parallel data streams with a universal

transceiver macro interface - UTMI and runs on a 30MHz clock provided by the transceiver. PIE decodes the token

and data packets issued by the USB host. It then generates internal signals based on decoded packets to other

sub-module of FUSB220. The generation of CRC5/CRC16 and the verification of packets transferred from or to

the USB host are also performed by PIE.

After chirp mode, PIE operates in either high-speed or full-speed mode depending on instructions by the PWE.

Information with respect to control transfer is communicated between PIE and CXF. The information on bulk,

isochronous and interrupt transfer is passed on the communication channel between PIE and PAM. The message

passed between PIE and RGF controls the operation of PIE. Information such as the start-of-frame is sent to RGF

by PIE for the AP to process later. Note that only the interconnection among PIE, PAM and CXF is shown in

Figure 20; communication paths among PIE, PWE and RGF are not displayed.

tx_bus[31:24]

Q1

8b FF

Q2

16b FF

EP#

Q3

32b FF

Q2[2:0], Q1[7]

328

16

addr

PID

u_di[7:0]

u_di[15:8]

RX

16u_di

ProtocolEngine

(PE)

setupin

pingsof

out

32 p_do

pw_hs

pw_hs{Q2[7:0],Q1}

Q3[15:0]Q3[31:16]

Q32[31:16]Q32[15:0]

QB32[31:16]QB32[15:0]

crc1616

16

16

CRC 5/16Cell units

CRC CHK/GEN

16

1616

pid(stl/nak/nyet/ack/data2/data1/data0/16'hff/16'h0tx_bus[15:8]Q8crc16[7:0]crc16[15:8]

tx_bus[7:0]tx_bus[23:16]crc16[15:8]crc16[7:0]

Q32

32b FF

QB32

32b FF

Q8

8b FF

TX32 32

32

u_do_l

u_do_h

8

832

PAM

16

u_do

pw_hs

UTMI

CXF

m_do

32

cx_do

32tx_bus[31:0]

8

Q8

Figure 20. PIE Block Diagram.

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12.1.2 Control Transfer FIFO (CXF)

The block diagram for Control Transfer FIFO (CXF) is shown in Figure 21. CXF contains three control-logic

sub-blocks and one memory block. The control signals are shown in dotted lines while the solid lines represent

data and address signals. Through a 32-bit data interface, the CXF sub-module communicates with Protocol

Interface Engine (PIE) on the transmission of control-transfer data from/to the USB host. CXF also communicates

with AMBA interface on sending/receiving control-transfer data to/from microprocessor. The channel between

CXF and RGF is used to pass information concerning the control transfer interrupts and the status control of

control-transfer FIFO.

CXF

PIE

FIFO

status CMD

FIFO

16x32

HBF

BFCfull/empty

CXF

FSM RGF

32

32

32

432

32

4

4

ap_adr

usb_adr

Figure 21. CXF Block Diagram.

12.1.3 Programmable Memory (PAM)

The block diagram for PAM is shown in Figure 22. PAM consists of three major blocks. The first one is an

interface block, which includes the interfaces to PIE and BFC modules. Both interfaces run on a 30MHz clock and

a 32-bit data bus. The second block is a timing generation block. Those modules receive the control signals and

data from both PIE and BFC then route the data to each corresponding FIFO according to the programming. The

built-in memory is a synchronous single-port SRAM macro. The size of the SRAM depends on design

configuration.

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EP_MAP: Endpoint Mapping

PKSIZE: Packet Size

FFINFO: FIFO Information

SELDONE: FIFO Select Done

PAM Timing Gen.

RGF

FIFOADR

FIFO AddressCalculator

PIEINF

PIEInterface

TIMGEN

PAMTiming

Gen

LOCSEL

FIFOLocationSelector

SRAM

N x 512Bytes

Output Data

Addr

Input Data

PIE HBF

BFC

Figure 22. PAM Block Diagram.

12.1.4 Ping-Pong Mechanism of PAM FIFO

The PAM can be configured up to sixteen (16) FIFOs, numbered from 0 to 15. FIFO0 to FIFO13 are 512-byte,

while FIFO14 and FIFO15 are 64-byte each.

A “block” can be composed of one FIFO or two FIFOs depending on the programming. The Ping-Pong FIFO

mechanism is block-based.

For example, if FIFO0 and FIFO1 are programmed for OUT endpoint 1 and the block size is set as 512-byte, the

initial value of the location counter is 0. When the host issues the first OUT transaction to endpoint 1, FIFO0 (0 + 0

= 0) will be accessed, and the location counter will add to 1. The next OUT transaction to endpoint 1 is

automatically redirected to FIFO1 (0 + 1 = 1), and the location counter is incremented by 1. The location counter

value is limited to 0 and 1 since the FIFO block number is programmed as 2. Hence the next value of the location

counter would be 0.

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Single buffer--No ping-pong

Double buffer--Ping-pong

Triple buffer--Ping-pong

Block size : 512-byte

512-byte FIFO0

Block size : 1024-byte

1024-byte FIFO0-1

512-byte FIFO0

FIFO11024-byte FIFO0-1

FIFO2-3

1024-byte FIFO0-1

FIFO2-3

FIFO4-5

512-byte FIFO0

FIFO1

FIFO2

Figure 23. Ping-Pong FIFO Mechanism with Different Block Size and Block Number.

12.1.5 Register Files (RGF)

The block diagram of RGF is shown in Figure 24. RGF contains registers for all the system configuration and the

status control between CPU and the internal blocks. It records the auto-configuration setting of each FIFO, the

status of each IN/OUT endpoint, interrupt status, test setting, and so on. RGF also communicates with PIE

regarding information on the USB transfers. The interconnection between RGF and PAM provides PAM with

configuration for non-control transfer endpoints. PAM passes on information for each transfer from non-control

endpoints to RGF and vice versa to allow AP to read this information for further processing. The information for

control transfer is transmitted between CXF and RGF. RGF talks with PWE for detection purposes and for the

support of speed emulation, power-down, USB reset and timeout. Finally, RGF adopts AMBA protocol to let AP

access the information recorded in the registers of FUSB220.

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controlregisters

interruptregisters

PWE

CXF

endpointconfiguration andstatus registers

test registers

PAM

PIE

RGF

HBS

Figure 24. RGF Block Diagram.

12.1.6 Power Management and Speed Emulation (PWE)

The block diagram for PWE is shown in Figure 25. PWE controls the switching between FUSB220

speed-operating modes: High/Full speed. For power management, PWE monitors u_linesta to detect any idle state

occurred during transactions on USB. If there is no traffic for more than 3ms, PWE would assert power-save signal

to inform the AP of the idle event. With AP’s consent, PWE would assert the suspend signal to instruct the

transceiver to enter suspend mode. PWE also monitors u_linesta to detect USB resets and resumes.

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u_opmode

u_xcvsel

u_termsel

u_susp_n

pw_resume

pw_hs

pw_normal(operation

pw_timeout

r_go_susp

r_cap_rmwkupu_linesta

pw_save

CXF

PAM

RGF

PIE

RX p_timeout

UTMI

pw_usbrstPWE

Line - State

Check

T1(timer)T0(timer)

wakeup2

2

Figure 25. PWE Block Diagram.

12.1.7 AHB SPLIT-Capable Slave (HBS)

The HBS of FUSB220 is an AMBA 2.0 compliant slave that supports multiple split transfers. It is the interface

between the AHB buffer (HBF)/RGF and the external AHB masters. Before a USB packet is completely

transferred to its destination, any AHB masters attempting to access another endpoint’s FIFO would be split. The

number of split AHB masters would be recorded. After a USB packet is transferred, HBS recalls all split masters to

re-attempt the transfer by asserting proper bit of HSPLIT[15:0] to arbiter and so on. 12.1.8 AHB Buffer (HBF)

Data written to or read from CXF and PAM are stored in HBF first. In the case of AP write, the data in HBF are

sent to the FIFOs of CXF or PAM only if the HBF is full or if HBF contains the last data payload of a USB packet.

In the case of AP read, the HBS does not accept any cycle by SPLIT response until the HBF is full or if HBF

contains the last data payload of a USB packet.

In the case of AP write, the FIFO done bit (0BH bit0 for CXF, A0H~AFH bit3 for PAM) should be set properly

after sending a packet in the following cases:

1. A short packet is sent.

2. The packet length is not a multiple of the HBF size. The done bit is used to flush the HBF data and finish a packet.

3. AP intends to read FIFO after sending the packet.

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4. The next packet is sent by another AHB master.

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After setting the FIFO done bit, firmware should make sure that HBF is emptied by 28H bit0 before sending the

next packet to the FUSB220.

Data written to or read from RGF are not buffered; they are transferred directly between HBS and RGF.

12.1.9 AHB Buffer Controller (BFC)

BFC assumes the responsibility of managing data flow between HBF and PAM/CXF. In AP write, BFC moves the

HBF data to the target FIFO if HBF is full or when the FIFO done bit is set. In AP read, BFC moves the data from

FIFO to HBF if HBF is empty.

USB Reset and Power Saving Mode 12.1.10 USB Reset

*1u_vbus (AP)

D+

D-u_usbrst *3

(FUSB220) *2

pw_hs(FUSB220)

SOF

*1. After a time-span of 50ms until the “UNPLUG” bit in “phy_tms” register with offset 08 is cleared,

*2. After host drives D+/D- as SE0 state for at least 2.5μs, PIE will see it as "USB reset", then issues

*3. The high-speed handshake sequence: FUSB220 issues K state to host first, then host issues the

one clk cycle

2.5￡gs min

the FUSB220 will turn on the Rpu (1.5K), and puts it in Full-Speed mode.

one pulse signal, “u_usbrst" for 30MHz to back-end block.

KJKJKJ sequence to indicate that it is HS host.

Figure 26. USB Reset and High-Speed Detection Handshake Timing Chart.

When a device (AP) plugs into the host/hub, it must detect the Vbus information from USB cable and asserts the

“u_vbus” to FUSB220 to show that the device has been attached to the downstream port of the hub; including the

root hub on the host. It is important that the device carries out this action when it operates in self-power mode.

On the other hand, if the device operates in bus-power mode, the u_vbus can be tied to “high” directly. This is for

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back-drive voltage consideration in USB2.0 compliance test. After a time-span of 50ms, until the “UNPLUG” bit

in “phy_tms” register with offset 08H is cleared, the FUSB220 would turn on the Rpu (1.5K), and puts it in

Full-Speed mode; so the J state would be asserted on the USB. The FUSB220 also spends at least 15ms to cover

the debounce interval. Thereafter, anytime the device observes no bus activity, it must obey the rules of going into

suspend mode. If the SE0 state on USB has been detected for at least 2.5µs at this moment, the FUSB220 would

assert one pulse signal, “u_usbrst”, to back-end blocks. For a while, the FUSB220 would assert Chirp K on the

USB. The host would detect this event and respond to the device with the KJKJKJ sequence. However, the

FUSB220 does not assert the indication “pw_hs” for operating in HS mode, until the first SOF packet is asserted

on USB.

12.1.11 Power Saving Mode

hwrst_n

u_vbus

D+/D-

u_susp_n

clk_gating

0 min.

*1

50 min.

*3

*2

*4

t10

*1. This interval depends on customer's design.

*2. The AP guarantees a minimum of 3ms for the recovery time of back-voltage.

*3/*4. The integrator can use some glue logic to combine both u_susp_n and clock-masked

control provided by AP to turn on or turn off the clock from PHY, such as "clk_gating" timing.

t9 t8 t7 t6 t5 t4 t3 t2 t1 t0

Figure 27. FUSB220 Asserts u_susp_n to Turn Off the PLL in PHY.

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FUSB220 provides the u_susp_n signal to turn on/off clock (u_clk) from PHY. However, in some cases, users may

want to turn the clock on/off by their own AP instead of using FUSB220. That means the integrator can use some

glue logic (e.g. an AND gate) to combine both u_susp_n and clock-masked control provided by AP to turn on/off

the clock from PHY. Please refer to the integration guide of FUSB220 for the details.

Figure 27 shows the timing relationship for u_susp_n between u_vbus and D+/D-. Here is an explanation of what

happens at each tn:

t0 System (power on/hardware) resets, while the device is not plugged into upstream facing port. FUSB220

drives u_susp_n to high state since now.

t1 The device is plugged into upstream facing port, such as the root hub.

t2 FUSB220 is initially attached as a full-speed device, and the J state is asserted on USB by Rpu(1.5K).

t3 Host drives reset on USB.

t4 FUSB220 operates in high-speed mode. Communication occurs on USB between host and FUSB220.

t5 There is no traffic since now.

t6 FUSB220 detects no traffic on USB for more than 3ms and asserts u_susp_n to low state to turn off PLL in

PHY.

t7 Host resumes FUSB220, then u_susp_n is de-asserted.

t8 The device is unplugged from upstream facing port.

t9 u_vbus is de-asserted because of the detachment.

t10 The u_susp_n still remains in High state. However, for power consumption in self-power operation with

battery, the integrator can create another signal, clk_gating, to turn off the clock from PHY.

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u_clk

pw_save

(FUSB220)

*3

go_suspend

(AP/FUSB220)

u_susp_n

(FUSB220)

*1

D+

D- *4

resume *6

(FUSB220) *1

D+

D- *5

u_usbrst(FUSB220)

2.5￡gsmin.

PHY turns off u_clk

*2

tsusp_delay

*1. The idle state in HS mode is SE0, and J state in FS mode. If FUSB220 detects idle than 3ms, FUSB220 will assert the "pw_save" to urge AP to enter "SUSPEND" mode.*2. The vaule of tsusp_delay can be set by AP. Please refer to the idle_cnt register for details.*3. "go_suspend" is the internal signal of FUSB220, which is not visible to AP. However, AP can set it by writing 1 to GOSUSP of main control register. Then FUSB220 will clear it if it detects the RESUME / USB RESET signals.*4. At the end of resume asserted by host, the FUSB220 will assert "resume".*5. If host issues reset in the suspend mode, the FUSB220 will assert "u_usbrst" when it sees the SE0 state for at least 2.5μs on USB.*6. When F/W sees the resume interrupt in offset 28H, it must clear it, then the resume will be de-asserted.

host resume / 20ms

host reset

one clk cycle width

unstable interval gated by PHY

Figure 28. FUSB220 Wakened Up by Host Resume / Reset.

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FUSB220 provides a Suspend Mode for power saving. The sequence for entering Suspend Mode is as follows:

1. If there is no transition on D+/D- for more than 3 ms, then FUSB220 asserts suspend interrupt to inform

firmware that it wishes to enter Suspend Mode.

2. Once firmware detects the suspend interrupt, it decides whether to accept the suspend request from

FUSB220. If firmware accepts the suspend request, it would finish the necessary operations. Such as,

reading some register of FUSB220 before setting the “GOSUSP” bit in the “main_ctr” register with offset

“00” of FUSB220. Those operations are necessary, since the clock of FUSB220 is turned off after

“GOSUSP” is set.

3. Firmware sets the “GOSUSP” bit in the register file of FUSB220.

4. Once “GOSUSP” is set, FUSB220 enters Suspend Mode and asserts the suspend output, u_susp_n to the

transceiver. The clock input, u_clk, is then turned off by transceiver.

5. Finally, if FUSB220 detects resume or USB reset signals, it would clear the “GOSUSP” bit.

There are three events that could force FUSB220 wake up from Suspend Mode:

• Host resumes; which occurs when D+/D- toggles, see Figure 44

• Host resets; which occurs when FUSB220 detects SE0 state on USB, see Figure 44

• Remote wake-up; which occurs when AP asserts an wake-up input, see Figure 45

For remote wake-up, AP should keep wake-up asserted until FUSB220 de-asserts pw_save. In other words, AP

cannot de-assert wake-up before FUSB220 de-asserts pw_save.

The procedure for the wake-up process is:

1. Host sets the Device_Remote_Wakeup feature to FUSB220.

2. Under Suspend Mode, either host resuming or the remote wake-up signal from AP would trigger the

wake-up process and FUSB220 would be awakened first.

3. Once FUSB220 is awake, it will de-assert suspend output to PHY, and PHY would turn on the 30 MHz

clock output after FUSB220 de-asserts the suspend output.

4. Typically, a clock output of PHY would be unstable for a short time after the suspended transceiver is

awake. This unstable interval is about 2 ms for the Andes USB2.0 transceiver (FZUSB200).

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u_clk

pw_save(FUSB220)

go_suspend

u_susp_n(FUSB220)

wakeup*1 *2

D+

D-

D+

D-

PHY turns off u_clk

tsusp_delay

unstable interval gated by PHY

10ms

*1. FUSB220 detects 3ms idle on USB in HS mode, then reverses to FS mode!*2. FUSB220 drives device-initialed resume-K state for about 10ms, then host detects the K state, and drives host-resumeK to downstream port!

FUSB220 operates in HS mode before enteingr SUSPEND mode

FUSB220 operates in FS mode

at least 20ms

0 min.

Figure 29. FUSB220 Wakened Up by AP.

Programming Model 12.1.12 Summary of the FUSB220 Registers Table 106. Summary of the FUSB220 Registers.

Name Address (Offset)

Size (Byte) Access Description

main_ctl 00 1 R/W Main Control Register, which performs device management for USB. dev_adr 01 1 R/W Device Address Register, which records the latest device address. tst_ep 02 1 R/W Test Register: Endpoints’ testing control signals for debugging. - 03 - - Reserved. frm_numb0 04 1 R/W Frame Number Register Byte 0: Frame number register records the SOF

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related frame number for high speed and full speed.

frm_numb1 05 1 R/W Frame Number Register Byte 1: Frame number register records the SOF related frame number for high speed and full speed.

sof_tmskb0 06 1 R/W SOF Mask Timer Register Byte 0. sof_tmskb1 07 1 R/W SOF Mask Timer Register Byte 1. phy_tms 08 1 R/W PHY Test Mode Selector Register: Test mode selector register for PHY.

vnd_ctl 09 1 R/W Vendor Defined IO Control Register: Vendor defined control signals for PHY.

vnd_sta 0A 1 R Vendor Defined IO Status Register, which reports the status of vendor defined control.

cx_csr 0B 1 R/W CX Configure and Status Register. ep0_dp 0C - R/W Endpoint 0 Data Port: For Endpoint 0 data access. - 0E-0F - - Reserved.

int_mgrp 10 1 R/W Interrupt Group Mask Register: Interrupt mask register for masking interrupt source group.

int_mskb0 11 1 R/W Interrupt Mask Register Byte 0: Interrupt mask register for masking interrupt source byte 0 register.








rx0byte_epb0 19 1 R/W Receive Zero-length Data Packet Register Byte 0: Indicates which endpoint among Endpoint 7 to Endpoint 1 receives a zero-length data packet.

rx0byte_epb1 1A 1 R/W Receive Zero-length Data Packet Register Byte 1: Indicates which endpoint among Endpoint15 to Endpoint 8 receives a zero-length data packet.

- 1B - - Reserved.

fempt_b0 1C 1 FIFO empty Byte 0: Indicates FIFO 0 ~ FIFO 7 are fully empty

fempt_b1 1D 1 FIFO empty Byte 1: Indicates FIFO 8 ~ FIFO 15 are fully empty

1E ~ 1F - - Reserved.

int_grp 20 1 R Interrupt Group Register: Interrupt source group register that indicates the interrupt for a certain group of interrupts.

int_srcb0 21 1 R Interrupt Source Register Byte 0: Interrupt group register for recording the

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interrupt sources of the endpoint 0 interrupts.

int_srcb1 22 1 R Interrupt Source Register Byte 1: Interrupt group register for recording the interrupt sources of the FIFO0 ~ FIFO3 OUT interrupts.




int_srcb5 26 1 R Interrupt Source Register Byte 5: Interrupt group register for recording the interrupt sources of the FIFO0 ~ FIFO7 IN interrupts.

int_srcb6 27 1 R Interrupt Source Register Byte 6: Interrupt group register for recording the interrupt sources of the FIFO8 ~ FIFO15 IN interrupts.

int_srcb7 28 1 R Interrupt Source Register Byte 7

iso_seq_errb0 29 1 R/W Isochronous Sequential Error Register Byte 0: Indicates which endpoint among Endpoint 7 to Endpoint 1 receives an isochronous sequential error.

iso_seq_errb1 2A 1 R/W Isochronous Sequential Error Register Byte 1: Indicates which endpoint among Endpoint 15 to Endpoint 8 receives an isochronous sequential error.

iso_seq_abtb0 2B 1 R/W Isochronous Sequential Abort Register Byte 0: Indicates which endpoint among Endpoint 7 to Endpoint 1 receives an isochronous sequential abort.

iso_seq_abtb1 2C 1 R/W Isochronous Sequential Abort Register Byte 1: Indicates which endpoint among Endpoint 15 to Endpoint 8 receives an isochronous sequential abort.

tx0byteb0 2D 1 R/W Transferred Zero-length Register Byte 0: Indicates which endpoint among Endpoint 7 to Endpoint 1 returns a zero-length data packet to USB HOST.

tx0byteb1 2E 1 R/W Transferred Zero-length Register Byte 1: Indicates which endpoint among Endpoint 15 to Endpoint 8 returns a zero-length data packet to USB host.

idle_cnt 2F 1 R/W Idle counter. When the “GOSUSP” bit of main control register is set by AP, FUSB220 will wait for a period defined in this counter, and then turn off the u_clk (drive u_susp_n to low state).

ep1_map 30 1 R/W Endpoint 1 FIFO Mapping Register. ep2_map 31 1 R/W Endpoint 2 FIFO Mapping Register. ep3_map 32 1 R/W Endpoint 3 FIFO Mapping Register. ep4_map 33 1 R/W Endpoint 4 FIFO Mapping Register. ep5_map 34 1 R/W Endpoint 5 FIFO Mapping Register. ep6_map 35 1 R/W Endpoint 6 FIFO Mapping Register. ep7_map 36 1 R/W Endpoint 7 FIFO Mapping Register. ep8_map 37 1 R/W Endpoint 8 FIFO Mapping Register. ep9_map 38 1 R/W Endpoint 9 FIFO Mapping Register. ep10_map 39 1 R/W Endpoint 10 FIFO Mapping Register. ep11_map 3A 1 R/W Endpoint 11 FIFO Mapping Register. ep12_map 3B 1 R/W Endpoint 12 FIFO Mapping Register. ep13_map 3C 1 R/W Endpoint 13 FIFO Mapping Register.

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ep14_map 3D 1 R/W Endpoint 14 FIFO Mapping Register. ep15_map 3E 1 R/W Endpoint 15 FIFO Mapping Register. hbf_cnt 3F 1 R HBF data byte count. iep1_xpsz 40 2 R/W IN Endpoint 1 MaxPacketSize Register. iep2_xpsz 42 2 R/W IN Endpoint 2 MaxPacketSize Register. iep3_xpsz 44 2 R/W IN Endpoint 3 MaxPacketSize Register. iep4_xpsz 46 2 R/W IN Endpoint 4 MaxPacketSize Register. iep5_xpsz 48 2 R/W IN Endpoint 5 MaxPacketSize Register. iep6_xpsz 4A 2 R/W IN Endpoint 6 MaxPacketSize Register. iep7_xpsz 4C 2 R/W IN Endpoint 7 MaxPacketSize Register. iep8_xpsz 4E 2 R/W IN Endpoint 8 MaxPacketSize Register. iep9_xpsz 50 2 R/W IN Endpoint 9 MaxPacketSize Register. iep10_xpsz 52 2 R/W IN Endpoint 10 MaxPacketSize Register. iep11_xpsz 54 2 R/W IN Endpoint 11 MaxPacketSize Register. iep12_xpsz 56 2 R/W IN Endpoint 12 MaxPacketSize Register. iep13_xpsz 58 2 R/W IN Endpoint 13 MaxPacketSize Register. iep14_xpsz 5A 2 R/W IN Endpoint 14 MaxPacketSize Register. iep15_xpsz 5C 2 R/W IN Endpoint 15 MaxPacketSize Register. - 5D-5F - - Reserved. oep1_xpsz 60 2 R/W OUT Endpoint 1 MaxPacketSize Register. oep2_xpsz 62 2 R/W OUT Endpoint 2 MaxPacketSize Register. oep3_xpsz 64 2 R/W OUT Endpoint 3 MaxPacketSize Register. oep4_xpsz 66 2 R/W OUT Endpoint 4 MaxPacketSize Register. oep5_xpsz 68 2 R/W OUT Endpoint 5 MaxPacketSize Register. oep6_xpsz 6A 2 R/W OUT Endpoint 6 MaxPacketSize Register. oep7_xpsz 6C 2 R/W OUT Endpoint 7 MaxPacketSize Register. oep8_xpsz 6E 2 R/W OUT Endpoint 8 MaxPacketSize Register. oep9_xpsz 70 2 R/W OUT Endpoint 9 MaxPacketSize Register. oep10_xpsz 72 2 R/W OUT Endpoint 10 MaxPacketSize Register. oep11_xpsz 74 2 R/W OUT Endpoint 11 MaxPacketSize Register. oep12_xpsz 76 2 R/W OUT Endpoint 12 MaxPacketSize Register. oep13_xpsz 78 2 R/W OUT Endpoint 13 MaxPacketSize Register. oep14_xpsz 7A 2 R/W OUT Endpoint 14 MaxPacketSize Register. oep15_xpsz 7C 2 R/W OUT Endpoint 15 MaxPacketSize Register. fifo_dma_en 7E 2 R/W DMA Mode Enable Register. fifo0_map 80 1 R/W FIFO 0 Mapping Register. fifo1_map 81 1 R/W FIFO 1 Mapping Register. fifo2_map 82 1 R/W FIFO 2 Mapping Register. fifo3_map 83 1 R/W FIFO 3 Mapping Register. fifo4_map 84 1 R/W FIFO 4 Mapping Register.

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fifo5_map 85 1 R/W FIFO 5 Mapping Register. fifo6_map 86 1 R/W FIFO 6 Mapping Register. fifo7_map 87 1 R/W FIFO 7 Mapping Register. fifo8_map 88 1 R/W FIFO 8 Mapping Register. fifo9_map 89 1 R/W FIFO 9 Mapping Register. fifo10_map 8A 1 R/W FIFO 10 Mapping Register. fifo11_map 8B 1 R/W FIFO 11 Mapping Register. fifo12_map 8C 1 R/W FIFO 12 Mapping Register. fifo13_map 8D 1 R/W FIFO 13 Mapping Register. fifo14_map 8E 1 R/W FIFO 14 Mapping Register. fifo15_map 8F 1 R/W FIFO 15 Mapping Register. fifo0_config 90 1 R/W FIFO 0 Configuration Register. fifo1_config 91 1 R/W FIFO 1 Configuration Register. fifo2_config 92 1 R/W FIFO 2 Configuration Register. fifo3_config 93 1 R/W FIFO 3 Configuration Register. fifo4_config 94 1 R/W FIFO 4 Configuration Register. fifo5_config 95 1 R/W FIFO 5 Configuration Register. fifo6_config 96 1 R/W FIFO 6 Configuration Register. fifo7_config 97 1 R/W FIFO 7 Configuration Register. fifo8_config 98 1 R/W FIFO 8 Configuration Register. fifo9_config 99 1 R/W FIFO 9 Configuration Register. fifo10_config 9A 1 R/W FIFO 10 Configuration Register. fifo11_config 9B 1 R/W FIFO 11 Configuration Register. fifo12_config 9C 1 R/W FIFO 12 Configuration Register. fifo13_config 9D 1 R/W FIFO 13 Configuration Register. fifo14_config 9E 1 R/W FIFO 14 Configuration Register. fifo15_config 9F 1 R/W FIFO 15 Configuration Register. fifo0_inst A0 1 R/W FIFO 0 Instruction Register. fifo1_inst A1 1 R/W FIFO 1 Instruction Register. fifo2_inst A2 1 R/W FIFO 2 Instruction Register. fifo3_inst A3 1 R/W FIFO 3 Instruction Register. fifo4_inst A4 1 R/W FIFO 4 Instruction Register. fifo5_inst A5 1 R/W FIFO 5 Instruction Register. fifo6_inst A6 1 R/W FIFO 6 Instruction Register. fifo7_inst A7 1 R/W FIFO 7 Instruction Register. fifo8_inst A8 1 R/W FIFO 8 Instruction Register. fifo9_inst A9 1 R/W FIFO 9 Instruction Register. fifo10_inst AA 1 R/W FIFO 10 Instruction Register. fifo11_inst AB 1 R/W FIFO 11 Instruction Register.

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fifo12_inst AC 1 R/W FIFO 12 Instruction Register. fifo13_inst AD 1 R/W FIFO 13 Instruction Register. fifo14_inst AE 1 R/W FIFO 14 Instruction Register. fifo15_inst AF 1 R/W FIFO 15 Instruction Register. fifo0_bc B0 1 R FIFO 0 Byte-Count Register. fifo1_bc B1 1 R FIFO 1 Byte-Count Register. fifo2_bc B2 1 R FIFO 2 Byte-Count Register. fifo3_bc B3 1 R FIFO 3 Byte-Count Register. fifo4_bc B4 1 R FIFO 4 Byte-Count Register. fifo5_bc B5 1 R FIFO 5 Byte-Count Register. fifo6_bc B6 1 R FIFO 6 Byte-Count Register. fifo7_bc B7 1 R FIFO 7 Byte-Count Register. fifo8_bc B8 1 R FIFO 8 Byte-Count Register. fifo9_bc B9 1 R FIFO 9 Byte-Count Register. fifo10_bc BA 1 R FIFO 10 Byte-Count Register. fifo11_bc BB 1 R FIFO 11 Byte-Count Register. fifo12_bc BC 1 R FIFO 12 Byte-Count Register. fifo13_bc BD 1 R FIFO 13 Byte-Count Register. fifo14_bc BE 1 R FIFO 14 Byte-Count Register. fifo15_bc BF 1 R FIFO 15 Byte-Count Register. fifo0_dp C0 - R/W FIFO 0 Data Port. fifo1_dp C4 - R/W FIFO 1 Data Port. fifo2_dp C8 - R/W FIFO 2 Data Port. fifo3_dp CC - R/W FIFO 3 Data Port. fifo4_dp D0 - R/W FIFO 4 Data Port. fifo5_dp D4 - R/W FIFO 5 Data Port. fifo6_dp D8 - R/W FIFO 6 Data Port. fifo7_dp DC - R/W FIFO 7 Data Port. fifo8_dp E0 - R/W FIFO 8 Data Port. fifo9_dp E4 - R/W FIFO 9 Data Port. fifo10_dp E8 - R/W FIFO 10 Data Port. fifo11_dp EC - R/W FIFO 11 Data Port. fifo12_dp F0 - R/W FIFO 12 Data Port. fifo13_dp F4 - R/W FIFO 13 Data Port. fifo14_dp F8 - R/W FIFO 14 Data Port. fifo15_dp FC - R/W FIFO 15 Data Port.

12.1.13 Register Description

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There are three reset conditions in FUSB220:

1. Reset; Power on or hardware reset. Each register is reset to its default value after a power on reset.

2. Bus reset; USB bus reset. Not all registers is reset by a bus reset. Please consult each register table for

detailed information.

3. Soft reset; By setting bit 4 of the Main Control Register, software can reset SOF Frame Number Register

(04H and 05H) and SOF Mask Timer Register (06H and 07H).

Ony effective reset conditions are listed in the following register tables.

12.1.13.1 Main Control Register (Offset == 0x00)

The main control register sets the general controls for the whole device, including the wake-up behaviors, global

interrupt activity, and software reset settings. The bit allocation is given in the following table.

Table 107. Main Control Register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Symbol AHB_RST HS_EN CHIP_EN SFRST GOSUSP GLINT_EN FLUSH_HBF

CAP_RMWKUP

Reset 0 0 0 0 0 0 0 0 Bus Reset - - - - 0 - - - Access - R R/W R/W R/W R/W R/W R/W

Bit Symbol Description

7 AHB_RST AHB Software Reset: Write a ‘1’ to reset HBS, HBF and BFC. This bit is automatically cleared by hardware.

6 HS_EN High Speed Enable: 1: Device is in high speed mode 0: Device is in full speed mode

5 CHIP_EN Chip Enable: Write a ‘1’ to enable the write cycle of PAM FIFO.

4 SFRST

Software Reset: Write a ‘1’ to set a software-initiated reset to FUSB220. This bit cannot be set when FUSB220 is in the suspend mode, because the u_clk is stopped. Setting of this bit will cause the de-assertion of pw_save output if it is asserted. The chirp sequence will be terminated while this bit is set. The command FIFO will be cleared by setting of this bit too. The Frame Number Register and SOF Timer Mask Register will be cleared too. In addition, the micro-frame number in the RGF will be cleared. Note that the data FIFO status will not be cleared.

3 GOSUSP Go Suspend: Writing a ‘1’ will activate the suspend mode.

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2 GLINT_EN Global Interrupt Enable: A ‘1’ enables all interrupts. Individual interrupts can be masked by setting the corresponding bits in interrupt mask register (index 11H ~ 17H).

1 FLUSH_HBF Flush HBF: Write a ‘1’ to flush HBF data to FIFO. This bit is automatically cleared by hardware.

0 CAP_RMWKUP Capability of Remote Wake-up: A ‘1’ indicates that FUSB220 has the capability of being wakened up by ‘wake-up’ signal.

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12.1.13.2 Device Address Register (Offset == 0x01)

The device address register stores the assigned address of a USB device, and enables the USB device after

executing the set-configuration command.

Table 108. Device Address Register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol AFT_CONF DEVADDR [6:0] Reset 0 00H Bus Reset 0 - Access R/W R/W


7 AFT_CONF After Set-Configuration: A ‘1’ indicates that the device has successfully executed SET_CONFIGURATION command.

6-0 DEVADR [6:0] Device Address: Records the latest USB device address for each SET_ADDRESS. 12.1.13.3 Test Register (Offset == 0x02)

The CXF loop back test procedure is as follows:

Clear "TST_CLREA" and set "TST_LPCX" at the same time.

Write data to control FIFO.

Set CX_DONE (0x0B Bit 0).

Check if CX_DONE is set.

Set "TST_CLREA" and clear "TST_LPCX" at the same time.

Read data from control FIFO.

Compare data.

Table 109. Test Register.


Symbol TST_HALF_SPEED TST_MOD TST_DIST

OG TST_DISC

RC TST_DISG

ENSOF TST_CLRE

A TST__LPC

X TST_CLRF

F Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W

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7 TST_HALF_SPEED Set Half-Speed: A ‘1’ turns half-speed on. When this bit is set to 1, FUSB220 allows AP to access FIFO only during even cycle of u_clk.

6 TST_MOD

Test Mode: A ‘1’ turns test_mode on. When this bit is set to 1, FUSB220 will enter test mode. In normal mode, FUSB220 uses a counter for 10ms detection of USB reset. The count is a large number. In test mode, FUSB220 will use a smaller count for USB reset detection to save the test cycle on test machine.

5 TST_DISTOG Disable Toggle Sequence: A ‘1’ disables the toggle sequence.

4 TST_DISCRC Disable CRC: When setting this bit as ‘1’, FUSB220 will not append CRC for upstream packets.

3 TST_DISGENSOF Disable Self Generation of SOF: This bit uses the SOF sent from the host instead of the SOF generated by the FUSB220 itself.

2 TST_CLREA Clear External Side Address: Write a ‘1’ then ‘0’ to clear external side address for loop back test.

1 TST_LPCX Loop Back Test for CX: A ‘1’ indicates loop-back test for control transfer (endpoint 0). 0 TST_CLRFF Clear FIFO: Writing a ‘1’ will clear all FIFO counters and location counters of PAM.

12.1.13.4 SOF Frame Number Register Byte 0 (Offset == 0x04)

The frame number records the last successfully received Start of Frame (SOF) number. The register contains two

bytes and the bit allocation is given in the following table.

Table 110. SOF Frame Number Register Byte 0.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol SOFN [7:0] Reset 0 Soft Reset 0 Access R

Bit Symbol Description 7-0 SOFN [7:0] SOF Frame Number Bits [7:0]: Record the frame number for high speed and full speed.

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12.1.13.5 SOF Frame Number Register Byte 1 (Offset == 0x05) Table 111. SOF Frame Number Register Byte 1.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol Reserved Reserved USOFN [2:0] SOFN [10:8] Reset - - 0 0 Soft Reset - - 0 0 Access - - R R

Bit Symbol Description 7-6 Reserved Reserved bit. 5-3 USOFN [2:0] SOF Microframe Number Bits [2:0]: Record the microframe number during high speed. 2-0 SOFN [10:8] SOF Frame Number Bits [10:8]: Record the frame number for high speed and full speed.

12.1.13.6 SOF Mask Timer Register Byte 0 (Offset == 0x06)

This two-byte register is used to mask the last SOF.

Table 112. SOF Mask Timer Register Byte 0.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol SOFTM [7:0] Reset 0 Soft Reset 0 Access R/W

Bit Symbol Description 7-0 SOFTM [7:0] SOF Mask Timer: Time elapsed since last SOF in 30 MHz clock bit.

12.1.13.7 SOF Mask Timer Register Byte 1 (Offset == 0x07) Table 113. SOF Mask Timer Register Byte 1

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol SOFTM [15:8] Reset 0 Soft Reset 0

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Access R/W Bit Symbol Description 7-0 SOFTM [15:8] SOF Mask Timer: Time since last SOF in 30MHz clock bit.

12.1.13.8 PHY Test Mode Selector Register (Offset == 0x08)

This one-byte register allows the firmware to set the D+/D- lines to predetermined states for testing purposes.

The bit allocation is given in the following table. Only one bit can be set at a time.

Table 114. PHY Test Mode Selector Register.


Symbol Reserved Reserved Reserved TST_PKT TST_SE0NAK TST_KSTA TST_JSTA UNPLUG

Reset - - - 0 0 0 0 1 Bus Reset - 0 Access - - - R/W R/W R/W R/W R/W

Bit Symbol Description 7-5 Reserved Reserved bit.

4 TST_PKT Test Mode for Packet: Upon writing a ‘1’ to this bit, FUSB220 repetitively sends the packet defined in UTMI specification to the transceiver. After the set_feature command shows test mode and index Test_Packet is decoded, this bit will be asserted.

3 TST_SE0NAK Upon writing a ‘1’, the D+/D- lines are set to HS, quiescent state. The device only responds to a valid HS IN token and always responds to the IN token with NAK.

2 TST_KSTA Upon writing a ‘1’, the D+/D- is set to the high-speed K state. 1 TST_JSTA Upon writing a ‘1’, the D+/D- is set to the high-speed J state.

0 UNPLUG

With UNPLUG set to logic ‘1’, the device controller will set PHY in Non-Driving mode, to emulate the detachment of a device even if it is really pluged. The USB host will not detect the plug of a device. Such an event is called soft-detachment. After hardware reset, UNPLUG will be logic ‘1’ and therefore the device is soft-detached. To let USB host detect the attachment of a device, PHY must drive D+ and D- in the manner defined in the USB specification. To let PHY drive D+ and D-, the AP should clear UNPLUG after hardware reset. If AP does not clear UNPLUG bit, the device will always be soft-detached and the USB host will never detect the attachment of the device.

12.1.13.9 Vendor Specific IO Control Register (Offset == 0x09)

This register is provided for vendor defined test control and status for PHY.

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Table 115. Vendor Specific IO Control Register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol Reserved Reserved Reserved VCTLAD_N VCTL [3:0] Reset - - - 0 0 Access - - - R/W R/W

Bit Symbol Description 7-5 Reserved Reserved bit.

4 VCTLOAD_N Vendor-Specific Test Mode Control Load. This bit controls the active low output u_vctload_n to PHY. A ‘1’ in this bit makes u_vctload_n output a ‘1’. When the bit is cleared, u_vctload_n outputs a ‘0’.

3-0 VCTL [3:0] Vendor-Specific Test Mode Control. The programmed value is delivered to PHY via the output “u_vctl”.

12.1.13.10 Vendor Specific IO Status Register (Offset == 0x0A)

The reset value depends on PHY.

Table 116. Vendor Specific IO Status Register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol VSTA [7:0] Reset The value is derived from PHY directly Access R

Bit Symbol Description 7-0 VSTA [7:0] Vendor-Specific Test Mode Status.

12.1.13.11 CX Configuration and Status Register (Offset == 0x0B)

CX Configuration and Status Register is used to control the FIFO management for endpoint0. Maximum packet

size for Endpoint 0 is 64 bytes.

Table 117. CX Configuration and Status Register.


Symbol Reserved Reserved CX_EMP CX_FUL CX_CLR CX_STL TST_PKDONE CX_DONE

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189

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset - - 1 0 0 0 0 0 Bus Reset - 0 - 0 Access - - R R R/W R/W R/W R/W

Bit Symbol Description 7-6 Reserved Reserved bit. 5 CX_EMP CX FIFO is Empty: A ‘1’ indicates that the endpoint 0 FIFO is empty. 4 CX_FUL CX FIFO is Full: A ‘1’ indicates that the endpoint 0 FIFO is full.

3 CX_CLR Clear CX FIFO Data: Write a ‘1’ to clear the data in endpoint 0 FIFO. Note that for endpoint 0, all the data in the FIFO will be cleared no matter the previous SETUP or IN or OUT transaction has completed or not.

2 CX_STL Stall CX: Writing a ‘1’ to this bit can stall Endpoint 0. The stall status will be cleared by the next setup transaction. This bit will be cleared automatically when the endpoint 0 transaction is ended. Upon detection of bus reset, the firmware should clear this bit.

1 TST_PKDONE Data Transfer is Done for Test Packet: Firmware has completely sent the whole test patterns to endpoint 0 FIFO for PHY test by writing a ‘1’ to this bit. This bit is cleared by hardware reset.

0 CX_DONE Data Transfer is Done for CX: Firmware has finished the whole packet transaction for endpoint 0 by writing a ‘1’ to this bit. This bit is cleared by hardware reset. This bit is cleared by internal signals p_endcx or p_comfail.

12.1.13.12 Endpoint 0 Data Port Register Byte 0 (Offset == 0x0C)

The address 0CH provides a micro-controller direct access to the FIFO of endpoint 0. To access endpoint 0 FIFO,

the AP should use address 0CH only.

For example, to read a 31-byte packet from CXF FIFO, the AHB master should issue the following cycles:

Cycle Number HADDR HTRANS HSIZE

1 0CH NONSEQUENTIAL word 2 0CH NONSEQUENTIAL word 3 0CH NONSEQUENTIAL word 4 0CH NONSEQUENTIAL word 5 0CH NONSEQUENTIAL word 6 0CH NONSEQUENTIAL word 7 0CH NONSEQUENTIAL word 8 0CH NONSEQUENTIAL halfword 9 0CH NONSEQUENTIAL byte

Alternatively, the AHB master may issue eight (8) NONSEQUENTIAL read cycles with word size and discard the

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invalid byte.

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191

12.1.13.13 Interrupt Group Mask Register (Offset == 0x10)

To disable interrupt, the micro-controller should set corresponding bit as 1.

Table 118. Interrupt Group Mask Register.


Symbol MINT_SCR7

MINT_SCR6

MINT_SCR5

MINT_SCR4

MINT_SCR3

MINT_SCR2

MINT_SCR1

MINT_SCR0

Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W


7 MINT_SCR7 Mask all the interrupt bits of Interrupt Source Register Byte 7. 0: Enable corresponding interrupt 1: Disable corresponding interrupt








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12.1.13.14 Interrupt Mask Register Byte 0 (Offset == 0x11) Table 119. Interrupt Mask Register Byte 0.


Symbol MR_COM_ABORT Reserved MRBUF_E

RR MCX_COMFAIL_INT

MCX_COMEND_INT

MCX_OUT_INT

MCX_IN_INT

MCX_SETUP_INT

Reset -0 - 1 0 0 0 0 0 Access R/W - R/W R/W R/W R/W R/W R/W


7 MR_COM_ABORT Mask command abort interrupt. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

6 Reserved Reserved.

5 MRBUF_ERR Mask the read HBF error interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

4 MCX_COMFAIL_INT Mask the interrupt caused by the host emitting extra IN or OUT data. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

3 MCX_COMEND_INT Mask the host end of command (entering status stage) interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

2 MCX_OUT_INT Mask the interrupt bits of endpoint 0 for OUT. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

1 MCX_IN_INT Mask the interrupt bits of endpoint 0 for IN. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

0 MCX_SETUP_INT Mask endpoint 0 setup data received interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt



Symbol MF3_SPK_INT

MF3_OUT_INT

MF2_SPK_INT

MF2_OUT_INT

MF1_SPK_INT

MF1_OUT_INT

MF0_SPK_INT

MF0_OUT_INT

Reset 1 1 1 1 1 1 1 1

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193

Access R/W R/W R/W R/W R/W R/W R/W R/W

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7 MF3_SPK_INT Mask the Short Packet Interrupt of FIFO 3. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

6 MF3_ OUT_INT Mask the OUT interrupt of FIFO 3. 0: Enable corresponding interrupt 1: Disable corresponding interrupt





1 MF0_SPK_INT Mask the Short Packet Interrupt of FIFO 0 0: Enable corresponding interrupt 1: Disable corresponding interrupt




Symbol MF7_SPK_INT

MF7_OUT_INT

MF6_SPK_INT

MF6_OUT_INT

MF5_SPK_INT

MF5_OUT_INT

MF4_SPK_INT

MF4_OUT_INT




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195


6 MF7_OUT_INT Mask the OUT interrupt of FIFO 7. 0: Enable corresponding interrupt 1: Disable corresponding interrupt









Symbol MF11_SPK_INT

MF11_OUT_INT

MF10_SPK_INT

MF10_OUT_INT

MF9_SPK_INT

MF9_OUT_INT

MF8_SPK_INT

MF8_OUT_INT





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Symbol MF15_SPK_INT

MF15_OUT_INT

MF14_SPK_INT

MF14_OUT_INT

MF13_SPK_INT

MF13_OUT_INT

MF12_SPK_INT

MF12_OUT_INT






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197









Symbol MF7_IN_INT

MF6_IN_INT

MF5_IN_INT

MF4_IN_INT

MF3_IN_INT

MF2_IN_INT

MF1_IN_INT

MF0_IN_INT



7 MF7_IN_INT Mask the IN interrupt bits of FIFO 7. 0: Enable corresponding interrupt 1: Disable corresponding interrupt




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199



Symbol MF15_IN_INT

MF14_IN_INT

MF13_IN_INT

MF12_IN_INT

MF11_IN_INT

MF10_IN_INT

MF9_IN_INT

MF8_IN_INT













Symbol MRX0BTYE_INT

MTX0BYTE_INT

MSEQ_ABORT_INT

MSEQ_ERR_INT

MRESM_INT

MSUSP_INT

MUSBRST_INT

MHBF_EMPTY_INT

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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W


7 MRX0BTYE_INT

Mask Received Zero-length Data Packet Interrupt. Mask the Active to Received Zero-length Data Packet interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

6 MTX0BYTE_INT

Mask Transferred Zero-length Data Packet Interrupt. Mask the Active to Transferred Zero-length Data Packet interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

5 MISO_SEQ_ABORT_INT

Mask ISO Sequential Abort Interrupt. Mask the Active to ISO Sequential Abort interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

4 MISO_SEQ_ERR_INT

Mask ISO Sequential Error Interrupt. Mask the Active to Received ISO Sequential Error interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

3 MRESM_INT Mask Resume Interrupt. Mask the Active to Resume State Change interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

2 MSUSP_INT Mask Suspend Interrupt. Mask the Active to Suspend State Change interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

1 MUSBRST_INT Mask USB Reset Interrupt. Mask the Bus Reset interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

0 MHBF_EMPTY_INTMask HBF Empty interrupt. Mask the MBF Empty interrupt bit. 0: Enable corresponding interrupt 1: Disable corresponding interrupt

12.1.13.22 Receive Zero-length Data Packet Register Byte 0 (Offset == 0x19)

When Receive Zero-length Data Packet Interrupt occurs (bit 7 of register 28H), the firmware would further check

registers 19H and 1AH to determine which endpoint received the zero-length data packet. This register should be

cleared by firmware.

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201

Table 127. Receive Zero-length Data Packet Register Byte 0.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol rx0byte_ep7 rx0byte_ep6 rx0byte_ep5 rx0byte_ep4 rx0byte_ep3 rx0byte_ep2 rx0byte_ep1 Reserved Reset 0 0 0 0 0 0 0 - Access R/W R/W R/W R/W R/W R/W R/W -

Bit Symbol Description 7 rx0byte_ep7 Endpoint 7 receives a zero-length data packet. 6 rx0byte_ep6 Endpoint 6 receives a zero-length data packet. 5 rx0byte_ep5 Endpoint 5 receives a zero-length data packet. 4 rx0byte_ep4 Endpoint 4 receives a zero-length data packet. 3 rx0byte_ep3 Endpoint 3 receives a zero-length data packet. 2 rx0byte_ep2 Endpoint 2 receives a zero-length data packet. 1 rx0byte_ep1 Endpoint 1 receives a zero-length data packet. 0 Reserved -

12.1.13.23 Receive Zero-length Data Packet Register Byte 1 (Offset == 0x1A) Table 128. Receive Zero-length Data Packet Register Byte 1.


Symbol rx0byte_ep15

rx0byte_ep14

rx0byte_ep13

rx0byte_ep12

rx0byte_ep11

rx0byte_ep10 rx0byte_ep9 rx0byte_ep8


Bit Symbol Description 7 rx0byte_ep15 Endpoint 15 receives a zero-length data packet. 6 rx0byte_ep14 Endpoint 14 receives a zero-length data packet. 5 rx0byte_ep13 Endpoint 13 receives a zero-length data packet. 4 rx0byte_ep12 Endpoint 12 receives a zero-length data packet. 3 rx0byte_ep11 Endpoint 11 receives a zero-length data packet. 2 rx0byte_ep10 Endpoint 10 receives a zero-length data packet. 1 rx0byte_ep9 Endpoint 9 receives a zero-length data packet. 0 rx0byte_ep8 Endpoint 8 receives a zero-length data packet.

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12.1.13.24 FIFO Empty Byte 0 (Offset == 0x1C)

By polling this register, firmware can know whether the FIFO is completely empty.

Table 129. FIFO Empty Byte 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol fempt_f7 fempt_f6 fempt_f5 fempt_f4 fempt_f3 fempt_f2 fempt_f1 fempt_f0

Reset 0 0 0 0 0 0 0 0

Access R R R R R R R R

Bit Symbol Description 7 fempt_f7 1: FIFO 7 is fully empty 0: FIFO 7 is not fully empty 6 fempt_f6 1: FIFO 6 is fully empty 0: FIFO 6 is not fully empty 5 fempt_f5 1: FIFO 5 is fully empty 0: FIFO 5 is not fully empty 4 fempt_f4 1: FIFO 4 is fully empty 0: FIFO 4 is not fully empty 3 fempt_f3 1: FIFO 3 is fully empty 0: FIFO 3 is not fully empty 2 fempt_f2 1: FIFO 2 is fully empty 0: FIFO 2 is not fully empty 1 fempt_f1 1: FIFO 1 is fully empty 0: FIFO 1 is not fully empty 0 fempt_f0 1: FIFO 0 is fully empty 0: FIFO 0 is not fully empty

12.1.13.25 FIFO Empty Byte 1 (Offset == 0x1D) Table 130. FIFO Empty Byte 1

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol fempt_f15 fempt_f14 fempt_f13 fempt_f12 fempt_f11 fempt_f10 fempt_f9 fempt_f8

Reset 0 0 0 0 0 0 0 0

Access R R R R R R R R

Bit Symbol Description 7 fempt_f15 1: FIFO 15 is fully empty 0: FIFO 15 is not fully empty 6 fempt_f14 1: FIFO 14 is fully empty 0: FIFO 14 is not fully empty 5 fempt_f13 1: FIFO 13 is fully empty 0: FIFO 13 is not fully empty 4 fempt_f12 1: FIFO 12 is fully empty 0: FIFO 12 is not fully empty 3 fempt_f11 1: FIFO 11 is fully empty 0: FIFO 11 is not fully empty 2 fempt_f10 1: FIFO 10 is fully empty 0: FIFO 10 is not fully empty 1 fempt_f9 1: FIFO 9 is fully empty 0: FIFO 9 is not fully empty

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203

0 fempt_f8 1: FIFO 8 is fully empty 0: FIFO 8 is not fully empty

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12.1.13.26 Interrupt Group Register (Offset == 0x20)

The returned value read by the micro-controller is the raw status of the register.

Table 131. Interrupt Group Register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol INT_SCR7 INT_SCR6 INT_SCR5 INT_SCR4 INT_SCR3 INT_SCR2 INT_SCR1 INT_SCR0Reset 1 0 0 0 0 0 0 0 Access R R R R R R R R

Bit Symbol Description 7 INT_SCR7 Indicates the occurrence of some interrupts in “Interrupt Source Register Byte 7”. 6 INT_SCR6 Indicates the occurrence of some interrupts in “Interrupt Source Register Byte 6”. 5 INT_SCR5 Indicates the occurrence of some interrupts in “Interrupt Source Register Byte 5”. 4 INT_SCR4 Indicates the occurrence of some interrupts in “Interrupt Source Register Byte 4”. 3 INT_SCR3 Indicates the occurrence of some interrupts in “Interrupt Source Register Byte 3”. 2 INT_SCR2 Indicates the occurrence of some interrupts in “Interrupt Source Register Byte 2”. 1 INT_SCR1 Indicates the occurrence of some interrupts in “Interrupt Source Register Byte 1”. 0 INT_SCR0 Indicates the occurrence of some interrupts in “Interrupt Source Register Byte 0”.

12.1.13.27 Interrupt Source Register Byte 0 (Offset == 0x21)


Table 132. Interrupt Source Register Byte 0.


Symbol CX_COMABT_INT Reserved RBUF_ERR CX_COMFA

IL_INT CX_COME

ND_INT CX_OUT_I

NT CX_IN_INT CX_SETUP_INT

Reset 0 - 0 0 0 0 0 0 Access R/W - R/W R R R R R

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205


7 CX_COMABT_INT

Indicates a command abort event has occurred. For interrupts recoded in this source register, a command abort interrupt receives the highest priority. For a command abort interrupt, the AP should only clear the CX_COMABT_INT bit. All other operations are unnecessary and should be avoided. In general, the command abort interrupt will be accompanied by a CX_SETUP_INT. The AP should service the command abort interrupt first in order to clear the CX_COMABT_INT. This is done because the CXF FIFO is frozen for AP access when the CX_COMABT_INT remains at one. To get the 8-byte for SETUP without generating command abort, the AP should clear CX_COMABT_INT first.

6 Reserved Reserved. 5 RBUF_ERR Indicates that AP reads an empty FIFO. This bit should be cleared by firmware.

4 CX_COMFAIL_INT

Indicates that the control transfer has abnormally terminated. This bit will be asserted when FUSB220 received extra IN/OUT token at the data stage of control transfer. Once this bit is asserted, it will be kept at ‘1’ before AP sets CX_STL bit of CX_Config_Status register. After setting CX_STL bit of CX_Config_Status register, AP should set CX_DONE bit of CX_Config_Status register.

3 CX_COMEND_INT

Indicates that the control transfer has entered status stage. This bit will remain asserted before firmware sets CX_DONE bit of CX Configuration and Status Register (Address 0B, bit 0). The bit will remain unchanged after AP sets CX_STL bit of CX_Config_Status register.

2 CX_OUT_INT

Indicates that the control transfer contains valid data for control-write transfers. This bit will remain asserted until firmware starts to read data from control transfer FIFO (CXF) of FUSB220. This bit will be cleared after AP sets CX_STL bit of CX_Config_Status register.

1 CX_IN_INT

Indicates that firmware should write data for control-read transfer to control transfer FIFO. For control-read with length less than or equal to 64-byte, this bit will never be asserted. The firmware will decode the 8-byte data sent in SETUP stage of control transfer. The firmware should write first payload of data into control transfer FIFO if the 8-byte indicates control-read transfer, without assertion of this bit. This bit will be asserted only when the length of control-read transfer is longer than 64-byte and USB host has successfully received the data of previous packet. For example, for a 65-byte control-read transfer, the firmware should automatically write the first 64-byte after it decodes 8 bytes of SETUP data. The firmware will be interrupted to write the 65th byte when the USB host ACKs to the first 64-byte. This bit will remain asserted until firmware starts to write data into control transfer FIFO (CXF) of FUSB220. This bit will be cleared after AP sets CX_STL bit of CX_Config_Status register.

0 CX_SETUP_INT This bit will remain asserted until firmware starts to read data from control transfer FIFO (CXF) of FUSB220. This bit will remain unchanged after AP sets CX_STL bit of CX_Config_Status register.

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The returned value read by the micro-controller is the raw status of the register.In the case of ping-pong FIFO, the

firmware has only to attend to the status of the “first” FIFO. For example, if FIFO0, FIFO1 and FIFO2

“ping-pong” for OUT endpoint 1, the firmware only needs to attend to the status of FIFO0.



Symbol F3_SPK_INT

F3_OUT_INT

F2_SPK_INT

F2_OUT_INT

F1_SPK_INT

F1_OUT_INT

F0_SPK_INT

F0_OUT_INT

Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R


7 F3_SPK_INT This bit becomes 1 when short packet data are received in FIFO3. This bit is cleared once AHB master reads FIFO3.

6 F3_OUT_INT This bit becomes 1 when FIFO3 is ready to be read. This bit is cleared when all data in FIFO3 are read out.







12.1.13.29 Interrupt Source Register Byte 2 (Offset == 0x23) The returned value read by the micro-controller is the raw status of the register. Table 134. Interrupt Source Register Byte 2.


Symbol F7_SPK_INT

F7_OUT_INT

F6_SPK_INT

F6_OUT_INT

F5_SPK_INT

F5_OUT_INT

F4_SPK_INT

F4_OUT_INT


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207










12.1.13.30 Interrupt Source Register Byte 3 (Offset == 0x24) The returned value read by the micro-controller is the raw status of the register. Table 135. Interrupt Source Register Byte 3.


Symbol F11_SPK_INT

F11_OUT_INT

F10_SPK_INT

F10_OUT_INT

F9_SPK_INT

F9_OUT_INT

F8_SPK_INT

F8_OUT_INT








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The returned value read by the micro-controller is the raw status of the register, not the masked status.



Symbol F15_SPK_INT

F15_OUT_INT

F14_SPK_INT

F14_OUT_INT

F13_SPK_INT

F13_OUT_INT

F12_SPK_INT

F12_OUT_INT











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209


The returned value read by the micro-controller is the raw status of the register, not the masked status In the case

of ping-pong FIFO, the firmware has only to attend to the status of the “first” FIFO. For example, if FIFO0, FIFO1

and FIFO2 “ping-pong” for IN endpoint 1, the firmware only needs to attend to the status of FIFO0.

Generally, these interrupt sources indicate whether the FIFO is ready to receive data from AHB. But if the FIFO is

dedicated to interrupt type endpoint, the interrupt source would occur only after the USB host has issued IN

transfer while FIFO is empty.


Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol F7_IN_INT F6_IN_INT F5_IN_INT F4_IN_INT F3_IN_INT F2_IN_INT F1_IN_INT F0_IN_INTReset 0 0 0 0 0 0 0 0 Access R R R R R R R R


7 F7_IN_INT

This bit becomes 1 to indicate FIFO7 is ready to be written. This bit is cleared under three conditions: A maximum-size packet is received in FIFO7. AHB master ends the transfer with the signal dma_termwr. CPU sets the Done bit of register A7H.

6 F6_IN_INT


5 F5_IN_INT


4 F4_IN_INT


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3 F3_IN_INT


2 F2_IN_INT


1 F1_IN_INT


0 F0_IN_INT






Symbol F15_IN_INT

F14_IN_INT

F13_IN_INT

F12_IN_INT

F11_IN_INT

F10_IN_INT F9_IN_INT F8_IN_INT



7 F15_IN_INT


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211


6 F14_IN_INT


5 F13_IN_INT


4 F12_IN_INT


3 F11_IN_INT


2 F10_IN_INT


1 F9_IN_INT


0 F8_IN_INT



When bus resets, bits [3:1] is reset to 3’b001.

Note that when the TX0BYTE_IEPx bit (see section 12.1.13.45) is applied to an IN endpoint, AP should not send

the next packet to the endpoint until the TX0BYTE_INT interrupt occurs.

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Symbol RX0BTYE_INT

TX0BYTE_INT

ISO_SEQ_ABORT_IN

T

ISO_SEQ_ERR_INT RESM_INT SUSP_INT USBRST_I

NT MBF_EMP

TY_INT

Reset 0 0 0 0 0 0 0 1 Bus Reset - - - - 0 0 1 Access R/W R/W R/W R/W R/W R/W R/W R


7 RX0BYTE_INT

Received Zero-length Data Packet Interrupt. FUSB220 received a zero-length data packet from USB host. When FUSB220 received a zero-length data packet from USB host, this bit will be set. The firmware may further check registers 19H and 1AH to determine which endpoint received a zero-length data packet from USB host. When the interrupt occurs, FUSB220 will NAK the next OUT transaction to the same endpoint until the corresponding bit (in 19H or 1AH) is cleared by firmware. This bit is not affected by USB bus reset.

6 TX0BYTE_INT

Transferred Zero-length Data Packet Interrupt. FUSB220 returned a zero-length data packet to USB host. This bit will be set under the following two cases: When USB host issues an IN transaction to an isochronous endpoint while the FUSB220 is not ready to return data, the FUSB220 will transfer a zero-length data packet to USB host. In such case, this bit will be set. When TX0BYTE_IEPx bit is set, after the endpoint’s data in FIFO are transferred, FUSB220 will return a zero-length data packet to the next IN transaction to the same endpoint. The firmware may further check registers 2DH and 2EH to determine which endpoint returns a zero-length data packet to USB host. After AP serviced the interrupt request, the bit must be cleared by firmware. This bit is not affected by USB bus reset.

5 ISO_SEQ_ABORT_INT

ISO Sequential Abort Interrupt. High bandwidth isochronous sequential abort. When FUSB220 detects an incomplete DATA PID sequence during a microframe, this bit will be set. For example, if FUSB220 detects an MDATA followed by an SOF, this is taken as sequential abort. The firmware should further check registers 2BH and 2CH to determine which endpoint received an isochronous sequential abort. After AP serviced the interrupt request, this bit must be cleared by firmware. This bit is not affected by USB bus reset.

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213


4 ISO_SEQ_ERR_INT

ISO Sequential Error Interrupt. High bandwidth isochronous sequential error. When FUSB220 detects DATA PID sequence error of isochronous transaction in high bandwidth, this bit will be set. Any out of order sequence will be taken as sequence error. The firmware should further check registers 29H and 2AH to determine which endpoint received an isochronous sequential error. After AP serviced the interrupt request, this bit must be cleared by firmware. This bit is not affected by USB bus reset.

3 RESM_INT

Resume Interrupt. Resume-state-change interrupt bit. When FUSB220 detects resume event from host, this bit will be set. After AP serviced the interrupt request, this bit must be cleared by firmware. When USB bus reset occurs, it will also be cleared.

2 SUSP_INT

Suspend Interrupt. Suspend-state-change interrupt bit. When USB bus remains in idle state for over 3ms, this bit will be set. This bit must be cleared before firmware sets the “GOSUSP” of register 00H. This bit will also be cleared when USB bus reset or resume occurs.

1 USBRST_INT USB Reset Interrupt. Bus reset interrupt bit. When FUSB220 detects USB bus reset from host, the bit will be set. When AP serviced the interrupt request, this bit must be cleared by firmware.

0 HBF_EMPTY_INT HBF Empty Interrupt. Before sending data to FUSB220, AP should make sure that HBF is empty and FIFO is not full. Please note that the value of this bit is not masked during CPU reads.

12.1.13.35 Isochronous Sequential Error Register Byte 0 (Offset == 0x29)

When an Isochronous Sequential Error Interrupt occurs (bit 4 of register 28H), the firmware would further check

registers 29H and 2AH to determine which endpoint received the isochronous sequential error. This bit should be

cleared by firmware.

Table 140. Isochronous Sequential Error Register Byte 0.


Symbol iso_seq_err_ep7

iso_seq_err_ep6

iso_seq_err_ep5

iso_seq_err_ep4

iso_seq_err_ep3

iso_seq_err_ep2

iso_seq_err_ep1 Reserved

Reset 0 0 0 0 0 0 0 - Access R/W R/W R/W R/W R/W R/W R/W -

Bit Symbol Description 7 iso_seq_err_ep7 Endpoint 7 receives an isochronous sequential error. 6 iso_seq_err_ep6 Endpoint 6 receives an isochronous sequential error. 5 iso_seq_err_ep5 Endpoint 5 receives an isochronous sequential error. 4 iso_seq_err_ep4 Endpoint 4 receives an isochronous sequential error.

AG101


Bit Symbol Description 3 iso_seq_err_ep3 Endpoint 3 receives an isochronous sequential error. 2 iso_seq_err_ep2 Endpoint 2 receives an isochronous sequential error. 1 iso_seq_err_ep1 Endpoint 1 receives an isochronous sequential error. 0 Reserved -

AG101


215

12.1.13.36 Isochronous Sequential Error Register Byte 1 (Offset == 0x2A) Table 141. Isochronous Sequential Error Register Byte 1.


Symbol iso_seq_err_ep15

iso_seq_err_ep14

iso_seq_err_ep13

iso_seq_err_ep12

iso_seq_err_ep11

iso_seq_err_ep10

iso_seq_err_ep9

iso_seq_err_ep8


Bit Symbol Description 7 iso_seq_err_ep15 Endpoint 15 receives an isochronous sequential error. 6 iso_seq_err_ep14 Endpoint 14 receives an isochronous sequential error. 5 iso_seq_err_ep13 Endpoint 13 receives an isochronous sequential error. 4 iso_seq_err_ep12 Endpoint 12 receives an isochronous sequential error. 3 iso_seq_err_ep11 Endpoint 11 receives an isochronous sequential error. 2 iso_seq_err_ep10 Endpoint 10 receives an isochronous sequential error. 1 iso_seq_err_ep9 Endpoint 9 receives an isochronous sequential error. 0 iso_seq_err_ep8 Endpoint 8 receives an isochronous sequential error.

12.1.13.37 Isochronous Sequential Abort Register Byte 0 (Offset == 0x2B)

When an Isochronous Sequential Abort Interrupt occurs (bits 5 of register 28H), the firmware would further check

registers 2BH and 2CH to determine which endpoint received an isochronous sequential abort. This register should

be cleared by firmware.

Table 142. Isochronous Sequential Abort Register Byte 0.


Symbol iso_seq_abt_ep7

iso_seq_abt_ep6

iso_seq_abt_ep5

iso_seq_abt_ep4

iso_seq_abt_ep3

iso_seq_abt_ep2

iso_seq_abt_ep1 Reserved

Reset 0 0 0 0 0 0 0 - Access R/W R/W R/W R/W R/W R/W R/W -

Bit Symbol Description 7 iso_seq_abt_ep7 Endpoint 7 receives an isochronous sequential abort. 6 iso_seq_abt_ep6 Endpoint 6 receives an isochronous sequential abort. 5 iso_seq_abt_ep5 Endpoint 5 receives an isochronous sequential abort. 4 iso_seq_abt_ep4 Endpoint 4 receives an isochronous sequential abort.

AG101


Bit Symbol Description 3 iso_seq_abt_ep3 Endpoint 3 receives an isochronous sequential abort. 2 iso_seq_abt_ep2 Endpoint 2 receives an isochronous sequential abort. 1 iso_seq_abt_ep1 Endpoint 1 receives an isochronous sequential abort. 0 Reserved -

12.1.13.38 Isochronous Sequential abort Register Byte 1 (Offset == 0x2C) Table 143. Isochronous Sequential Abort Register Byte 1


Symbol iso_seq_abt_ep15

iso_seq_abt_ep14

iso_seq_abt_ep13

iso_seq_abt_ep12

iso_seq_abt_ep11

iso_seq_abt_ep10

iso_seq_abt_ep9

iso_seq_abt_ep8


Bit Symbol Description 7 iso_seq_abt_ep15 Endpoint 15 receives an isochronous sequential abort. 6 iso_seq_abt_ep14 Endpoint 14 receives an isochronous sequential abort. 5 iso_seq_abt_ep13 Endpoint 13 receives an isochronous sequential abort. 4 iso_seq_abt_ep12 Endpoint 12 receives an isochronous sequential abort. 3 iso_seq_abt_ep11 Endpoint 11 receives an isochronous sequential abort. 2 iso_seq_abt_ep10 Endpoint 10 receives an isochronous sequential abort. 1 iso_seq_abt_ep9 Endpoint 9 receives an isochronous sequential abort. 0 iso_seq_abt_ep8 Endpoint 8 receives an isochronous sequential abort.

12.1.13.39 Transferred Zero-length Register Byte 0 (Offset == 0x2D)

When the Transferred Zero-length Data Packet Interrupt occurs (bit 6 of register 28H), the firmware may further

check registers 2DH and 2EH to determine which endpoint returns the zero-length data packet to USB host.

This register should be cleared by firmware.

Table 144. Transferred Zero-length Register Byte 0.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol tx0byte_ep7 tx0byte_ep6 tx0byte_ep5 tx0byte_ep4 tx0byte_ep3 tx0byte_ep2 tx0byte_ep1 Reserved Reset 0 0 0 0 0 0 0 - Access R/W R/W R/W R/W R/W R/W R/W -

AG101


217

AG101


Bit Symbol Description 7 tx0byte_ep7 Endpoint 7 transfers a zero-length data packet. 6 tx0byte_ep6 Endpoint 6 transfers a zero-length data packet. 5 tx0byte_ep5 Endpoint 5 transfers a zero-length data packet. 4 tx0byte_ep4 Endpoint 4 transfers a zero-length data packet. 3 tx0byte_ep3 Endpoint 3 transfers a zero-length data packet. 2 tx0byte_ep2 Endpoint 2 transfers a zero-length data packet. 1 tx0byte_ep1 Endpoint 1 transfers a zero-length data packet. 0 Reserved -

12.1.13.40 Transferred Zero-length Register Byte 1 (Offset == 0x2E) Table 145. Transferred Zero-length Register Byte 1.


Symbol tx0byte_ep15

tx0byte_ep14

tx0byte_ep13

tx0byte_ep12

tx0byte_ep11

tx0byte_ep10 tx0byte_ep9 tx0byte_ep8


Bit Symbol Description 7 tx0byte_ep15 Endpoint 15 transfers a zero-length data packet. 6 tx0byte_ep14 Endpoint 14 transfers a zero-length data packet. 5 tx0byte_ep13 Endpoint 13 transfers a zero-length data packet. 4 tx0byte_ep12 Endpoint 12 transfers a zero-length data packet. 3 tx0byte_ep11 Endpoint 11 transfers a zero-length data packet. 2 tx0byte_ep10 Endpoint 10 transfers a zero-length data packet. 1 tx0byte_ep9 Endpoint 9 transfers a zero-length data packet. 0 tx0byte_ep8 Endpoint 8 transfers a zero-length data packet.

12.1.13.41 Idle Counter (Offset == 0x2F) Table 146. Idle Counter.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol Reserved IDLE_CNT Reset 0 0 Access R R/W

AG101


219


2:0 IDLE_CNT

Control the timing delay from the time indicated in the GOSUSP bit of the main control register to the time FUSB220 entered suspend mode. The delay is denoted as tsusp_delay in the following figure for reference. 000: tsusp_delay = 0ms. 001: tsusp_delay = 1ms. 010: tsusp_delay = 2ms. 011: tsusp_delay = 3ms. 100: tsusp_delay = 4ms. 101: tsusp_delay = 5ms 110: tsusp_delay = 6ms. 111: tsusp_delay = 7ms. Note: The USB2.0 specification defines TSUSP to mandate that the device should enter suspend mode no later than 10ms after D+/D- is continuously in idle state. The firmware programmer should be cautious in programming the value of tsusp_delay.

u_clk

pw_save(FUSB220)

go_suspend

u_susp_n(FUSB220)

D+

at least 2ms

FUSB220 suspended

*1

tsusp_delay

*1 go_suspend is the internal signal of the FUSB220, which is not visible to AP. However, AP can set/clear it by writing 1/0 to GOSUSP of main control register. The vaule of tsusp_delay can be set by AP. Please refer to the idle_cnt register for details.

Figure 30. Timing Diagram for tsusp_delay Programming.

12.1.13.42 Endpoint x Map Register (One per Endpoint, x = 1 ~ 15) (Offset == 0x30 ~ 0x3E)

This register records the mapped FIFO number of each non-control-transfer 0 endpoint.

Table 147. Endpoint x Map Register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol FNO_OEPx [3:0] FNO_IEPx [3:0]

AG101


Reset fH fH Access R/W R/W

AG101


221


7-4 FNO_OEPx [3:0] FIFO Number for OUT Endpoint x: Records the physical FIFO number for logical out endpoint x.

3-0 FNO_IEPx [3:0] FIFO Number for IN Endpoint x: Records the physical FIFO number for logical in endpoint x.

The table below shows the Endpoint x Map Register offset for each endpoint.

Endpoint Number Endpoint x Map

Register Offset (Hex) Endpoint Number

Endpoint x Map Register Offset (Hex)

Endpoint 1 30 Endpoint 9 38 Endpoint 2 31 Endpoint 10 39 Endpoint 3 32 Endpoint 11 3A Endpoint 4 33 Endpoint 12 3B Endpoint 5 34 Endpoint 13 3C Endpoint 6 35 Endpoint 14 3D Endpoint 7 36 Endpoint 15 3E Endpoint 8 37

12.1.13.43 HBF Data Byte Count (Offset == 0x3F)

This register contains byte count information for HBF.

Table 148. HBF Data Byte Count

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol Reserved Reserved Reserved HBF_CNT Reset - - - 0 Access - - - R

Bit Symbol Description 7:5 Reserved Reserved. 4:0 HBF_CNT[4:0] HBF Data Byte Count: Records the data byte count in HBF.

AG101


12.1.13.44 IN Endpoint x MaxPacketSize Register Low Byte (One per Endpoint, x = 1 ~ 15) (Offset == 0x(40+2(x-1))) Table 149. IN Endpoint x MaxPacketSize Register Low Byte.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol MAXPS_IEPx [7:0] Reset 0 Access R/W


7-0 MAXPS_IEPx [7:0] Max Packet Size of IN Endpoint x: Maximum packet size bits [7:0] of endpoint x which is capable of sending or receiving data smaller than or equal to this size.

12.1.13.45 IN Endpoint x MaxPacketSize Register High Byte (One per Endpoint, x = 1 ~ 15) (Offset == 0x(41+2(x-1))) Table 150. IN Endpoint x MaxPacketSize Register High Byte.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Symbol TX0BYTE_IEPx TX_NUM_HBW[1:0] RSTG_IEPx STL_IEPx MAXPS_IEPx [10:8] Reset 0 0 0 0 2H Bus Reset - 0 - Access R/W R/W R/W R/W R/W


7 TX0BYTE_IEPx

Transfer a Zero-length Data Packet from Endpoint x to USB Host. This bit should be set after the last packet of transaction is sent to FIFO by the AHB master. After the endpoint’s data in FIFO are transferred, FUSB220 will return a zero-length data packet to the next IN transaction to the same endpoint. The AP should not send the next packet to the same endpoint until TX0BYTE_INT interrupt for the endpoint (see section 12.1.13.34) occurs. This bit is cleared by hardware automatically when TX0BYTE_INT occurs.

6-5 TX_NUM_HBW_IEPx

Transaction Number for High Bandwidth Endpoint x. TX_NUM_HBW[1:0]: 0 0, 0 1: Indicate endpoint x is non-high-bandwidth 1 0: Two transactions per microframe 1 1: Three transactions per microframe

4 RSTG_IEPx Reset Toggle Sequence for IN Endpoint x: Firmware resets the toggle bit of indexed endpoint x by writing a ‘1’ to this bit. This bit should also be cleared by firmware.

AG101


223


3 STL_IEPx Stall IN Endpoint x: The indexed endpoint x can be stalled by writing a ‘1’ to this bit. The stall status of the indexed endpoint x can be cleared by writing a ‘0’ to this bit.


The table below shows the IN Endpoint x MaxPacketSize Register Low and High Byte offset for each endpoint.

Endpoint Number High Byte Offset (Hex) Low Byte Offset (Hex)

Endpoint 1 41 40 Endpoint 2 43 42 Endpoint 3 45 44 Endpoint 4 47 46 Endpoint 5 49 48 Endpoint 6 4B 4A Endpoint 7 4D 4C Endpoint 8 4F 4E Endpoint 9 51 50 Endpoint 10 53 52 Endpoint 11 55 54 Endpoint 12 57 56 Endpoint 13 59 58 Endpoint 14 5B 5A Endpoint 15 5D 5C

12.1.13.46 OUT Endpoint x MaxPacketSize Register Low Byte (One per Endpoint, x = 1 ~ 15) (Offset == 0x(60+2(x-1))) Table 151. OUT Endpoint x MaxPacketSize Register Low Byte.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol MAXPS_OEPx [7:0] Reset 0 Access R/W


7-0 MAXPS_OEPx [7:0] Max Packet Size of OUT Endpoint x: Maximum packet size bits [7:0] of endpoint x which is capable of sending or receiving data smaller than or equal to this size.

AG101


12.1.13.47 OUT Endpoint x MaxPacketSize Register High Byte (One per Endpoint, x = 1 ~ 15) (Address = 0x(61+2(x-1))) Table 152. OUT Endpoint x MaxPacketSize Register High Byte.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol Reserved Reserved Reserved RSTG_OEPx STL_OEPx MAXPS_OEPx [10:8] Reset - - - 0 0 2H Bus Reset - 0 - Access - - - R/W R/W R/W

Bit Symbol Description 7-5 Reserved Reserved bits.

4 RSTG_OEPx Reset Toggle Sequence for OUT Endpoint x: Firmware resets the toggle bit of indexed endpoint x by writing a ‘1’ to this bit. This bit should also be cleared by firmware.

3 STL_OEPx Stall OUT Endpoint x: Writing a ‘1’ to STL_OEP will stall endpoint x. The stall status of the indexed endpoint x can be cleared by writing a ‘0’ to this bit.


The table below shows the OUT Endpoint x MaxPacketSize Register Low and High Byte offset for each endpoint.

Endpoint Number High Byte Offset (Hex) Low Byte Offset (Hex)

Endpoint 1 61 60 Endpoint 2 63 62 Endpoint 3 65 66 Endpoint 4 67 66 Endpoint 5 69 68 Endpoint 6 6B 6A Endpoint 7 6D 6C Endpoint 8 6F 6E Endpoint 9 71 70

Endpoint 10 73 72 Endpoint 11 77 74 Endpoint 12 77 76 Endpoint 13 79 78 Endpoint 14 7B 7A Endpoint 15 7D 7C

AG101


225

AG101


12.1.13.48 DMA Mode Enable Register Low Byte (Offset == 0x7E)

This register allows the FUSB220 to assert fusb220_dma_req_r according to the enabled FIFO. Only one bit

should be set as ‘1’ between 0x7E and 0x7H at any time. This setting informs the FUSB220 which FIFO is

currently being serviced by the DMA controller.

For example, suppose the FIFO 0 and FIFO 1 are “ping-pong-ing” for IN endpoint 1. Only bit 0 of 0x7E should be

set by firmware. The fusb220_dma_req_r is asserted when either FIFO 0 or FIFO 1 is not full. If endpoint 1 is for

OUT, the fusb220_dma_req_r is asserted when either FIFO 0 or FIFO 1 is not empty.

Table 153. DMA Mode Enable Register Low Byte


Symbol fifo7_dma_en

fifo6_dma_en

fifo5_dma_en

fifo4_dma_en

fifo3_dma_en

fifo2_dma_en

fifo1_dma_en

fifo0_dma_en


12.1.13.49 DMA Mode Enable Register High Byte (Offset == 0x7F)

Please refer to section 12.6.2.48 for detailed information.

Table 154. DMA Mode Enable Register High Byte


Symbol fifo15_dma_en

fifo14_dma_en

fifo13_dma_en

fifo12_dma_en

fifo11_dma_en

fifo10_dma_en

fifo9_dma_en

fifo8_dma_en


12.1.13.50 FIFOx Map Register (One per FIFO, x = 0 ~ 15) (Offset == 0x80 ~ 0x8F) Table 155. FIFOx Map Register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol Reserved Reserved Reserved Dir_Fx EPx_FIFO [3:0] Reset - - - 0 fH Access - - - R/W R/W

AG101


227

Bit Symbol Description 7-5 Reserved Reserved bits. 4 Dir_Fx FIFO Direction: Data transfer direction. 0 = OUT, 1= IN.

3-0 EP_FIFOx [3:0] Endpoint Number for FIFO x: Records the physical endpoint number for physical FIFO x.

The table below shows the FIFOx Map Register offset for each FIFO.

FIFO Number Offset (Hex) FIFO Number Offset (Hex)

FIFO 0 80 FIFO 8 88 FIFO 1 81 FIFO 9 89 FIFO 2 82 FIFO 10 8A FIFO 3 83 FIFO 11 8B FIFO 4 84 FIFO 12 8C FIFO 5 85 FIFO 13 8D FIFO 6 86 FIFO 14 8E FIFO 7 87 FIFO 15 8F

12.1.13.51 FIFOx Configuration Register (One per FIFO, x = 0 ~ 15) (Offset == 0x90 ~ 0x9F)

The PAM can be configured up to sixteen (16) FIFOs numbered from 0 to 15. FIFO0 to FIFO13 are 512-byte,

FIFO14 and FIFO15 are 64-byte each.

A “block” can be composed of one FIFO or two FIFOs depending on the setting of the bit BLKSZ_Fx. When this

bit is set as ‘1’, the block size is 1024-byte; when this bit is set as ‘0’, the block size is 512-byte. For example, if

90H bit 4 is set as ‘1’, it means FIFO0 and FIFO1 are combined just like a 1024-byte FIFO; also known as a

“block”.

The Ping-Pong FIFO mechanism is block-based. For example, if bit 4 of 90H is set as ‘1’ and bits [3:2] are set as

2’b10. When FIFO0 is accessed, three 1024-byte blocks (FIFO0 combined with FIFO1, FIFO2 combined with

FIFO3, and FIFO4 combined with FIFO5) would “Ping-Pong” in turn.

Table 156. FIFOx Configuration Register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol EN_Fx Reserved Reserved BLKSZ_Fx BLKNO_Fx [1:0] TYP_Fx [1:0] Reset 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W

AG101


AG101


229

Bit Symbol Description 7 EN_Fx Enable FIFO x: A ‘1’ indicates that the FIFO is enabled.

6-5 Reserved Reserved bits.

4 BLKSZ_Fx

Block Size of FIFO x: BLKSIZE_Fx = 0 FIFO0 ~ FIFO13: For transferring packets whose maximum packet size is smaller than or equal to 512 bytes FIFO14 & FIFO15: For transferring packets whose maximum packet size is smaller than or equal to 64 bytes BLKSIZE_Fx = 1 FIFO0 ~ FIFO13 : For transferring packets whose maximum packet size is smaller than or equal to 1024 bytes and greater than 512 bytes FIFO14 and FIFO15 : For transferring packets whose maximum packet size is smaller than or equal to 128 bytes and greater than 64 bytes

3-2 BLKNO_Fx [1:0]

Block Number of FIFO x: BLKNUM_Fx = 00 : Single block BLKNUM_Fx = 01 : Double blocks BLKNUM_Fx = 10 : Triple blocks BLKNUM_Fx = 11 : Reserved

1-0 BLK_TYP_Fx [1:0]

Transfer Type of FIFO x: Indicates the transfer type used for FIFOx transfer. TYP_Fx = 00 : Reserved TYP_Fx = 01 : Isochronous type TYP_Fx = 10 : Bulk type TYP_Fx = 11 : Interrupt type

The table below shows the FIFOx Configuration Register offset for each FIFO.


FIFO 0 90 FIFO 8 98 FIFO 1 91 FIFO 9 99 FIFO 2 92 FIFO 10 9A FIFO 3 93 FIFO 11 9B FIFO 4 94 FIFO 12 9C FIFO 5 95 FIFO 13 9D FIFO 6 96 FIFO 14 9E FIFO 7 97 FIFO 15 9F

AG101


12.1.13.52 FIFOx Instruction Register (One per FIFO, x = 0 ~ 15) (Offset == 0xA0 ~ 0xAF)

Table 157. FIFOx Instruction Register.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol Reserved Reserved Reserved FFRST DONE_Fx BC_Fx [10:8] Reset - - - 0 0 0 Access - - - R/W R/W R

Bit Symbol Description 7-5 Reserved Reserved bits.

4 FFRST FIFO x Reset: FIFO can be reset by firmware through setting this bit. This bit must be cleared by firmware after resetting FIFO.

3 DONE_Fx Data Transfer is Done for IN FIFO x: The firmware must set this bit to inform the HBS the whole transaction is completed.

2-0 BC_Fx [10:8] OUT FIFO x Byte Count: BC_Fx [10:0] indicates the byte number of data stored in the FIFO for OUT EPx.

The table below shows the FIFOx Instruction Register offset for each FIFO.


FIFO 0 A0 FIFO 8 A8 FIFO 1 A1 FIFO 9 A9 FIFO 2 A2 FIFO 10 AA FIFO 3 A3 FIFO 11 AB FIFO 4 A4 FIFO 12 AC FIFO 5 A5 FIFO 13 AD FIFO 6 A6 FIFO 14 AE FIFO 7 A7 FIFO 15 AF

12.1.13.53 FIFOx Byte-Count Register Low Byte (One per FIFO, x = 0 ~ 15) (Offset == 0xB0 ~ 0xBF)

The value of the byte-count register is not valid after the hardware resets. The AP should commit verfication only

when OUT interrupts are issued.

Table 158. FIFOx Byte-Count Register Low Byte.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Symbol BC_Fx [7:0] Reset 1

AG101


231

Access R

AG101



7-0 BC_Fx [7:0] OUT FIFO x Byte Count: BC_Fx [10:0] indicates the byte number of data stored in the FIFO for OUT EPx.

The table below shows the FIFOx Byte-Count Register Low Byte offset for each FIFO.


FIFO 0 B0 FIFO 8 B8 FIFO 1 B1 FIFO 9 B9 FIFO 2 B2 FIFO 10 BA FIFO 3 B3 FIFO 11 BB FIFO 4 B4 FIFO 12 BC FIFO 5 B5 FIFO 13 BD FIFO 6 B6 FIFO 14 BE FIFO 7 B7 FIFO 15 BF

12.1.13.54 Data Port Register (Offset == 0xC0 ~ 0xFC)

This address provides a port for an AHB master to access the FIFO of PAM. For insistance, if an AHB master

intends to read data from FIFO 0, it would always issue read cycle with the address C0H. In the case of ping-pong

FIFO, the AHB master would access data via the address of the “first” FIFO. For example, if FIFO2 and FIFO3

“ping-pong” for endpoint 2, the AHB master should always access the data of endpoint 2 via address C4H only.

It is invalid for AHB master to access endpoint 2 via address C8H in this example.

The table below shows the PAM Data Port Register offset for each FIFO.

Table 159. Data Port Register.

FIFO Number Offset (Hex) FIFO Number Offset (Hex) FIFO 0 C0 FIFO 8 E0 FIFO 1 C4 FIFO 9 E4 FIFO 2 C8 FIFO 10 E8 FIFO 3 CC FIFO 11 EC FIFO 4 D0 FIFO 12 F0 FIFO 5 D4 FIFO 13 F4 FIFO 6 D8 FIFO 14 F8 FIFO 7 DC FIFO 15 FC

AG101


233

USB2.0 Transceiver Macrocell Tester (T&MT) Interface

FUSB220 adopts Universal Transceiver Macrocell Tester Interface (T&MT) to communicate with USB2.0

transceiver. T&MT supports 16-bit and 8-bit transfer modes. In FUSB220, 16-bit transfer mode is adopted since

the operation frequency for 16-bit interface is 30MHz. Refer to the USB2.0 Transceiver and Macrocell Tester

(T&MT) Interface Specification for a detail description of the T&MT interface.

12.1.14 FUSB220 Receives Even Data Bytes from Transceiver

The timing example for FUSB220 receiving even-byte of data from the transceiver is shown in Figure 31. At cycle

C0, the transceiver asserts u_rxact to inform FUSB220 that it will transmit data to FUSB220. In this example, 8

bytes of data are sent to FUSB220 by the transceiver. The transceiver sends the first byte of data at cycle C1 by

asserting u_rxval. The signal u_rxvalh is also asserted since the high byte of u_di is also valid. At cycle C5, the

transceiver de-asserts u_rxact to inform FUSB220 of the termination of the data transfer.

C-1 C0 C1 C2 C3 C4 C5

u_clk

u_rxact

u_rxval

u_rxvalh

u_di[7:0] PID Byte1 Byte3 CRC[15:8]

u_di[15:8] Byte0 Byte2 Byte4 CRC[7:0]

Figure 31. FUSB220 Receives Even Data Bytes from Transceiver.

AG101


12.1.15 FUSB220 Receives Odd Data Bytes from Transceiver

Figure 32 shows the timing diagram for FUSB220 receiving odd bytes of data from the transceiver. The transceiver

asserts u_rxact at cycle C0 to notify FUSB220 that it will send data. The u_rxval is asserted by the transceiver at

cycle C1 to indicate the start of data bytes. The transceiver de-asserts u_rxvalh at cycle C4 because only one byte on

u_di is valid at cycle C4. The u_rxact is cleared at cycle C5 by the transceiver to indicate the end of data transfer.

C-1 C0 C1 C2 C3 C4 C5

u_clk

u_rxact

u_rxval

u_rxvalh

u_di[7:0] PID Byte1 Byte3 CRC[7:0]

u_di[15:8] Byte0 Byte2 CRC[15:8]

Figure 32. FUSB220 Receives Odd Data Bytes from Transceiver.

12.1.16 FUSB220 Transmits Even Data Bytes to Transceiver

An example for FUSB220 transmitting 8 bytes of data to the transceiver is shown in Figure 33. At cycle C-1,

FUSB220 asserts u_txval to inform the transceiver that it wishes to start sending data to the transceiver. The signal

u_txvalh is also asserted by FUSB220 since the high byte of u_do is also valid. The transceiver asserts u_txrdy at

cycle C1 because it can receive the data. When detecting the transceiver has received the first 2 bytes of data,

FUSB220 toggles u_do at cycle C2. At cycle C5, FUSB220 de-asserts u_txval to inform the transceiver the

termination of the data transfer. FUSB220 also de-asserts u_txvalh at the same cycle.

AG101


235

C-1 C0 C1 C2 C3 C4 C5

u_clk

u_txrdy

u_txval

u_txvalh

u_do[7:0] PID Byte1 Byte3 CRC[15:8]

u_do[15:8] Byte0 Byte2 Byte4 CRC[7:0]

Figure 33. FUSB220 Transmits Even Data Bytes to Transceiver.

12.1.17 FUSB220 Transmits Odd Data Bytes to Transceiver

An example for FUSB220 transmitting odd data bytes to the transceiver is shown in Figure 34. FUSB220 asserts

u_txval at cycle C-1 to start sending data to the transceiver. Note that FUSB220 also asserts u_txvalh since the high

byte of u_do is valid at the same cycle. The transceiver asserts u_txrdy at cycle C1 to inform FUSB220 that it can

receive data sent by FUSB220. The FUSB220 then toggles u_do at cycle C2. FUSB220 de-asserts u_txvalh at cycle

C4 because only the low byte of u_do is valid at that cycle. The u_txval is de-asserted at cycle C5 by FUSB220 to

indicate the end of data transfer.

C-1 C0 C1 C2 C3 C4 C5

u_clk

u_txrdy

u_txval

u_txvalh

u_do[7:0] PID Byte1 Byte3 CRC[7:0]

u_do[15:8] Byte0 Byte2 CRC[15:8]

Figure 34. FUSB220 Transmits Odd Data Bytes to Transceiver.

AG101


Programming Guide 12.1.18 Bulk / Isochronous / Interrupt Data Transfer 12.1.18.1 Interrupt Handling Wait for interrupt

GRPINT = (ReadFUSB220(Address 0x20) & ~MGPRINT (Address 0x10))

if ((GRPINT[0] & ~MGPRINT[0] == 1)

// Check Control transfer status

if ((GRPINT[7] & ~MGPRINT[7] == 1)

// Special condition interrupt

if (GRPINT[3] & ~MGPRINT[3]== 1 or GRPINT[2] & ~MGPRINT[2] == 1 or GRPINT[1] & ~MGPRINT[1] == 1)

// OUT Endpoint has data in FIFO

Start data transfer

if (GRPINT[6] & ~MGPRINT[6] == 1 or GRPINT[5] & ~MGPRINT[5] == 1) // FIFO for IN Endpoint is not

full

if there is data available

Start data transfer

Else

Mask interrupt

12.1.18.2 IN Endpoint Data Transfer if Read FUSB220(Address 0x26) != 0

calculate corresponding interrupt FIFO_number(n)

else

Read FUSB220(Address 0x27)

calculate corresponding interrupt FIFO_number(n)

mask interrupt of FIFO_number

wait for buffer empty

write data to FIFO_number

if write data complete

if write data number is less than max_packet_size

write 1 to FUSB220(Address 0xAn) : bit 3 // Setting Done_Fn, n=0, 1, 2, …, f

unmask interrupt

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12.1.18.3 OUT Endpoint Data Transfer if Read FUSB220(Address 0x22) != 0

calculate interrupt FIFO_number(n)

else if Read FUSB220(Address 0x23) != 0

Calculate interrupt FIFO_number(n)

else

Read FUSB220(Address 0x24)

Calculate interrupt FIFO_number(n)

mask interrupt of FIFO_number

if short_packet

read ByteCount of FIFO_number

else

ByteCount = MAX_PACKET_SIZE(FIFO_number)

Read data from FIFO_number

unmask interrupt of FIFO_number 12.1.19 Initial Register Setting for FIFO Control 12.1.19.1 Setting the Relationship between Internal FIFO and Endpoint

Two registers have to be set to establish the relationship between the internal FIFO and the endpoint:

Table 160. Endpoint Map Register: Address = 3xH (x = 0 ~ E).


7-4 FNO_OEPx+1 [3:0] FIFO Number for OUT Endpoint x+1: Records the physical FIFO number for logical out endpoint x+1.

3-0 FNO_IEPx+1 [3:0] FIFO Number for IN Endpoint x+1: Records the physical FIFO number for logical in endpoint x+1.

Table 161. FIFO Map Register: Address = 8xH (x = 0 ~ F).

Bit Symbol Description 4 Dir_Fx FIFOx Direction: Data transfer direction: 0 = OUT, 1= IN.

3-0 EP_FIFOx [3:0] Endpoint Number for FIFOx: Records the physical endpoint number for physical FIFO x.

The two registers are in contrast. For example, if you want to have two endpoints, one being endpoint 1 for bulk-in

direction, and the other being endpoint 3 for isochronous-out direction; while you choose FIFO0 to store endpoint

1 data, and FIFO5 to store endpoint 3 data, then the setting will be: write 30 F0H // Assign IN Endpoint 1 to FIFO0 write 32 5FH // Assign OUT Endpoint 3 to FIFO5 write 80 11H // Dedicate FIFO0 to IN Endpoint 1

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write 85 03H // Dedicate FIFO5 to OUT Endpoint 3

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12.1.20 Setting the Properties of Endpoint 12.1.20.1 Max_packet_size for IN Endpoint

Address 40H + (x-1) * 2H for bits [7:0]

Address 40H + (x-1) * 2H + 1 for bits [10:8] (x = 01H ~ 0FH)

Table 162. 40H + (x-1) * 2H for bits [7:0].



Table 163. 40H + (x-1) * 2H + 1 for bits [10:8].


4 RSTG_IEPx Reset Toggle Sequence for IN Endpoint x: Firmware resets the toggle bit of indexed endpoint x by writing a ‘1’ to this bit.

3 STL_IEPx Stall IN Endpoint x: The indexed endpoint x can be stalled by writing a ‘1’ to this bit. The stall status of the indexed endpoint x can be cleared by writing a ‘0’ to this bit.


12.1.20.2 Max_packet_size for OUT Endpoint

Address 60H + (x-1) * 2H for bits [7:0]

Address 60H + (x-1) * 2H + 1 for bits [10:8] (x = 01H ~ 0FH)

Table 164. 60H + (x-1) * 2H for bits [7:0].



Table 165. 60H + (x-1) * 2H + 1 for bits [10:8].


4 RSTG_OEPx Reset Toggle Sequence for OUT Endpoint x: Firmware resets the toggle bit of indexed endpoint x by writing a ‘1’ to this bit.

3 STL_OEPx Stall OUT Endpoint x: Writing a ‘1’ to STL_OEP will stall endpoint x. The stall status of the indexed endpoint x can be cleared by writing a ‘0’ to this bit.


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12.1.20.3 Setting the Properties of Internal FIFO

Register Address 9xH (x = 0H ~ FH) is the FIFO configuration register for setting the FIFO properties:

Bit Symbol Description 7 EN_Fx Enable FIFO x: A ‘1’ indicates that the FIFO is enabled.

6-5 Reserved Reserved bit to be ‘01’.

4 BLKSZ_Fx Block Size of FIFO x: BLKSIZE_Fx = 0: FIFO size smaller than or equal to 512 bytes BLKSIZE_Fx = 1: FIFO size smaller than or equal to 1024 bytes and greater than 512 bytes

3-2 BLKNO_Fx [1:0]

Block Number of FIFO x: BLKNUM_Fx = 00: Single buffered BLKNUM_Fx = 01: Double buffered BLKNUM_Fx = 10: Triple buffered BLKNUM_Fx = 11: Reserved

1-0 BLK_TYP_Fx [1:0]

Transfer Type of FIFOx: Indicates the transfer type used for FIFOx transfer. TYP_Fx = 00: Reserved TYP_Fx = 01: Isochronous type TYP_Fx = 10: Bulk type TYP_Fx = 11: Interrupt type

For example, if you wish to have two endpoints, one being endpoint 1 for bulk-in direction with ping pong buffers

with max_packet_size = 512 bytes, the other being endpoint 3 for isochronous-out direction with single buffer and

max_packet_size = 1024 bytes; you could choose FIFO0 ~ FIFO1 to store endpoint 1 data, and FIFO5 combined

with FIFO6 to store endpoint 3 data, then the setting will be: write 30 F0H // Assign IN Endpoint 1 to FIFO0

write 32 5FH // Assign OUT Endpoint 3 to FIFO5

write 80 11H // Dedicate FIFO0 to IN Endpoint 1

write 85 03H // Dedicate FIFO5 to OUT Endpoint 3

write 40 00H // Set max_Packet_size of IN Endpoint 1 to be 512 bytes

write 41 02H

write 64 00H // Set max_Packet_size of OUT Endpoint 3 to be 1024 bytes

write 65 04H

write 90 86H // Set FIFO0 to be bulk 512 bytes, double buffer

write 91 06H // Set FIFO1 to be bulk 512 bytes, double buffer, setting the FIFO enable

// bit is unnecessary but the transfer type must be set

write 95 91H // Set FIFO5 to be isochronous 1024 bytes, single buffer

// Please note FIFO6 has also been used in conjunction with

// FIFO 5 to become a 1024-byte FIFO

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13 Interrupt Controller (INTC) General Description

Andes’ AG101 Interrupt Controller communicates with the Andes CPU in IVIC mode and EVIC mode. .

Features

Speed: 66 MHz APB clock rate support

Support 32 IVIC HW0 priority level interrupt inputs Support 32 IVIC HW1 priority level interrupt inputs

Support 32 EVIC interrupt inputs

Provide 0(min.)~7(max.) configurable priority levels for each EVIC interrupt input

Provide both edge and level triggered interrupt sources with positive and negative directions(both IVIC and EVIC mode)

Block Diagram

Figure 35 shows the block diagram of the interrupt controller.

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APB Controller

Configure register

Interrupt detection unit

evic mode priority configuration

hw0status[31:0]

hw1status[31:0]{1'b0,Evic_vec_num[4:0]}

HW[0]

HW[1]

HW[5:2]=0int_req[5:0]

ireqval

ireqack

PCLKPRSTn

pselpenablepwrite

paddr[31:0]

pwdata[31:0]

prdata[31:0]

hw1_int_in[31:0]

evic_mode

1

0

hw0_int_in[31:0]

EVIC Interrupt detection

unit

Evic priority arbiter and vector encoder

evic interript source

Figure 35. INTC Block Diagram.

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13.1.1 APB

All registers can be read/written via APB bus protocol.

13.1.2 Config Register Block

The config register block is used to generate the IRQ and FIQ signal fed to the microprocessor.

13.1.3 Interrupt Detect Block

Each hw1 or hw0 interrupt input bit has a corresponding detection logic circuit to generate various types of interrupt.

The generation type of each interrupt bit can be configured by related programmable registers. 13.1.4 EVIC interrupt input detection When the evic_mode is asserted, the following conditions would be changed:

1. The corresponding bit of hw0 and hw1 interrupt input are treated as the same “evic interrupt source bit”.

2. Each “evic interrupt source bit” priority level is depending on the EVIC interrupt priority level configuration

registers(+0x60~0x6c)

IDLE

TAKEN VALID

hw0status | hw1status

~hw0status & ~hw1status~hw0status & ~hw1status

ireqack

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Because the interrupt signals are serviced in turn in EVIC mode, FSM is designed to distinguish the current interrupt

request as either “new request” or “serviced”. 1. When the hw0status or hw1status is asserted while the FSM is in IDLE state, the FSM would transit in VALID

state and the current interrupt request would be defined as a “new request”.

2. If the hw0status and hw1status is cleared while the FSM is in VALID state, then this interrupt need not be serviced.

3. If the “new request” interrupt source has been serviced (the ireqack is 1 and the vector number of corresponding the interrupt source is on the int_req bus), the FSM would transit in the TAKEN state and the current interrupt

would be “serviced”.

4. The FSM waits for the hw0status and hw1status to be cleared before taking in new interrupt assertions.

13.1.5 EVIC priority arbiter and vector encoder

core_clk

bus_clk

ireqval

ireqack

int_req vetcor number When one of “evic interrupt source” is under the “new request” status, the corresponding vector number would be sent to the Andes processor core by the following protocol:

1. Andes Interrupt Controller takes one of the “new request” interrupt vector numbers on the int_req[5:0] bus and set

1 to ireqval.

2. Andes processor core receives the int_req[5:0] to enter corresponding service routine and set 1 to ireqack. 3. When the Andes Interrupt Controller detects the ireqack is 1, the ireqval would be cleared.

4. When the Andes processor core detects the ireqval is cleared, the ireqack would be cleared

When multiple “evic interrupt sources” are under the “new request” status, the Andes Interrupt Controller would follow

two rules to service each of the “evic interrupt sources”. 1. Taking turns by the current highest priority leveled “evic interrupt source”

2. Taking turns under the pseudo LRU policy if the current highest priority leveled “evic interrupt source” count is

more than two. Interrupt Routing Table

The active-high input signals indicate that a peripheral device is requesting an interrupt to the interrupt controller.

The interrupt source assignment is shown in Table 166.

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Table 166. Interrupt Routing Table.

Bit Device Name Description 31 External Device X_hwint3 X_hwint3 30 External Device X_hwint2 X_hwint2 29 External Device X_hwint1 X_hwint1 28 External Device X_hwint0 X_hwint0 27 External Device X_hwint4 X_hwint4

26 USB 2.0 Device usb_int0 Indicates the occurrence of interrupts. The application should read interrupt register to verify the cause of interrupt event.

25 Ethernet MAC mac_int When the mac_int is asserted, the user must read the Interrupt Status Register to find out which interrupt occurred

24 APB Bridge rshint Bridge interface status. 23 Reserved 22 Reserved 21 DMA dmaint Interrupt requests for combining dmaint_tc and dmaint_err 20 Reserved 19 TIMER tm1_intr Timer 1 interrupt signal 18 RTC rtc_sec RTC once-per-second auto alarm

17 RTC rtc_alarm The RTC second, minute and hour counter registers all match with the alarm second, minute and hour registers.

16 WDT wd_intr Watch Dog Timer system interrupt signal 15 TIMER tm3_intr Timer 3 interrupt signal 14 TIMER tm2_intr Timer 2 interrupt signal

13 GPIO gpio_intr When it is at high, this signal indicates that a valid match has occurred between any of the interrupts.

12 External Device X_hwint5 X_hwint5

11 BTUART uartintr2

This pin goes high whenever any one of the following interrupt types has an active high condition and being enabled via the IER: Receiver Error Flag; Received Data Available: timeout (FIFO Mode only); Transmitter Holding Register Empty; and Modem Status. The signal is reset low upon the appropriate interrupt service or a system reset operation.

10 FTUART uartintr1

This pin goes high whenever any one of the following interrupt types has an active high condition and being enabled via the IER: Receiver Error Flag; Received Data Available: timeout (FIFO Mode only); Transmitter Holding Register Empty; and Modem Status. The signal is reset low upon the appropriate interrupt service or a system reset operation.

9 Reserved

8 PMU pmu_fiq Interrupt request for combining power low status, completing FCS and completing Turbo mode.

7 STUART uartintr4 This pin goes high whenever any one of the following interrupt types has an active high condition and being enabled via the IER: Receiver Error Flag; Received Data Available: Timeout (FIFO Mode only); Transmitter Holding Register Empty Status. The signal is reset low upon the appropriate interrupt

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Bit Device Name Description service or a system reset operation.

6 I2S/AC97 ssp2intr

Interrupt generation block collects information (FIFO full/empty, transmit/receive busy, ect.) from transmit/receive control block and transmit the information to the register block as the register value. If interrupt conditions are matched, ssp_intr will be asserted.

5 SDC sdc_intr The interrupt logic will generate the interrupt request signal sdc_intr when at least one of the selected status flag is high.

4 Reserved

3 I2C isi2c

This signal is set if the interrupt enable bit is set in the control register (CR), and the interrupt conditions are met; which means the corresponding status register will be set. When the I2C controller interrupt is asserted, software reads SR bits to check the status of the I2C controller.

2 SSP ssp1intr

Interrupt generation block collects information (FIFO full/empty, transmit/receive busy, ect.) from transmit/receive control block and transmit the information to the register block as the register value. If interrupt conditions are matched, ssp_intr will be asserted.

1 CFC cfc_int_dma_r This signal is asserted high while the active buffer has finished the transaction of a sector of data. It will be reset when the CF Host Status Register has been read.

0 CFC cfc_int_cd_r This signal will be asserted high when the host detects a card insertion. The signal would be de-asserted when the host detects a card desertion event.

Programming Model 13.1.6 Summary of Interrupt Controller Registers

The Interrupt Controller registers are shown in Table 167.

Table 167. Summary of Interrupt Controller Registers.

Address Type Default value Description

+0x00 RO 0 HW1 source register

+0x04 R/W 0 HW1 enable register

+0x08 WO - HW1 interrupt clear register

+0x0C R/W 0 HW1 trigger mode register

+0x10 R/W 0 HW1 trigger level register

+0x14 RO 0 HW1 status register

+0x18~+0x1C - - Reserved

+0x20 RO 0 HW0 source register

+0x24 R/W 0 HW0 enable register

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+0x28 WO - HW0 interrupt clear register

+0x2C R/W 0 HW0 trigger mode register

+0x30 R/W 0 HW0 trigger level register

+0x34 RO 0 HW0 status register

+0x38~+0x3C - - Reserved

+0x50 RO - Revision register

+0x60 R/W 0 EVIC interrupt priority level configuration for bit0~bit7

+0x64 R/W 0 EVIC interrupt priority level configuration

for bit8~bit15


for bit16~bit23


for bit24~bit31

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13.1.7 Register Descriptions 13.1.7.1 HW1(+0x00)/HW0(+0x20) Source Register Width Name Type Description

31:0 hw0srcreg/hw1srcreg RO Shows the status of the interrupts before masking

by the enable registers. A HIGH bit indicates that the appropriate interrupt request is active before

masking. 13.1.7.2 HW1(+0x04)/HW0(+0x24) Enable Register Width Name Type Description

31:0 hw0enreg/hw1enreg R/W Enables the interrupt request lines: 1 = Interrupt enabled. Enables interrupt request to

processor.

0 = Interrupt disabled. 13.1.7.3 HW1(+0x08)/HW0(+0x28) Interrupt Clear Register Width Name Type Description

31:0 hw0clear/hw1clear WO A HIGH bit clears the corresponding bit in the hw0status/hw1status register. A LOW bit renders

no effect. 13.1.7.4 HW1(+0x0C)/HW0(+0x2C) Trigger Mode Register Width Name Type Description

31:0 hw0trigmode/hw1trigmode RW 1: edge trigger 0: level trigger

13.1.7.5 HW1(+0x10)/HW0(+0x30) Trigger Level Register Width Name Type Description

31:0 hw0triglevel/

hw1triglevel

RW 1: Active-high level trigger or rising edge trigger

0: Active-low level trigger or falling edge trigger 13.1.7.6 HW1(+0x0C)/HW0(+0x2C) Status Register Width Name Type Description

31:0 hw0status/

hw1status

RO Shows the status of the interrupts after masking is done by the

enable registers. A HIGH bit indicates that the appropriate

interrupt request is active after masking. 13.1.7.7 Revision Register(+0x50) Width Name Type Description

31:0 intcrevision RO Show the current used interrupt controller revision

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13.1.7.8 EVIC interrupt priority level configuration registers(+0x60~0x6c)

There are 32 EVIC interrupt inputs and each can be counfigured at level 0(min.)~level 7(max.) priority levels. Each EVIC interrupt input corresponds to the 3 bits priority level register and aligns at 4 bits boundary. The 4th bit of each

EVIC interrupt priority level field is reserved. The content in the white grid on the table correspond the bit number of

the EVIC interrupt inputs.

Addr.\bit field 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7 6:4 3 2:0

+0x60 7 6 5 4 3 2 1 0

+0x64 15 14 13 12 11 10 9 8

+0x68 23 22 21 20 19 18 17 16

+0x6C 31 30 29 28 27 26 25 24

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14 General Purpose Input / Output (GPIO) General Description

There are twenty-three (23) GPIOs used to input/output data on the system and devices. Each GPIO can be

programmed as an input, output, or an interrupt input. The GPIO supports rising edge/falling edge, both-edge, and

high level/low level interrupt sense types.

Features

● Up to twenty-three (23) independent input, output and output enable buses for bi-directional I/O pins

● Each port can trigger the GPIO interrupt independently

● Each port interrupt generation can be triggered by rising edge, falling edge, both edges, or high/low level

● Each input port can be pulled high or pulled low

● Programmable sampling rate for all I/O ports

● Output data bit can be set or cleared independently

● All ports are set to input mode at hardware reset

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Block Diagram

Figure 36 shows the block diagram of the GPIO.

AMBA APB interface

Register block

in/out control

interruptcontrol

data register

GpioDataOut[31:0]

IO-MUXPinDir[31:0]

interrupt detection logicgpio_intr

gpio_mis[31:0]

GpioDataIn[31:0]

pullcontrol

pull high or pull down logicdetect logic

bouncecontrol

bounce clock logic

gpio_pullup[31:0]

gpio_pulldown[31:0]

BCLK

gpio_out[31:0]

gpio_in[31:0]

gpio_en[31:0]

Figure 36. GPIO Block Diagram.

The GPIO supports data input/output, data bit set/clear, variable interrupt detection, pull function and bounce

clock.

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Programming Model 14.1.1 Summary Of General Purpose I/O Registers

Table 168 shows the offset, type, width, reset value and name of each GPIO programming registers.

Table 168. Summary of General Purpose I/O Registers.

Address (Offset) Type Width Reset Name Description

+0x00 R/W 32 0x0 GpioDataOut GPIO data output register +0x04 R 32 0x0 GpioDataIn GPIO data input register

+0x08 R/W 32 0x0 PinDir GPIO direction register 0: Input 1: Output

Reserved

+0x10 W 32 0x0 GpioDataSet

GPIO data bit set register When writing to this register, the corresponding bits in data register are set to one, while the other bits are unchanged.

+0x14 W 32 0x0 GpioDataClear

GPIO data bit clear register When writing to this register, the corresponding bits in data register are cleared to zero, while the other bits are unchanged

+0x18 R/W 32 0x0 PinPullEnable GPIO pull enable register 0: Pin is not pulled 1: Pin is pulled

+0x1C R/W 32 0x0 PinPullType GPIO pull high pull low register 0: Pin is pulled low 1: Pin is pulled high

+0x20 R/W 32 0x0 IntrEnable GPIO interrupt enable register 0: Pin interrupt is disabled 1: Pin interrupt is enabled

+0x24 R 32 0x0 IntrRawState GPIO interrupt raw status register 0: Interrupt is not detected 1: Interrupt is detected

+0x28 R 32 0x0 IntrMaskedState GPIO interrupt masked status register 0: Interrupt is not detected or masked 1: Interrupt is detected and not masked

+0x2C R/W 32 0x0 IntrMask GPIO interrupt mask register 0: Mask is disabled 1: Mask is enabled

+0x30 W 32 0x0 IntrClear GPIO interrupt clear

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Address (Offset) Type Width Reset Name Description

0: No effect 1: Clear interrupt

+0x34 R/W 32 0x0 IntrTrigger GPIO interrupt trigger method register 0: Edge trigger 1: Level trigger

+0x38 R/W 32 0x0 IntrBoth GPIO interrupt edge trigger by both 0: Single edge 1: Both edges

+0x3C R/W 32 0x0 IntrRiseNeg

GPIO interrupt trigger by rising or falling edge 0: Rising edge 1: Falling edge GPIO interrupt trigger by high or low level 0: High level 1: Low level

+0x40 R/W 32 0x0 BounceEnable

GPIO pre-scale clock enable. When enabled, PCLK will be divided by BouncePreScale clocks. It is used to extend the clock cycle of detecting interrupt. 0: Disable 1: Enable

+0x44 R/W 24 0x7D0 BouncePreScale

GPIO pre-scale. It is used to adjust different PCLK frequencies. The allowed range is 0x1 ~ 0xFFFF. If BouncePreScale is zero, and Bounce is enabled, this pin cannot detect any interrupt.


The following sections describe the GPIO registers in detail.

14.1.2.1 GpioDataOut (Offset == 0x00)

The GpioDataOut register, as its name implies, is the GPIO data out register. When the PinDir indicates the pin is

in output mode, the GpioDataOut content is connected to gpio_out. When the PinDir indicates the pin is in input

mode, the GpioDataOut can hold the data.

Table 169. Gpio Data Out Register.

Bit Name Type Comment 31-0 GpioDataOut Read / Write None

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14.1.2.2 GpioDataIn (Offset == 0x04)

The GpioDataIn register, as its name suggests, is the GPIO data in register. When the PinDir indicates the pin is in

input mode, the GpioDataIn will latch the value of gpio_in at PCLK rising edge. If the PinDir indicates the pin is in

output mode, the GpioDataIn register value is ignoreable.

Table 170. Gpio Data In Register.

Bit Name Type Comment 31-0 GpioDataIn Read None

14.1.2.3 PinDir (Offset == 0x08)

The PinDir register controls the gpio_en. When the PinDir indicates the pin is in output mode, the related gpio_en

is set to one. Otherwise, the related gpio_en is set to zero.

Table 171. Pin Direction Register.

Bit Name Type Comment 31-0 PinDir Read / Write None

14.1.2.4 GpioDataSet (Offset == 0x10)

GpioDataSet is under one-bit operation logic. When writing to this address, if some bits of GpioDataSet are one,

then the related bits of GpioDataOut will be set also. For example, if GpioDataOut[7:0] = 0x23 and pwdata[7:0]

from APB is 0x47, in a write operation to the GpioDataSet address, the result of GpioDataOut[7:0] will be 0x67.

Table 172. Gpio Data Bit Set Register.

Bit Name Type Comment 31-0 GpioDataSet Write None

14.1.2.5 GpioDataClear (Offset == 0x14)

GpioDataClear is under one-bit operation logic. When writing to this address, if some bits of GpioDataClear are

one, then the related bits of GpioDataOut will be cleared. For example, if GpioDataOut[7:0] = 0x23 and

pwdata[7:0] from APB is 0x47, in a write operation to GpioDataClear address, the result of GpioDataOut[7:0] will

be 0x20.

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Table 173. Gpio Data Bit Clear Register.

Bit Name Type Comment 31-0 GpioDataClear Write None

14.1.2.6 PinPullEnable (Offset == 0x18)

The PinPullEnable register controls the gpio_pullup and gpio_pulldown. If the PinPullEnable indicates the pin is

disabled pull, the gpio_pullup and gpio_pulldown are masked to zero.

Table 174. Pin Pull Enable Register.

Bit Name Type Comment 31-0 PinPullEnable Read / Write None

14.1.2.7 PinPullType (Offset == 0x1C)

PinPullType controls the gpio_pullup and gpio_pulldown. If PinPullEnable is enabled and PinPullType is set to

zero, the gpio_pullup will be set to zero, and the gpio_pulldown will be set to one. The pull truth table is shown in

Table 176.

Table 175. Pin Pull Type Register.

Bit Name Type Comment 31-0 PinPullType Read / Write None

Table 176. Pull Truth Table.

PinPullEnable PinPullType gpio_pullup gpio_pulldown 0 X 0 0 1 0 0 1 1 1 1 0

14.1.2.8 IntrEnable (Offset == 0x20)

The IntrEnable register controls the enabling or disabling of the interrupt detection logic. It is a mask of interrupt

detection logic. While the pin direction is input and interrupt detection is enabled, the pin can accept interrupt from

pad. The sense state is stored in the IntrMaskedState register (masked by IntrEnable). Before turning on the

IntrEnable, the programmer can clear the masked state by writing one to the IntrClear to ensure the initial state.

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Table 177. Interrupt Enable Register.

Bit Name Type Comment

31-0 Gpio Interrupt Detection Enable Read / Write None

14.1.2.9 IntrRawState (Offset == 0x24)

The IntrRawState register indicates the raw results of interrupt detection. If the IntrEnable is enabled, the

IntrRawState register would reflect the interrupt detection status. The programmer can poll this register to detect an

interrupt.

Table 178. Interrupt Raw State Register.


31-0 Interrupt Detection Raw State Read None

14.1.2.10 IntrMaskedState (Offset == 0x28)

The IntrMaskedState register is the masked result of the interrupt detection. The IntrMaskedState register is

controlled by the IntrEnable, IntrRawState and IntrMask registers.

Table 179. Interrupt Masked State Register.


31-0 Interrupt Detection Masked State Read None

14.1.2.11 IntrMask (Offset == 0x2C)

The IntrMask register is the mask register of the interrupt detection. It masks the IntrRawState register. For

example, if IntrEnable[0] = 1, IntrRawState[0] = 1 and IntrMask[0] = 1, then IntrMaskedState[0] will never be

changed to 1.

Table 180. Interrupt Mask Register.

Bit Name Type Comment 31-0 Interrupt Mask Read / Write None

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14.1.2.12 IntrClear (Offset == 0x30)

The IntrClear is one-bit operation logic. If some bits of the pwdata are set in a write operation to the IntrClear

address, the related bit of IntrMaskedState will be cleared.

Table 181. Interrupt Clear.

Bit Name Type Comment 31-0 Interrupt Clear Read None

14.1.2.13 IntrTrigger (Offset == 0x34)

The IntrTrigger register indicates the interrupt trigger method for each pin. If the IntrTrigger is zero, interrupt is

edge triggered; otherwise, interrupt is level triggered.

Table 182. Interrupt Trigger Method Register.


31-0 Interrupt Detection Trigger Method Read / Write Require INTR option.

14.1.2.14 IntrBoth (Offset == 0x38)

The IntrBoth register indicates whether the edge trigger is done by both-edge or single edge. If the IntrTrigger

indicates edge trigger and IntrBoth is zero, interrupt edge trigger is done by single edge. If the IntrTrigger indicates

edge trigger and the IntrBoth is one, interrupt edge trigger is done by both edges.

Table 183. Interrupt Both Edge Trigger Register.


31-0 Interrupt Both Edge Trigger Read / Write None

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14.1.2.15 IntrRiseNeg (Offset == 0x3C)

The IntrRiseNeg register indicates whether the edge trigger is done by rising edge or falling edge. If the IntrTrigger

is edge triggered, then IntrBoth is single edge and IntrRiseNeg is 0, interrupt edge trigger is done by rising edge.

If the IntrTrigger is edge trigger, the IntrBoth is single edge and IntrRiseNeg is 1, interrupt edge trigger is done by

falling edge.

Table 184. Interrupt Rise or Neg Edge Trigger Register.


31-0 Interrupt Rise or Neg Edge Trigger Read / Write None

14.1.2.16 BounceEnable (Offset == 0x40)

The BounceEnable register controls the bounce function. If the BounceEnable indicates on, interrupt detection is

sampled by the extended clock. The extended number is controlled by the BouncePreScale register.

Table 185. Bounce Enable Register.

Bit Name Type Comment 31-0 Bounce Enable Read / Write None

14.1.2.17 BouncePreScale (Offset == 0x44)

The BouncePreScale register is an auto reload register dedicated to the bounce timer. It can extend PCLK to the

BouncePreScale cycles. This can be used to adjust interrupt sample clock period in different machines. The reset

value is 0x7D0, which means that if APB clock frequency is 66 MHz, then the de-bounce clock will be divided to

33 KHz frequency. The programmer can adjust this register to fit different systems.

Table 186. Bounce Clock Pre-scale Register.

Bit Name Type Comment 23-0 Bounce Pre-Scale Read / Write None

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14.1.3 Timing

14.1.3.1 Write to GpioDataOut Register

PADDR GpioData AddressPWRITEPSELPENABLEPWDATA DATA1GpioDataOut DATA1

Figure 37. Write to GpioDataOut Register.

14.1.3.2 Positive Edge Trigger

PCLKIntrTrigger[0]PinDir[0]gpio_en[0]gpio_in[0]IntrRawState[0]IntrMaskedState[0]gpio_intr

Figure 38. Positive Edge Trigger.

14.1.3.3 Level High Trigger

PCLKIntrTrigger[0]PinDir[0]gpio_en[0]gpio_in[0]IntrRawState[0]IntrMaskedState[0]gpio_intr

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Figure 39. Level High Trigger.

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Programming Sequence

The GPIO is the default set for data input. The programmer can read the GpioDataIn register after reset directly.

If the GPIO is used for data output, the programmer should set the PinDir to one, so that the GpioDataOut register

could be sent to pad.

If the GPIO is used to detect an interrupt, the programmer needs to set the PinDir and the detection type first. The

PinDir needs to be set to zero to indicate the pin is for input. The detection types include rising edge, falling edge,

both-edge, high level and low level. Please refer to the IntrTrigger, IntrBoth and IntrRiseNeg register descriptions

for more details. The following steps constitute the GPIO programming sequence:

1. Set PinDir.

2. Set IntrTrigger, IntrBoth and IntrRiseNeg.

3. Enable IntrEnable.

In some cases, the interrupt detection may need the de-bounce function, for example, if the GPIO is used to control

keypad or switch. The following steps are required to activate the de-bounce function:

1. Set PinDir.

2. Set IntrTrigger, IntrBoth and IntrRiseNeg.

3. Set BouncePreScale.

4. Enable BounceEnable.

5. Enable IntrEnable.

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15 AHB to APB Bridge (APB Bridge)

Please refer to ATFAPBBRG020S_DS_v1.4.pdf.

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16 Pulse Width Modulator (PWM) General Descriptions

The Pulse Width Modulator (PWM) generates two output signals at most. The output signals are based on the 5.0

MHz clock and must be a minimum of 2 clock cycles wide. Various configurations can be programmed to adjust

the period and the waveform of the output signals. The output signals of PWM are shared with GPIO pins.

Features

● Two Pulse Width Modulator channels

● Enhanced Period control through 6-Bit Clock divider and 10-Bit Period counter

● 10-Bit Pulse control

Block Diagram

Figure 40 shows the block diagram of Andes’s PWM block.

APB Slave

PWM0 CTRL

PWM0 DUTY

PWM0 PERVAL

PWM1 PERVAL

6-bit Counter

10-bit Counter

pwm_clk

PWM_OUT0

Figure 40. Block Diagram of PWM.

The PWM block consists of an APB slave interface, a control register module, a 6-bit counter and a 10-bit counter.

Additionally, there are four comparators generating two channels of output signals in this block.

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16.1.1 APB Slave

The APB slave module provides AMBA/APB interface so the processor can access the control register via APB

slave module. This interface is complaint with AMBA 2.0 specification.

16.1.2 Control Register

There are six registers in the PWM block. For each channel, there are PWM CTRL, PWM DUTY and PWM

PERVAL control registers. The detail information for each register is illustrated in the next chapter.

16.1.3 Counters and Comparators

For each channel, the 6-bit counter is used to set the scale of the 3.6864MHz input clock and the 10-bit counter is

used to adjust the period and waveform.

Programming Model 16.1.4 Summary of PWM Registers Table 187. Summary of PWM Control Register.

Address (Offset) Type Description Reset Value +0x00 R/W PWM control registers for the first clock output 0x0000_0000 +0x04 R/W PWM duty cycle registers for the first clock output 0x0000_0000 +0x08 R/W PWM period control register for the first clock output 0x0000_0004 +0x0C - Reserved - +0x10 R/W PWM control registers for the second clock 0x0000_0000 +0x14 R/W PWM duty cycle registers for the second clock output 0x0000_0000 +0x18 R/W PWM period control register for the first clock output 0x0000_0004 +0x1C - Reserved -

16.1.5 Register Descriptions 16.1.6 PWM0 CTRL Register (Offset == 0x00)

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Table 188. PWM0 CTRL Register.

Bit Name Type Description 31-6 Reserved - -

5-0 Prescale R/W PWM pre-scale Divisor Determines the frequency of the PWM module clock (in terms of the 3.86 MHz clock) PSCLK_PWMn = 5.0 MHz / (PWM_CTRL[PRESCALE] + 1)

16.1.6.1 PWM0 DUTY Register (Offset == 0x04) Table 189. PWM0 DUTY Register.

Bit Name Type Description 31-11 Reserved - -

10 FDCYCLE R/W PWMn Full Duty Cycle 0 = PWM clock (PWM_OUTn) duty cycle is determined by DCYCLE field. 1 = PWM_OUTn is set high and does not toggle.

9-0 DCYCLE R/W PWMn Duty Cycle Duty cycle of PWMn clock, i.e. the number of PSCLK_PWM cycles PWMn is asserted within one cycle of PWMn.

16.1.6.2 PWM0 PERVAL Register (Offset == 0x08) Table 190. PWM0 PERVAL Register.

Bit Name Type Description 31:10 Reserved - -

9:0 PWM PERVAL R/W

PWMn Period Control: The number of PSCLK_PWMn cycles that comprise one PWM_OUTn cycle NOTE: If PWM PERVAL = 0x0, the PWMn clock (PWM_OUTn) is set high and does not toggle unless FDCYCLE=0x0 and DCYCLE=0x0. In this case PWM_OUTn is set low and does not toggle regardless of the value in PWM PERVAL.

16.1.6.3 PWM1 CTRL Register (Offset == 0x10)

Refer to PWM0 CTRL Register.

16.1.6.4 PWM1 DUTY Register (Offset == 0x14)

Refer to PWM0 DUTY Register.

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16.1.6.5 PWM1 PERVAL Register (Offset == 0x18)

Refer to PWM0 PERVAL Register.

Pulse Width Modulator Output Signal Example

In this case PWN CTRL =0x0, PWN DUTY = 0x6, and PWM PERVAL = 0x0A

Figure 41. Basic Pulse Width Waveform.

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17 I2C Bus Interface Controller

Please refer to ATFIIC010_DS_v1.4.pdf.

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18 Watch Dog Timer (WDT) General Descriptions

The WDT prevents a system from infinite looping if software becomes trapped in a deadlock. In normal operation, the user restarts the WDT at regular intervals before the counter counts down to zero. The WDT generates one or a combination of the following signals: reset, interrupt or external interrupt.

Features

● While timeout, outputs are one or a combination of: System Reset/System Interrupt/External Interrupt

● 32-bit down counter

● PCLK or EXTCLK (32.768 KHz) source selection

● Variable time-out period of reset

● Access protection

Block Diagram

Watch Dog TimerCounter

APBInterface

Watch DogComparison

PCLK

PRSTn

psel

penable

pwrite

paddr

pwdata

prdata

EXTCLK

Watch Dog TimerRegisters

wd_rstwd_intrwd_ext

Control registers

Figure 42. Block Diagram of Watch Dog Timer.

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The WDT complies with AMBA specification. The APB interface can accept signals coming from AMBA APB

bus. When reset, WDT registers are set to the predefined reset values. After the programmer turns on the WDT

enable bit in the WDT control register, the WDT counter then starts to count down. If the WDT counter reaches

zero, the WdStatus bit would be set to 1, indicating a watchdog time-out. The status could be cleared by writing 1

to the WdClear bit. Once a time-out has occurred, the WDT would assert the wd_rst, wd_intr or wd_ext signal,

depending on the state of the WdRst, WdIntr or WdExt bit in the WdCR register. The pulse width depends on the

setting of the WdIntrCter register.

To prevent unexpected watchdog reset, the programmer should write 0x5AB9 to the WdRestart register as the

password to activate down counting. If the WdRestart register equals 0x5AB9, the value of the WdLoad register

would be loaded into the WDT counter. The default reset value of the WdRestart register is zero. The WdRestart

register automatically returns to zero after each write. The default value of the WdLoad is set to 0x3EF1480; the

programmer can write this register to customize the operation of WDT reset.

Programming Model 18.1.1 Summary Of WDT Registers

Table 191 is a summary of the Watch Dog Timer programming registers.

Table 191. Summary of WDT Registers.

Address (Offset) Type Width Reset Value Name Config Description

+0x00 R 32 0x3EF1480 WdCounter None Watch Dog Timer Counter Register

+0x04 R/W 32 0x3EF1480 WdLoad None

Watch Dog Timer Counter Auto Reload Register The auto reload register is default set to 0x3EF1480.

+0x08 W 16 0x0000 WdRestart None

Watch Dog Timer Counter Restart Register When writing 0x5AB9 to this register, Watch Dog Timer will automatically reload WdLoad to WDcounter and restart counting.

+0x0C R/W 5 0x0 WdCR None Watch Dog Timer Control Register

+0x10 R 1 0x0 WdStatus None

Watch Dog Timer Status This bit is set when the counter reaches zero. 0: Watch Dog Timer does not reach zero 1: Watch Dog Timer reachs zero

+0x14 W 1 0x0 WdClear None Watch Dog Timer Clear Writing one to this register will clear the WdStatus.

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Address (Offset) Type Width Reset Value Name Config Description

+0x18 R/W 8 0xFF WdIntrCter None

Watch Dog Timer Interrupt Length This register controls the length of wd_rst, wd_intr and wd_ext. The default value is 0xFF.


The following sections describe the WDT registers in greater detail.

18.1.2.1 WdCounter (Offset == 0x00)

The WdCounter contains the current counter value. The WdCounter register is set to 0x3EF1480 when it resets.

After the programmer writes to WdRestart with 0x5AB9, the value of the WdLoad would be loaded into the

WdCounter. The WdCounter starts to count down once the WdEnable bit of the WdCR register is set. If the Watch

Dog timer is disabled, the WdCounter would hold the value. If the WdClock bit of the WdCR register is set, the

clock source is from an external clock and the WdCounter would drop to the EXTCLK frequency. This register is

read-only.

Table 192. WdCounter Register.

Bit Name Type Comment 32 WdCounter Read only None

18.1.2.2 WdLoad (Offset == 0x04)

The WdLoad contains a value which would be loaded into WdCounter. Upon reset or restart, the WdLoad value

would be automatically loaded into the WdCounter register. The reset value of the WdLoad is 0x3EF1480.

Table 193. WdLoad Register.

Bit Name Type Comment 32 WdLoad Read/Write None

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18.1.2.3 WdRestart (Offset == 0x08)

The WdRestart is used to avoid unexpected counting. If the programmer writes 0x5AB9 to this register, the Watch

Dog timer counter would load WdLoad into the WdCounter register and the WD would restart to decrease. After

finishing write cycle, The WdRestart would automatically reset to zero.

Table 194. WdRestart Register.

Bits Name Type Comment 16 WdRestart Write None

18.1.2.4 WdCR (Offset == 0x0C)

The WdCR is the Watch Dog timer control register. It defines enable, reset, interrupt, external enable and clock

source bits. The following table shows the bit definition.

Table 195. WdCR Register.

Bit Name Reset Comment

0 WdEnable 0x0 Watch Dog Timer Enable Bit 0: Disable 1: Enable

1 WdRst 0x0 Watch Dog Timer System Reset Enable Bit 0: Disable 1: Enable

2 WdIntr 0x0 Watch Dog Timer System Interrupt Enable Bit 0: Disable 1: Enable

3 WdExt 0x0 Watch Dog Timer External Signal Enable Bit 0: Disable 1: Enable

4 WdClock 0x0 Watch Dog Timer Clock Source 0: PCLK 1: EXTCLK

18.1.2.5 WdStatus (Offset == 0x10)

The WdStatus register records whehter the Watch Dog Timer reaches zero or not. It is a read-only register.

Table 196. WdStatus Register.


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1 WdStatus Read None

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18.1.2.6 WdClear (Offset == 0x14)

When writing one to this register, the WdStatus would be cleared.

Table 197. WdClear Register.

Bit Name Type Comment 1 WdClear Write None

18.1.2.7 WdIntrCter (Offset == 0x18)

The WdIntrCter register determines the asserting duration of wd_rst, wd_intr, and wd_ext signals. The default

value is 0xFF. It means the default durations of wd_rst, wd_intr, and wd_ext assertion are 256 clock cycles.

Table 198. WdIntrCter Register.

Bits Name Type Comment 16 WdIntrCter Read / Write None

Timing 18.1.3 Write to WdLoad Register

PADDR WdLoad Address

PWRITEPSELPENABLEPWDATA DATA1

WdLoad DATA1

Figure 43. Write to WdLoad Register.

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18.1.4 Write to WdLoad Register

PCLKcounter 2 0xA9

WdLoadwd_intrWdClear

1 0 0xAA

0xAA

Figure 44. Watch Dog Timer Interrupt.


To enable the WDT, the programmer needs to set the WdLoad first. The WdLoad determines the period of Watch

Dog Timer reset. The default value of the WdLoad is 0x3EF1480, which means that in a 66 MHz system, the

period of Watch Dog Timer reset is one second. The programmer is able to alter this setting. For example, setting

WdLoad to 0xEC08CE00 makes the period of Watch Dog Timer reset 1 minute, which guarantees the system

would be reset in one minute. This can be used to avoid system deadlock. The programmer also needs to write

0x5AB9 to the WdRestart for the purpose of protection.

Another consideration is clock source. The clock source PCLK cannot be gated when system sleeps, even if the

WdCR[WdClock] bit is turned on. Andes’ Watch Dog Timer can be set driven by the external clock by writing an

1 to the WdCR[WdClock] bit. The relationship between EXTCLK and PCLK should follow the limitation:

"EXTCLK cycle time / PCLK cycle time > 1". If the system does not need the external clock, simply keep

WdCR[WdClock] bit in the default value.

After setting the WdLoad, the WdRestart and the WdCR[WdClock] bits, the programmer can enable Watch Dog

Timer by writing one to the WdCR[WdEnable] bit. Thereafter, Watch Dog Timer would start to count down. The

aforementioned process is summarized in the following steps:

1. Disable Watch Dog Timer.

2. Set WdLoad register.

3. Write 0x5AB9 to WdRestart register.

4. Set WdCR[Clock] bit.

5. Enable Watch Dog.

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19 Timer

Please refer to ATFTMR010_DS_v1.2.pdf.

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20 Real Time Clock (RTC)

Please refer to ATFRTC010_DS_v1.2.pdf.

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21 SD Memory Card Host Controller (SDC)

Please refer to ATFSDC010_DS_v1.3.pdf.

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22 CompactFlash Host Interface Controller (CFC)

Please refer to ATFCFC010_DS_v1.2.pdf.

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23 UART and IrDA Controller General Descriptions

The UART Controller is a serial communications element that implements the most common infrared

communications protocols. In addition to the infrared modes, the device also provides a UART mode of operation

that is backward compatible to the 16550 to support existing communications software.

The AG101 supports two (2) UARTs: a Bluetooth UART (BTUART), and a Standard UART (STUART), both

employing the same programming model. The BTUART provides a partial set of modem control pins, including

nCTS and nRTS. The other modem control pins can be implemented via General-Purpose Input / Output (GPIO).

The STUART does not provide any modem control pins. All the UARTs can support baud rates up to 1152 Kbps.

Please note that AG101 does not support IrDA nor FFUART.

Features

The UART features include:

● High-speed NS 16C550A-compatible UART

● Programmable baud rates up to 1152 Kbps

● Ability to add or delete standard asynchronous communications bits (start, stop, and parity) in the serial data

● Programmable baud rate generator that allows the internal clock to be divided by 1 to (216-1) to generate an

internal 16X clock

● Fully programmable serial interface:

5-, 6-, 7-, or 8-bit characters

Even, odd, and no parity detection

1, 1.5, or 2 stop bit generation

● Complete status reporting capability

● Ability to generate and detect line breaks

● Fully prioritized interrupt system controls

● Separate DMA requests for transmit and receive data services

● Break, parity, overrun, framing error simulation for UART mode

● BTUART provides 32-byte transmit FIFO and 32-byte receive FIFO

● STUART provides 16-byte transmit FIFO and 16-byte receive FIFO

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Block Diagram

Figure 45 shows the block diagram of the UART Communications Controller.

Prescaler

Baud RateGenerator

UART Interface

SIR Loigic

SIP Generator

FIR Loigic

APB Interface

16-byte Tx FIFO

Status FIFO

Configuration andStatus Registers

InterruptController

Tx FIFO Controller

Rx FIFO Controller

Modem control andFlags

16-byte Rx FIFO

5

8

8

paddr[6:2]

psel

penable

pwrite

pwdata[7:0]

prdata[7:0]

irda_dma_ack

io_irda_ncts

io_irda_ndcd

io_irda_ndsrio_irda_nri

io_irda_uclk

PRSTnPCLK

io_irda_rxl

io_irda_tx_r

io_irda_rxh

irda_intr1

irda_intr2

irda_ntxrdy

irda_nrxrdy

io_irda_sin

io_irda_sout

io_irda_nout1io_irda_nout2

io_irda_nrtsio_irda_ndtr

io_irda_nout3

irda_nddis

irda_dma_req_r

io_irda_sout

FTUART010

irda_tx_ack

irda_rx_ack

Figure 45. Block Diagram of UARTCommunications Controller.

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23.1.1 APB Interface

The APB interface services the accesses to the controller registers and data FIFOs. 23.1.2 Prescaler

The prescaler divides the io_irda_uclk value by 1 to 25-1 to produce a pre-divided clock PB16XCLK for the baud

rate generator.

The prescaler also recovers the sampling clock from the received signal in FIR mode. The clock PB16XCLK

derived from the prescaler is used to sample the received signal in FIR mode. 23.1.3 Baud Rate Generator

The baud rate generator is capable of dividing the pre-divided clock PB16XCLK by 1 to 216-1 to produce a 16

times baud clock B16XCLK. 23.1.4 Tx FIFO and Rx FIFO

Both Tx and Rx FIFOs are 8-bit wide, 16-location deep. CPU data written across the APB interface is stored in the

Tx FIFO until it is read out by the transmit logic. Received data are stored in the receive FIFO by the receive logic

until it is read out by the CPU across the APB interface. Both FIFOs can be disabled to act like a one-byte holding

register.

The FIFOs are enabled or disabled using the FIFO Control Register (FCR). When the FIFOs are disabled, the

behavior is the same as if they had not been implemented. The UART working without FIFOs is called the 16450

mode by convention of the industry’s standards. In SIR and FIR modes, the Tx FIFO and Rx FIFO should always

be enabled. 23.1.5 Status FIFO

During data reception, the corresponding error bits, i.e. Parity Error, Framing Error and Break conditions, are

stored in the Status FIFO (STFIFO). Disabling the Tx/Rx FIFOs would also disable the status FIFO.

The status FIFO is also used in FIR mode. It is always an 8-level FIFO and is intended to support back-to-back

incoming frames in DMA mode. Each status FIFO entry contains both status information and frame length for a

single frame. The status FIFO is flushed when hardware reset occurs or when the Rx FIFO soft resets. The status

and length information of received frames is loaded into the status FIFO whenever the DMA_EN bit in the MDR

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register is set to 1.

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23.1.6 Configuration and Status Registers

The register files store the data to be written, or to be read across the AMBA APB interface.

23.1.7 Modem Control and Flags

This block controls the interface with the modem and provides the current state of the control lines from the

modem (or peripheral device) to the CPU.

23.1.8 SIR Logic

The SIR logic includes SIR encoder and decoder.

The encoder converts UART zeros to light pulses and ones to no pulses. The converted optical pulse duration can

be 3/16 of one bit duration or 1.6 µs by programming ACR [7]. The decoder “stretches” a valid light pulse to a

single bit cell of zeros (low level) and no light pulses to ones (high level).

23.1.9 FIR Logic

The FIR logic includes FIR encoder/decoder and transmitter/receiver.

The FIR encoder uses the Four Pulse Position Modulation (4PPM) scheme, in which 2 bits of data (symbol) are

encoded into a 4-bit cell “chip”. Each bit cell or “chip” is 125 ns wide, so each input byte (symbol) requires 2 µs

to send. Unlike SIR, chips with logic 1 produces a light pulse, and chips with logic 0 produces no light pulse.

The decoder takes a valid light pulse as a single chip with logic one while no light pulses is taken to zeros, and

de-modulates the 4PPM-encoded input signal to its raw data.

23.1.10 SIP Generator

During the FIR mode of operation, the SIP generator sends a 1.6 µs Serial Infrared Interaction Pulse (SIP)

according to the setting of MDR [2] and ACR [4].

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Modes of Operation

Basic data communication involves at least two devices. In the data transmission mode, the first device transmits

data and the second device receives the transmitted data. In the data reception mode, the second device transmits

the data and the first device receives the data. When the FIrDA is configured for the UART mode, both data

transmission and data reception can occur simultaneously, which is known as full duplex operation. In the infrared

(IR) modes, either data transmission or data reception is possible at any time but not simultaneously, which is

known as half duplex operation.

23.1.11 UART Mode

The UART mode is the default mode of operation after power up and system reset. This mode uses a wired

interface for serial communication with a remote device or a modem. The FTUART010 can operate in a

full-duplex mode, i.e. data transmission and reception can take place simultaneously. The FTUART010 in the

UART mode works as a regular serial asynchronous communication controller that converts the parallel data

received from the CPU or the DMA controller into serial data. It also converts the serial data received on the serial

input terminal into parallel data.

The term “character” is used throughout this datasheet to describe a word of data being transmitted serially. A

character can have several possible word lengths, including 5-, 6-, 7- or 8-bit managed by this module.

This mode is designed to support serial data communications with a remote peripheral device or modem using a

wired interface. The controller provides transmit and receive channels that can operate concurrently to handle

full-duplex operation. They perform parallel-to-serial conversion on data characters received from the CPU or a

DMA controller, and serial-to-parallel conversion on data characters received from the serial interface. The format

of the serial data stream is shown in Figure 46.

Start DATA (B5h, 7-bit word length) Parity (odd) Stop

SamplePoint

Figure 46. UART Data Representation and Sampling.

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A data character contains 5 to 8 data bits. It is preceded by a start bit and is followed by an optional parity bit and a

stop bit. Data is transferred in little endian order (least significant bit first).

The UART mode is the default mode of operation after power up or reset; the 16450-compatibility mode is

selected after resest. In addition to the 16450 and 16550 compatibility modes, IrDA modes are also available.

When the FIR mode is selected, the interrupt sources are no longer prioritized. The additional features include

transmitter FIFO threshold, DMA capability, and interrupts on transmitter empty.

The clock for both transmit and receive channels is provided by an internal baud generator that divides the

pre-scaled clock by any value from 1 to 2 16 - 1. The output clock frequency of the baud generator must be

programmed to be sixteen times the baud rate value. The baud generator input clock is derived from io_irda_uclk

clock through a programmable prescaler. The PSR register determines the prescaler value. Its default value is 0x01.

Both the communications format and baud rate must be programmed properly before operation. The

communications format is programmed by setting the LCR register, while the baud rate is selected by

programming the baud generator divisor registers (DLL and DLM). The software can read the status of the device

at any time during operation. The status information includes state for FIFO, and any other condition detected on

the received data stream, like parity error, framing error, data overrun, or break event.

Figure 47. SIR Encoding.

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23.1.11.1 FIR Transmission Closing Method

There are two ways a transmission frame can be properly terminated in FIR mode: frame-length method and

set-EOT bit method. The two methods are described as follows:

● Frame-Length Counter method:

This method can be used when data transfers are performed in either PIO or DMA mode. This method is

selected when the MDR [3] bit equals 0. The CPU writes the frame-length value to the TXLENH and

TXLENL registers. The device automatically attaches an ending flag to the frame when the number of

bytes transmitted becomes equal to the TXLENH and TXLENL value. This method also allows a large

data block to be automatically split into equal-size back-to-back frames while an equal-size or

different-size frame can be added in PIO or DMA mode. The length of the last frame is defined in the

registers LSTFMLENH and LSTFMLENL. The number of frames to be transmitted is defined in

LSTFMLENH [7:5]. For example, when LSTFMLENH [7:5] are programmed as zeros, the data in Tx

FIFO will always be transmitted as equal-size frames (the 4-byte CRC is not shown in the figure for

simplification):

TXLEN TXLEN TXLEN

When LSTFMLENH [7:5] are programmed as non-zeros, say 3, the data in Tx FIFO are always

transmitted as three (3) equal-size frames plus one (1) equal- or different-size frame:

TXLEN TXLEN TXLEN TXLEN

Note:

When MDR [2] bit is set as 0, the SIP would not be issued until all back-to-back frames are transferred, i.e. Tx FIFO is empty.

● Set-EOT bit method:

This method is used when data transfers are performed in PIO mode. This method is selected when the

MDR [3] bit equals 1. The CPU writes a 1 to the SET_EOT bit of the ACR register just before it writes the

last byte to the Tx FIFO. When the CPU writes the last byte to the Tx FIFO, the device internally sets the

tag bit for that particular byte in the Tx FIFO. As the FTUART010 in the transmission mode reads bytes

from the Tx FIFO, the flag-bit information is used to attach an ending flag and properly terminate the

frame.

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23.1.11.2 FIR Data-Receive Method in PIO mode

When the data reaches the preset threshold level of the Rx FIFO, the device interrupts the CPU. When the CPU is

interrupted, it reads the FMIIR_PIO to identify the source of the interrupt. When the source of the interrupt is the

FMIIR_PIO [0] bit and not the FMIIR_PIO [4] bit, the CPU enters the Threshold Mode as follows.

● Threshold Mode

During Threshold Mode, the CPU reads a number of bytes (determined by the Rx FIFO threshold level)

from the Rx FIFO. For example, when the Rx threshold value is set to be 16, the CPU can perform 16

consecutive read operations from the Rx FIFO. When the source of interrupts is the FMIIR_PIO [4] bit, the

CPU should read the RXFF_CNTR to determine the number of data bytes in the Rx FIFO when an

end-of-frame (EOF) flag is detected.

23.1.11.3 Serial Infrared Interaction Pulse

During the FIR mode of operation, the transmitter sends a 1.6µs Serial Infrared Interaction Pulse (SIP) at least once

every 500 ms. The purpose of this special pulse is to inform the slow device (in SIR mode) that the high-speed

device involved in data transaction is currently occupied. When the MDR [2] bit is a 0 (the default value), the

FTUART010 in the transmission mode always sends a 1.6µs pulse at the end of a transmission frame. However,

when bit MDR [3] is a 1, the transmission of a 1.6µs pulse depends on the value of ACR [4]. The CPU keeps a

timer and sets the ACR [4] at least once in every 500ms. When the MDR [3] is set as 1, the FTUART010 in

transmission mode sends a 1.6µs pulse only if the ACR [4] bit is a 1. The advantage to this approach over applying

the default value (always sending 1.6µs pulse at the end of a frame) is that the FTUART010 in the transmission

mode need not send the special 1.6µs pulse at the end of every frame. Sending a 1.6µs pulse at the end of every

frame may increase overhead.

Serial Infrared Interaction Pulse

1.6μs

8.7μs

Figure 48. Serial Infrared Interaction Pulse.

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23.1.11.4 Tx FIFO Underrun in FIR Mode

An underrun during data transmission occurs when the CPU fails to supply the data to the Tx FIFO. The Tx FIFO

becomes empty before the end of the frame is transmitted. When an underrun occurs, the FTUART010 closes the

frame with an ending flag but attaches an incorrect CRC value. The receiving device detects the CRC error and

discards the frame. The FTUART010 sets an internal flag and further transmission of data is disabled. The CPU

must reset the Tx FIFO and read the RESUME register. This read operation clears the internal flag.

23.1.11.5 Rx FIFO Overrun in FIR Mode

An overrun occurs during data reception if the CPU cannot timely read out data from the Rx FIFO and the Rx

FIFO is overwritten. When an overrun occurs in PIO mode, the FTUART010 interrupts the CPU with the

FMIIR_PIO [2] bit and discards the remaining portion of the frame. When an overrun occurs, the FTUART010

sets an internal flag and the receive operation of the next frame is disabled. Before the next frame can be received,

the CPU must reset the Rx FIFO and read the RESUME register. This read operation clears the internal flag.

When an Rx FIFO overrun occurs in DMA mode, the receiver continues to receive further frames. The status of

data reception will be reported in the status FIFO.

23.1.11.6 St FIFO Overrun in FIR Mode

The St FIFO overrun occurs during data reception if the CPU cannot timely read out data from the St FIFO and the

St FIFO is overwritten. The St FIFO overrun occurs only in DMA mode. The FTUART010 interrupts the CPU

with the FMIIR_DMA [2] bit and stops receiving the next frame. Then the FTUART010 sets an internal flag and

the receive operation of the next frame is disabled. Before the next frame can be received, the CPU may read out

data from St FIFO or reset St FIFO and read the RESUME register. This read operation clears the internal flag.

23.1.11.7 DMA Operation in FIR Mode

The DMA mode of data transfer is used to achieve faster data transfer when the FTUART010 is operating in the

FIR mode. In a multi-application environment, where multiple applications are running at the same time, the DMA

mode should be used to keep up with the high rate of data transfer without having underrun during data

transmission or overrun during data reception. Frames can be transmitted and received back-to-back.

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23.1.11.8 DMA Data-Transmit Mode

In DMA mode, packets are automatically fragmented into equal-sized frames, (determined by the TXLENH and

TXLENL register values) and are then properly transmitted. The last portion of the packet, which may be different

from the (TXLENH, TXLENL) register values, can be transmitted back-to-back by programming LSTFMLENL

and LSTFMLENH registers properly.

If LSTFMLENH [7:5] are programmed as zeros, the interrupt FMIIR_DMA [5] bit is generated to inform the CPU

whenever a frame is transmitted.

If LSTFMLENH [7:5] are programmed as non-zeros, the interrupt FMIIR_DMA [5] bit would be generated when

all frames are transmitted; to inform the CPU that the data transmission is completed. The FTUART010 asserts the

irda_dma_req_r signal when the number of bytes in the Tx FIFO falls below the set trigger level and de-asserts

the irda_dma_req_r when the irda_dma_ack is sampled high.

23.1.11.9 DMA Data-Receive Mode

The DMA controller controls the data reception of back-to-back frames. The back-to-back frames are transferred to

memory and the status of each received frame is stored in the Status FIFO which can hold up to 8 entries. Each

entry in the Status FIFO corresponds to one received frame. Each entry stores the length of each received frame

and the error-status of that frame. The CPU reads the Status FIFO entries to locate the frame boundaries and the

status of individual frames inside memory.

The Status FIFO has 4 interrupt levels, which are 1, 4, 7, and 8. In a data receive transaction, the receiver expects

to receive 1 to 7 frames. When the number of received frames becomes equal to or greater than the set threshold

value in the Status FIFO, the FTUART010 generates an interrupt FMIIR_DMA [0] bit. After the CPU receives the

Status FIFO interrupt (FMIIR_DMA [0 ] bit), it reads the STFF_STS register to determine the error-status of that

frame. The Status FIFO Received Frame Length Low (STFF_RXLENL) and the Status FIFO Received Frame

Length High (STFF_RXLENH) are read to determine the length of the frame. The CPU checks the content of the

bit STFF_STS [5] which is set to a 1 when this entry of Status FIFO is valid. If this bit is found to be a 0, the CPU

should stop reading the STFF_RXLENL and STFF_RXLENH.

The STFIFO timeout interrupt (bit FMIIR_DMA [1]) is set at 1 ms. This is useful when the number of frames in a

data receive transaction is less than the set Status FIFO threshold level. When the CPU receives a Status FIFO

timeout interrupt, it should read STFIFO_STS, STFF_RXLENL, and STFF_RXLENH registers until bit

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STFF_STS [4] is 0 (indicates entry invalid). The STFIFO Time-out Conditions are:

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1. At least one entry is in the STFIFO

2. More than 1 ms has elapsed since the last byte was loaded into the STFIFO from the receiver logic

3. More than 1 ms has elapsed since the CPU read the last entry from the STFIFO.

The FTUART010 asserts the irda_dma_req_r signal when the Rx FIFO is not empty. The irda_dma_req_r is

de-asserted when the irda_dma_ack is sampled high. An overrun in the Rx FIFO in the DMA mode is handled

differently than in the programmed I/O mode. When an overrun occurs in the Rx FIFO, during any frame, data

reception is terminated and the receiver state machine waits for the next frame. It continues to receive the frames to

follow. The RXFIFO_ORUN is set to a 1 in the STFF_STS register for the frame in which the Rx FIFO overrun

has occurred.

Programming Model 23.1.12 Summary Of UART and IrDA Communications Controller Registers Table 199. Summary of UART/SIR Mode Registers.

Offset Type Width Name Description Reset ValueUART / Infrared SIR Mode

R 8 RBR Receiver Buffer Register 0x00 +0x00

W 8 THR Transmitter Holding Register 0x00 +0x04 R/W 4 IER Interrupt Enable Register 0x00

R IIR Interrupt Identification Register 0x01 +0x08

W 8

FCR FIFO Control Register 0x00 +0x0C R/W 8 LCR Line Control Register 0x00 +0x10 R/W 7 MCR Modem Control Register 0x00

R LSR Line Status Register 0x60 +0x14

W 8

TST Testing Register 0x00 +0x18 R 8 MSR Modem Status Register 0x00 +0x1C R/W 8 SPR Scratch Pad Register 0x00

Registers accessible when DLAB =1 +0x00 R/W 8 DLL Baud Rate Divisor Latch Least Significant Byte 0x01 +0x04 R/W 8 DLM Baud Rate Divisor Latch Most Significant Byte 0x00 +0x08 R/W 5 PSR Prescaler Register 0x01

Infrared FIR Mode +0x20 R/W 7 MDR Mode Definition Register 0x00 +0x24 R/W 8 ACR Auxiliary Control Register 0x00

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+0x28 R/W 8 TXLENL Transmitter Frame Length Low 0x00 +0x2C R/W 5 TXLENH Transmitter Frame Length High 0x00 +0x30 R/W 8 MRXLENL Maximum Receiver Frame Length Low 0x00 +0x34 R/W 5 MRXLENH Maximum Receiver Frame Length High 0x00 +0x38 R/W 2 PLR FIR Preamble Length Register 0x00

FMIIR_PIO FIR Mode Interrupt Identification Register in PIO Mode 0x00 +0x3C R 5

FMIIR_DMA FIR Mode Interrupt Identification Register in DMA Mode 0x00

FMIIER_PIO FIR Mode Interrupt Enable Register for PIO Mode 0x00 +0x40 R/W 5

FMIIER_DMA FIR Mode Interrupt Enable Register for DMA Mode 0x00 +0x44 R 5 STFF _STS Status FIFO Line Status Register 0x00 +0x48 R 8 STFF_RXLENL Status FIFO Received Frame Length Register Low 0x00 +0x4C R 5 STFF_RXLENH Status FIFO Received Frame Length Register Low 0x00 +0x50 R 8 FMLSR FIR Mode Link Status Register 0xC3 +0x54 R/W 8 FMLSIER FIR Mode Link Status Interrupt Enable Register 0x00 +0x58 R - RSR Resume Register 0x00 +0x5C R 5 RXFF_CNTR Rx FIFO Count Register 0x00 +0x60 R/W 8 LSTFMLENL Last Frame Length Register Low 0x00 +0x64 R/W 8 LSTFMLENH Last Frame Length Register High 0x00

23.1.13 Registers Descriptions 23.1.13.1 Receiver Buffer Register (Offset == 0x00 for read)

The user can obtain the data by reading this read-only location. This data is retrieved either from the read port of

the Rx FIFO or the 1-byte register depending on whether the FIFOs are enabled or not.

● If the FIFOs are enabled:

This location refers to the top of 16-byte FIFO (i.e. the next to be read).

● If the FIFOs are not enabled:

This location refers to a 1-byte register (the bottom word of the receive FIFO) that receives the contents of

the receiver shift register once a character has been assembled.

Table 200. Receiver Buffer Register.

Bit Name Type Function 7-0 RBR R Receive Data Port

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23.1.13.2 Transmitter Holding Register (Offset == 0x00 for write)

The transmitter holding register is used to write the transmitter holding register or the transmit FIFO depending on

whether the FIFOs are enabled or not.

● If the FIFOs are enabled:

Data written to this location is pushed onto the transmit FIFO.

● If the FIFOs are not enabled:

Data written to this location is stored in the transmitter holding register (the bottom entry of the transmit

FIFO).

If the transmitted character width is less than 8 bits, it must be right-justified. Left bits (i.e. MSB) are don’t care

bits. For example, with a word length of 5 bits, writing 0xd3 or 0xf3 will result in the transmission of a 13h

character. Before writing this register, the user must ensure that the UART is ready to accept data for transmission,

for example checking if THR Empty flag is set in the LSR (see the description of this register below).

Table 201. Transmitter Holding Register.

Bit Name Type Function 7-0 THR W Transmit Data Port

23.1.13.3 Interrupt Enable Register (Offset == 0x04)

This register enables each of the possible interrupt sources individually. A logic “1” in any of these bits enables the

corresponding interrupt, while a logic “0” disables it. For a detailed description of the interrupt sources, see the

description of the Interrupt Identification Register (IIR) below.

Table 202. Interrupt Enable Register.

Bit Name Type Function 7:4 Reserved - - 3 MODEM Status R/W This bit enables the Modem Status Interrupt when set to logic 1. 2 Receiver Line Status R/W This bit enables the Receiver Line Status Interrupt when set to logic 1.

1 THR Empty R/W This bit enables the Transmitter Holding Register Empty Interrupt when set to logic 1.

0 Receiver Data Available R/W This bit enables the Received Data Available Interrupt (and character reception timeout interrupts in the FIFO mode) when set to logic 1.

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23.1.13.4 Interrupt Identification Register (Offset == 0x08)

The main purpose of this register is to identify the interrupt currently pending with the highest priority. The

FTUART010 implements a priority encoder with four levels from highest priority to lowest priority as follows:

1. Receive Line Status (highest priority)

2. Receive Data Ready and Character Reception Timeout (second priority)

3. Transmitter Holding Register Empty (third priority)

4. Modem Status (lowest priority)

Table 204 describes the different interrupt conditions and their codes of identification, together with their reset

method.

Table 203. Interrupt Identification Register.

Bit Name Type Function 7:6 FIFO mode enable R These two bits are set when FCR [0] is set as 1. 5 Reserve R These two bits of the IIR are always logic 0. 4 TxFIFO full R This bit is set as 1 when Tx FIFO is full.

3 FIFO mode only R In the 16450 Mode, this bit is 0. In the FIFO mode, this bit is set along with bit 2 when a timeout interrupt is pending.

2:1 Interrupt Identification Code R

These bits identify the highest priority interrupt that is pending. Table 204 below describes the different interrupt conditions and their codes of identification, together with their reset method. Note that for an interrupt source to be considered as pending, the corresponding bit in the IER must be enabled.

0 Interrupt Pending R

This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is pending. 0: An interrupt is pending and the IIR contents may be used as a pointer to the appropriate interrupt service routine. 1: No interrupt is pending.

Table 204. Interrupt Control Table.

FIFO Mode Only Interrupt

Identification Register

Interrupt Set and Reset Functions

Bit3 Bit2 Bit1 Bit0 Priority Level

Interrupt Type Interrupt Source Description Interrupt Reset Method

0 0 0 1 ---- None There is no interrupt pending. None

0 1 1 0 Highest Receiver Line Status

There is an overrun error, paity error, framing error or break interrupt indication corresponding to the received data on top of the receive

Read the Line Status Register (LSR)

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FIFO. Note that the FIFO error flag in LSR does not influence this interrupt, which is related only to the data on top of the Rx FIFO. This is directly related to the presence of a 1 in any of the LSR bits 1 to 4.

0 1 0 0 Second Received Data Ready

In non-FIFO mode, there is received data available in the RHR register. In FIFO mode, the number of characters in the receive FIFO is equal to or greater than the trigger level programmed in FCR. The interrupt signal will stay active while the number of words in the FIFO stays higher than that value and will be cleared when the microprocessor reads the necessary words to make the number of words in the FIFO less than the trigger level. Note that this is not directly related to LSR bit 0, which would always indicate that there is at least one word ready.

Read the Receiver Buffer Register (RBR).

1 1 0 0 Second Character Reception Timeout

There is at least one character in the receive FIFO and during a time corresponding to four characters at the selected baud rate, no new character has been received. A FIFO timeout interrupt will occur if the following conditions exist: 1. At least one character is in the FIFO. 2. The most recent serial character received was longer than 4 continuous character times ago (if 2 stop bits are programmed, the second one is included in this time delay).

Read the Receiver Buffer Register (RBR).

0 0 1 0 Third

Transmitter Holding Register Empty

In non-FIFO mode, the 1-byte THR is empty. In FIFO mode, the complete 16-byte transmit FIFO is empty, so 1 to 16 characters can be written to THR. That is to say, THR Empty bit in LSR is one.

Write the Transmitter Holding Register (THR). Alternatively, reading the Interrupt Identification Register (IIR) will also clear the interrupt if this is the interrupt type being currently indicated (this will not clear

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the flag in the LSR).

0 0 0 0 Fourth Modem Status

A change has been detected in the Clear To Send (CTS), Data Set Ready (DSR) or Carrier Detect (CD) input lines or a trailing edge in the Ring Indicator (RI) input line. That is to say, at least one of MSR bits 0 to 3 is one.

Read the Modem Status Register (MSR)

23.1.13.5 FIFO Control Register (Offset == 0x08 for write)

This is a write-only register at the same location as the IIR (the IIR is a read-only register). This register is used to

enable and clear the FIFOs, and set the Rx FIFO trigger level.

Table 205. FIFO Control Register.

Bit Name Type Function 7:6 RXFIFO_TRGL W Used to set the trigger level for the Rx FIFO interrupt. See Table 206. 5:4 TXFIFO_TRGL W Used to set the trigger level for the Tx FIFO interrupt. See Table 207.

3 DMA Mode W This bit selects the UART DMA mode. The DMA mode affects the way in how the DMA signaling outputs pins (irda_nrxrdy and irda_ntxrdy) behave.

2 Tx FIFO Reset W Setting this bit to logic 1 clears all bytes in the Tx FIFO and resets its counter logic to 0. The shift register is not cleared, so any reception active will continue. This bit will automatically return to zero.

1 Rx FIFO Reset W Setting this bit to logic 1 clears all bytes in the Rx FIFO and resets its counter logic to 0. The shift register is not cleared, so any reception active will continue. This bit will automatically return to zero.

0 FIFO Enable W Setting this bit to logic 1 enables both the transmit and receive FIFOs. Changing this bit automatically resets both FIFOs. In FIR mode, the device driver should always set this bit as 1.

Table 206. Receiver’s FIFO Trigger Level.

FCR Code Bit 7 Bit 6

16-Byte Receiver’s FIFO Trigger Level 32-Byte Receiver’s FIFO Trigger Level

0 0 1 character 1 character 0 1 4 characters 8 characters 1 0 8 characters 16 characters

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1 1 14 characters 28 characters

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64-Byte Receiver’s FIFO Trigger Level 128-Byte Receiver’s FIFO Trigger Level

0 0 1 character 1 character 0 1 16 characters 32 characters 1 0 32 characters 64 characters 1 1 56 characters 120 characters

Table 207. Transmitter’s FIFO Trigger Level.


16-Byte Transmitter’s FIFO Trigger Level 32-Byte Transmitter’s FIFO Trigger Level



64-Byte Transmitter’s FIFO Trigger Level 128-Byte Transmitter’s FIFO Trigger Level


23.1.13.6 Line Control Register (Offset == 0x0C)

This register controls the way in how transmitted characters are serialized and received characters are assembled

and checked.

Table 208. Line Control Register.

Bit Name Type Function

7 DLAB R/W Divisor Latch Access Bit (DLAB). This bit must be set in order to access the DLL, DLM and PSR registers which program the division constants for the baud rate divider and the prescaler.

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6 Set Break R/W

This bit causes a break condition to be transmitted to the receiving UART. When it is set to a logic 1, the serial output (io_irda_sout) is forced to the Spacing (logic 0) state. The break is disabled by setting bit 6 to a logic 0. The Break Control bit acts only on io_irda_sout and has no effect on the transmitter logic, so if several characters are stored in the transmit FIFO, they will be removed from this FIFO and passed sequentially to the Transmitter Shift Register which serializes them. This fact can be useful to establish the break time making use of the THR Empty and Transmitter Empty flags of the LSR.

5 Stick Parity R/W When bits 3, 4 and 5 are logic 1, the Parity bit is transmitted and checked as a logic 0. If bits 3 and 5 are 1 and bit 4 is a logic 0, then the Parity bit is transmitted and checked as a logic 1. If bit 5 is a logic 0, Stick Parity is disabled. See Table 209.

4 Even Parity R/W This bit is the Even Parity Select bit. When bit 3 is logic 1 and bit 4 is logic 0, an odd number of logic 1s is transmitted or checked in the data word bits and Parity bit. See Table 209.

3 Parity Enable R/W

This bit is the Parity Enable bit. When this bit is a logic 1, a Parity bit is generated (transmit data) or checked (receive data) between the last data word bit and Stop bit of the serial data. When bit 3 is a logic 1 and bit 4 is a logic 1, an even number of logic 1s is transmitted or checked. See Table 209.

2 Stop Bits R/W

This bit selects the number of stop bits to be transmitted. If cleared, only one stop bit will be transmitted. If set, two stop bits (1.5 with 5-bit data) will be transmitted before the start bit of the next character. The receiver always checks only one stop bit. See Table 209.

1 WL1 R/W This bit along with WL0 defines the word length of the data being transmitted and received. See Table 209 for the possible selections.

0 WL0 R/W This bit along with WL1 defines the word length of the data being transmitted and received. See Table 209 for the possible selections.

Table 209. Parity Setting Table.

LCR Code Bit5 Stick Parity Bit4 Even Parity Bit3 Parity Enable

Parity Bit (Transmitted or Checked)

X X 0 Not transmitted or checked 0 1 1 Even parity 0 0 1 Odd parity 1 0 1 1 1 1 1 0

Table 210. Word Length and Stop Bits Setting Table.

LCR Code Bit2 Stop Bit Bit1 WL1 Bit0 WL0

Character Length (bits) Number of Stop Bits

0 0 5 0 1 6

0

1 0 7

1

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1 1 8 0 0 5 1.5 0 1 6 1 0 7

1

1 1 8 2

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23.1.13.7 Modem Control Register (Offset == 0x10)

By writing this register, the user can set the modem control outputs (io_irda_ndtr and io_irda_nrts). This

register also controls the loop back mode, and provides general purpose outputs.

Table 211. Modem Control Register.

Bit Name Type Function 7 Reserved - -

6 Out3 R/W This bit controls the general purpose, active low, output io_irda_nout3 in the same way as bit 0 controls io_irda_ndtr. This bit is not found in the standard 16550 UART.

5 DMAmode2 R/W This bit selects the UART/SIR DMA mode. The DMA mode2 affects the way in which the DMA signaling output pins (irda_nrxrdy and irda_ntxrdy) behave.

4 Loop R/W Loop back mode control bit. Loop back mode is intended to test the UART or SIR communication.

3 Out2 R/W This bit controls the general purpose, active low, output io_irda_nout2 in the same way as bit 0 controls io_irda_ndtr.

2 Out1 R/W This bit controls the general purpose, active low, output io_irda_nout1 in the same way as bit 0 controls io_irda_ndtr.

1 RTS (Request to Send) R/W This bit controls the “request to send” active low output (io_irda_nrts) in the same way as bit 0 controls io_irda_ndtr.

0 DTR (Data Terminal Ready) R/W This bit controls the “data terminal ready” active low output io_irda_ndtr. A 1 in this bit makes io_irda_ndtr output a 0. When this bit is cleared, io_irda_ndtr outputs a 1.

When this UART is set in loop back mode, the following occurs:

● The serial output is connected internally to the serial input, so every character sent is looped back and

received.

● The input pin io_irda_sin is not used and the output pin io_irda_sout is set to 1 (inactive state).

● The four modem control inputs are internally connected to the two modem control outputs plus the general

purpose outputs. In this way, io_irda_ncts is internally controlled by io_irda_nrts, io_irda_ndsr by

io_irda_ndtr, io_irda_nri by io_irda_nout1 and io_irda_ndcd by io_irda_nout2. That is to say, there is a

non-ordered correspondence between the four least significant bits of the MCR and the four most

significant bits of the MSR. See Figure 49 for the connections. The modem control output pins are forced

to their inactive state (high).

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The four modem control input pins io_irda_ncts, io_irda_ndsr, io_irda_nri and io_irda_ndcd are not used. The

two modem control output pins: io_irda_ndtr and io_irda_nrts, and the two user outputs: io_irda_nout1 and

io_irda_nout2 are set to 1 (inactive state).

Register

MCR

DCD RI DSR CTSMSR

Out2 Out1 RTS DTR

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Figure 49. Interconnection between MCR and MSR in Loop Back Mode.

23.1.13.8 Line Status Register (Offset == 0x14 for read)

This register informs the user of the status of the transmitter and the receiver. In order to get information about a

received character, LSR must be read before reading the received character from RBR.

Table 212. Line Status Register.


7 FIFO Data Error R

If the FIFO is disabled (16450 mode), this bit is always zero. If the FIFO is active, this bit would be set as soon as any data character in the receiver’s FIFO has parity or framing error or if the break indication is active. This bit is cleared when the CPU reads the LSR and the rest of the data in the receiver’s FIFO do not have any of these three associated flags on.

6 Transmitter Empty R

This bit is 1 when both the THR (or Tx FIFO) and the TSR (Transmitter Shift Register) are empty. Reading this bit as 1 means that no transmission is currently taking place in the io_irda_sout output pin, and that the transmission line is idle. As soon as new data is written in the THR, this bit will be cleared.

5 THR Empty R

This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable bit (IER [1]) is set high. In non-FIFO mode, this bit is set whenever the 1-byte THR is empty. If the THR holds data to be transmitted, this bit is immediately set when this data is passed to the TSR. In FIFO mode, this bit is set when the transmitter’s FIFO is completely empty, being 0 if there is at least one byte in the FIFO waiting to be passed to the TSR for transmission.

4 Break Interrupt R

This bit is set to 1 if the receiver’s line input io_irda_sin was held at zero for a complete character time. That is, the positions corresponding to the start bit, the data, the parity bit (if any) and the (first) stop bit were all detected as zeroes. Note that a Framing Error flag always accompanies this flag. This bit is queued in the receiver’s FIFO in the same way as the Parity Error bit. When break occurs, only one zero character is loaded into the FIFO. The next character transfer is enabled after io_irda_sin goes to the marking state and receives the next valid start bit.

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Bit Name Type Function This bit is cleared as soon as the LSR is read.

3 Framing Error R

This bit indicates that the received character did not have a valid stop bit (i.e., a 0 was detected in the (first) stop bit position instead of a 1). This bit is queued in the receiver’s FIFO in the same way as the Parity Error bit. When a framing error is detected, the receiver tries to resynchronize: if the next sample is again a zero, it will be taken as the beginning of a possible new start bit. This bit is cleared as soon as the LSR is read.

2 Parity Error R

When this bit is set, it indicates that the parity of the received character is wrong according to the current setting in LCR. This bit is queued in the receiver’s FIFO, so it is associated with the particular character that had the error. Therefore, LSR must be read before RBR. Each time a character is read from RBR, the next character passes to the top of the FIFO and LSR is loaded with the queued error flags corresponding to this top-of-the-FIFO character. This bit is cleared as soon as the LSR is read.

1 Overrun Error R

When this bit is set, a character has been completely assembled in the Receiver Shift Register without having free space to put it in the receiver’s FIFO or holding register. When an overrun condition appears, the result would be different depending on whether the 16-byte FIFO is active or not: If the FIFO is not active, so that only a 1-character Receiver Holing Register is available, the unread data in this RBR will not be overwritten with the new character just received.If the FIFO is active, the character just received in the Receiver Shift Register will be overwritten, but the data already present in the FIFO is not changed. The Overrun Error flag is set as soon as the overrun condition appears. This bit is not queued in the FIFO if it is active. This bit is cleared as soon as the LSR is read.

0 Data Ready R This bit is set if one or more characters have been received and are waiting in the receiver’s FIFO for the user to read them. It is cleared to a logic 0 by reading all of the data in the Receiver Buffer Register or the FIFO.

23.1.13.9 Modem Status Register (Offset == 0x18)

This register provides information about the status of the four modem control input pins. The four most significant

bits directly provides the status of the pin, while the four least significant bits give information about changes in

these pins.

The four least significant bits can generate an interrupt (Modem Status interrupt) if enabled by the corresponding

bit in the IER. The interrupt will be generated as soon as any of them is 1. They are reset to logic "0" whenever the

Modem Status Register is read.

Table 213. Modem Status Register.

Bit Name Type Function 7 DCD R Data Carrier Detect (DCD), which is the complement of the io_irda_ndcd input.

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Bit Name Type Function 6 RI R Ring Indicator (RI), which is the complement of the io_irda_nri input. 5 DSR R Data Set Ready (DSR), which is the complement of the io_irda_ndsr input. 4 CTS R Clear To Send (CTS), which is the complement of the io_irda_ncts input.

3 Delta DCD R The delta-DCD flag. If set, it means that the io_irda_ndcd input has changed since the last time the microprocessor read this bit.

2 Trailing edge R1 R This bit is set when a trailing edge is detected in the io_irda_nri input pin, that is, when io_irda_nri changes from 0 to 1.

1 Delta DSR R If set, it means that the io_irda_ndsr input has changed since the last time the microprocessor read this bit.

0 Delta CTS R If set, it means that the io_irda_ncts input has changed since the last time the microprocessor read this bit.

23.1.13.10 Scratch Pad Register (Offset == 0x1C) Table 214. Scratch Pad Register.


7:0 User Data R/W This 8-bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to be used by the programmer to hold data temporarily.

23.1.13.11 Baud-Rate Divisor Latch (Offset == 0x00, 0x04 when DLAB = 1)

The Divisor Latch is a 16-bit register, whose most significant byte is held in DLM while the least significant byte

is held in DLL. Division factors from 1 to 65535 can be programmed. The access to these two registers, located at

addresses 1 and 0 respectively, is conditioned on the value of the DLAB bit in LCR register. The two registers can

be written and read only if this bit is 1, otherwise, the IER, RBR and THR would be accessed instead.

These two registers, together with the Prescaler Register (PSR), select the speed at which the communication will

occur. This is the baud rate at which characters would be transmitted and the expected baud rate for the characters

which would be received. Only one baud rate is defined for both transmission and reception.

The baud rate is defined as io_irda_uclk frequency divided by 16, divided by the contents of the PSR register,

and further divided by the contents of the Divisor Latch. When DLM and DLL are programmed as 0’s, there is no

output clock. It is recommended to program DLL and DLM as 0’s for power saving in FIR mode.

Table 215. Baud Rate Divisor Latch LSB.

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Bit Name Type Function 7-0 DLL R/W Baud Rate Divisor Latch Least Significant Byte

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Table 216. Baud Rate Divisor Latch MSB.

Bit Name Type Function 7-0 DLM R/W Baud Rate Divisor Latch Most Significant Byte

23.1.13.12 Prescaler Register (Offset == 0x08 when DLAB =1)

This five-bit register (PSR [4:0]) adds a second programmable division factor to obtain the desired baud rate (see

Divisor Latch description above). The division factor is the value hold in this register, so the maximum factor is 31

and the minimum is 0. Bits 5 to 7 are always zero. This is a non-standard register (i.e., it is not present in the

industry standard 16550 UART). The input clock io_irda_uclk is divided by integers from 1 to 31. When PSR is

a 0 there is no input clock to divisor latch unit. So, programming DLL and DLM would yield no effect when PSR

is set as 0. The default value for the PSR register is 01 (Hex).

This register is only accessible when the DLAB bit in LCR is set, otherwise, the Line Status Register would be

accessed instead.

Table 217. Prescaler Register.

Bit Name Type Function 7-6 Reserved - - 5-0 PSR R/W Prescaler Value

23.1.13.13 Mode Definition Register Offset == 0x20)

This register is used to select the operation mode.

Table 218. Mode Definition Register.

Bit Name Type Function 7 Reserved - - 6 IR_INV_TX R/W When set, the FIrDA generates inverted FIR or SIR pulse during transmission.

5 FIR_INV_RX R/W

This bit is provided to support optical transceivers with receive signals of opposite polarity (active high instead of active low). When set to 1, an inverter is placed on the receiver input signal path. In SIR mode, this bit is useless.

4 DMA_EN R/W When set to 1, DMA mode of operation is enabled. When data transfers are performed by a DMA controller, transmit and/or receive data, interrupts in PIO mode, should be disabled to avoid spurious interrupts.

3 FMEND_MD R/W 0: Apply Frame Length Counter method

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Bit Name Type Function 1: Apply Set End of Transmission bit method

2 SIP_BYCPU R/W

0: The controller in transmission mode always sends a 1.6µs pulse at the end of a transmission frame. 1: The transmission of a 1.6µs pulse depends on the ACR [4]. The CPU should keep a timer and set the ACR [4] bit at least once in every 500ms. Bit 1 Bit 0 Operational Mode 0 0 UART (default) 0 1 SIR 1 0 FIR

1:0 MODE_SEL R/W

1 1 Reserved 23.1.13.14 Auxiliary Control Register (Offset == 0x24)

Table 219. Auxiliary Control Register.


7 SIR_PW R/W

SIR pulse duration select. This bit determines the selection of either a 1.6µs or a 3/16 of the baud-rate pulse width. 0: 3/16 1: 1.6µs

6-5 STFF_TRGL R/W Used to set the trigger level for the status FIFO interrupt. See Table 220.

4 SEND_SIP R/W

When MDR bit 3 equals to a 1 and CPU writes a 1 to this bit while FIR is transmitting, an SIR Interaction Pulse (SIP) occurs at the end of a transmission frame. When CPU writes a 1 to this bit while FIR is idle, an SIP will be emitted immediately. This bit is cleared automatically by the controller at the end of 1.6µs IR pulse data transmission.

3 FORCE_ABORT R/W

In FIR mode, the CPU can intentionally abort data transmission of a frame by writing a 1 to this bit. The default value is a 0. Neither the end flag nor the CRC bits are appended to the frame. The CPU must reset the TX FIFO and clear this bit to 0 before next frame can be transmitted.

2 SET_ EOT (End of transmission ) R/W

In FIR mode, the CPU writes a 1 to bit 0 just before it writes the last byte to the Tx FIFO register. This bit is automatically cleared to 0 in the next CPU write of the last byte to the FTUART010. When CPU sets this bit, TX_ENABLE should also be set as 1 to keep transmitting the last byte.

1 RX_ENABLE R/W This bit is set to a 1 to enable data receptoin in all IR modes. 0 TX_ENABLE R/W This bit is set to a 1 to enable data transmission in all IR modes.

Table 220. Status FIFO Trigger Level.

ACR Code Bit7 Bit6

Status FIFO Trigger Level

0 0 1 0 1 4

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1 0 7 1 1 8

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23.1.13.15 Transmit Frame-Length Register (Offset == 0x28, 0x2C)

The TXLENL register and the TXLENH register store the value for the number of bytes of a data frame to be

transmitted. The TXLENL register stores the lower 8 bits while the TXLENH register stores the upper bits.

The frame length value does not include any appended CRC bytes. The zero value is reserved and must not be

used. Values from 1 to 213 - 1 can be used. To properly program TXLEN, the CPU must always write the lower

value into TXLENL first and then the upper value into TXLENH.

The upper 3 bits of TXLENH are reserved and must be written with 0's.

Table 221. Transmit Frame-Length Register Low.

Bit Name Type Function 7-0 TXLENL R/W Transmitter Frame Length Low

Table 222. Transmit Frame-Length Register High.

Bit Name Type Function 7-5 Reserved - - 4-0 TXLENH R/W Transmitter Frame Length High

23.1.13.16 Maximum Receiver Frame-Length (Offset == 0x30, 0x34)

While receiving data, the maximum length of a frame is limited to the value written to the MRXLENL and the

MRXLENH registers. The MRXLENL register stores the lower 8 bits while the MRXLENH register stores the

upper bits. Any frame greater than the set maximum value will be reported as a size error in FMIIR. The maximum

frame length value includes the 4-byte CRC field. Values from 5 to 2 13 - 1 can be used. The values from 0 to 4 are

reserved and must not be used.

Table 223. Maximum Receiver Frame-Length Register Low.

Bit Name Type Function 7-0 MRXLENL R/W Maximum Receiver Frame-Length Low

Table 224. Maximum Receiver Frame-Length Register High.

Bit Name Type Function 7-5 Reserved - - 4-0 MRXLENH R/W Maximum Receiver Frame-Length High

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23.1.13.17 Preamble Length Register (Offset == 0x38)

The PLR specifies the number of the preambles for FIR. At 4Mbps (FIR), the FPL count number of additional PA

bytes is inserted at the start of every frame, excluding brick walled frames.

Table 225. Preamble Length Register.

Bit Name Type Function 7:2 Reserved - - 1:0 FPL R/W Number of Preambles for FIR frames. See Table 226.

Table 226. Number of FIR Preambles.

FPL [1:0] FIR Preamble Length 0 0 16 (default) 0 1 4 1 0 8 1 1 32

23.1.13.18 FIR Mode Interrupt Identification Register (Offset == 0x3C, PIO Mode)

This register has two different definitions depending on whether the current data transfer is in PIO mode or in

DMA mode.

Table 227. FIR Mode Interrupt Identification Register.

Bit Name Type Function 7:6 Reserved - -

5 FRM_SENT R

This bit will be set under the following circumstance: If Set-EOT bit method is applied: Whenever a frame is transmitted, this bit will be set. If Frame-Length Counter method is applied: When LSTFMLENH [7:5] are programmed as 0’s, this bit will be set at the end of each frame. When LSTFMLENH [7:5] are programmed as non-zeros, this bit will be set at the end of the last frame.

4 EOF_DECTED R Received end-of-frame interrupt pending. Bit 5 is set to a 1 when the receiver detects STO flag of a frame. This bit is cleared to a 0 when FMIIR_PIO is read.

3 TXFIFO_URUN R Transmit underrun interrupt pending. Bit 4 is set to a 1 when an underrun occurs in the transmit FIFO. This bit is cleared when FMIIR_PIO is read.

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2 RXFIFO_ORUN R

Receiver FIFO overrun interrupt. Bit 2 is set to a 1 when an overrun occurs in the Rx FIFO. Overrun occurs when the CPU cannot read data fast enough from the Rx FIFO and there is no empty space available in the Rx FIFO register to store frame data. If an overrun occurs, the CPU has to service the overrun before the FTUART010 can receive more data. This bit is cleared to a 0 when FMIIR_PIO is read.

1 TXFIFO_TRIG R Transmitter interrupt pending. Bit 1 is set to a 1 when the Tx FIFO level is below its trigger level.

0 RXFIFO_TRIG R Receiver interrupt pending. Bit 0 is set to a 1 when the Rx FIFO level is equal to or above its trigger level.

23.1.13.19 FIR Mode Interrupt Identification Register (Offset == 0x3C, DMA Mode) Table 228. FIR Mode Interrupt Identification Register.

Bit Name Type Function 7:6 Reserved - -

5 FRM_SENT R

This bit will be set under the following circumstance: If Set-EOT bit method is applied: Whenever a frame is transmitted, this bit will be set. If Frame-Length Counter method is applied: When LSTFMLENH [7:5] are programmed as 0’s, this bit will be set at the end of each frame. When LSTFMLENH [7:5] are programmed as non-zeros, this bit will be set at the end of the last frame.

4 RXFIFO_ORUN R

Receiver FIFO overrun interrupt. Bit 4 is set to a 1 when an overrun occurs in the Rx FIFO. Overrun occurs when the CPU cannot read data fast enough from the Rx FIFO and there is no empty space available in the Rx FIFO register to store frame data. If an overrun occurs, the CPU has to service the overrun before the FTUART010 can receive more data. This bit is cleared to a 0 when FMIIR_PIO is read.

3 TXFIFO_URUN R Transmit underrun pending. Bit 4 is set to a 1 when an underrun occurs in the data Tx FIFO. This bit is cleared to a 0 when FMIIR_DMA is read.

2 STFIFO_ORUN R

Status FIFO overrun interrupt. Bit 2 is set to a 1 when an overrun occurs in the Status FIFO. Overrun occurs when the CPU cannot read data fast enough from the Status FIFO and there is no empty space available in the Status FIFO register to store information of received frames. If an overrun occurs, the CPU has to service the overrun before the FTUART010 can receive more data. This bit is cleared to a 0 when FMIIR_DMA is read.

1 STFIFO_TIME OUT R Status FIFO timeout interrupt pending. This bit is cleared to 0 by reading the Status FIFO.

0 STFIFO_TRIG R Status FIFO threshold interrupt pending. This bit is cleared to 0 by reading the Status FIFO until the number of valid entries is less than the set trigger level.

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23.1.13.20 FIR Mode Interrupt Identification Enable Register (Offset == 0x40, PIO Mode)

Table 229. FIR Mode Interrupt Enable Register.

Bit Name Type Function 7-6 Reserved - - 5 IRIIREN5 R/W Enable FRM_SENT Interrupt 4 IRIIREN4 R/W Enable EOF_DECTED Interrupt 3 IRIIREN3 R/W Enable TXFIFO_URUN Interrupt 2 IRIIREN2 R/W Enable RXFIFO_ORUN Interrupt 1 IRIIREN1 R/W Enable TXFIFO_TRIG Interrupt 0 IRIIREN0 R/W Enable RXFIFO_TRIG Interrupt

23.1.13.21 FIR Mode Interrupt Identification Enable Register (Offset == 0x40, DMA Mode)

Table 230. IrDA Mode Interrupt Enable Register.

Bit Name Type Function 7-6 Reserved - - 5 IRIIREN5 R/W Enable FRM_SENT Interrupt 4 Reserved - - 3 IRIIREN3 R/W Enable TXFIFO_URUN Interrupt 2 IRIIREN2 R/W Enable STFIFO_ORUN Interrupt 1 IRIIREN1 R/W Enable STFIFO_TRIG Interrupt 0 IRIIREN0 R/W Enable STFIFO_TIME OUT Interrupt

23.1.13.22 Status FIFO Line Status Register (Offset == 0x44)

This register returns the status byte at the bottom of the Status FIFO. If the LOST_FRM bit is 0, bits 0 to 4 indicate

whether any erroneous condition occurred during reception of the corresponding frame. Erroneous conditions

would also affect the error flags in the LSR register.

Table 231. Status FIFO Line Status Register.

Bit Name Type Function 7:5 Reserved - - 4 STS_VLD R When set to 1, the bottom Status FIFO entry contains valid data. 3 SIZE_ERR R Set to 1 when a frame exceeding the maximum length has been received. 2 PHY_ERR R Set to 1 when an illegal symbol is received or abort is detected during reception.

1 CRC_ERR R Set to 1 when a mismatch between the received CRC and the receiver-generated CRC is detected.

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0 RXFIFO_ORUN R This bit is set to 1 when incoming characters or entire frames have been discarded due to the RX_FIFO full.

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23.1.13.23 Status FIFO Received Frame Length Register - Low (Offset == 0x48)

This register must be read only when the STS_VLD bit in STFIFO_STS is 1. Upon reset, all bits are set to 0.

Table 232. Status FIFO Received Frame Length Register – Low.

Bit Name Type Function 7:0 RCVLENL R Least significant 8 bits of the received frame length.

23.1.13.24 Status FIFO Received Frame Length Register - High (Offset == 0x4C)

This register must be read only when the STS_VLD bit in STFIFO_STS register is 1. Upon reset, all bits are set to

0. Reading this register removes the bottom STFIFO entry. Therefore, when the STS_VLD is read as 1, the

STFF_RXLENL and STFF_RXLENH must be read sequentially in order.

Table 233. Status FIFO Received Frame Length Register – High.

Bit Name Type Function 4:0 RCVLENH R Most significant 5 bits of the received frame length.

23.1.13.25 FIR Mode Link Status Register (Offset == 0x50) Table 234. FIR Mode Link Status Register.

Bit Name Type Function 7 FIR_IDLE R No FIR transaction is in progress.

6 TXFIFO_EMPTY R Tx FIFO is empty. When the Tx FIFO becomes empty, bit 6 becomes a 1 and when Tx FIFO is not empty, it becomes a 0.

5 STFIFO_FULL R This bit is set to a 1 when the Status FIFO is full.

4 SIZE_ERR R

Frame is longer than expected. Bit 4 is set to 1 when a frame exceeding the maximum length (set by MRXLENL register and the MRXLENH register) is received. When this error is detected, current frame reception is terminated. The data received in Rx FIFO is incomplete. Reception is stopped until the next BOF is detected. Bit 4 is cleared to a 0 when the FMLSR register is read.

3 PHY_ERR R Physical error. In FIR mode, bit 3 is set to a 1 when an illegal symbol is received or abort is detected during reception. Bit 3 is cleared to a 0 when the FMLSR register is read.

2 CRC_ERR R CRC error. When a bad CRC is detected on data reception, bit 2 is set to 1. Bit 2 is cleared to 0 when the FMLSR register is read.

1 STFIFO_EMPTY R This bit is set to a 1 when the Status FIFO is empty.

0 RXFIFO_EMPTY R Rx FIFO is empty. When the Rx FIFO becomes empty, bit 0 becomes a 1 and when Rx FIFO is not empty, it becomes a 0.

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23.1.13.26 FIR Mode Link Status Interrupt Enable Register (Offset == 0x54)

Table 235 shows the bit assignment of FIR mode line status interrupt enable register. The interrupt enable registers

determine which status flag would generate an interrupt request by setting the corresponding bit to 1.

Table 235. FIR Mode Link Status Interrupt Enable Register.

Bit Name Type Function 7 FMLSIER7 R/W Enable FIR_IDLE Interrupt 6 FMLSIER6 R/W Enable TX_EMPTY Interrupt 5 FMLSIER5 R/W Enable STFIFO_FULL Interrupt 4 FMLSIER4 R/W Enable SIZE_ERR Interrupt 3 FMLSIER3 R/W Enable PHY_ERR Interrupt 2 FMLSIER2 R/W Enable CRC_ERR Interrupt 1 FMLSIER1 R/W Enable STFIFO_EMPTY Interrupt 0 FMLSIER0 R/W Enable RXFIFO_EMPTY Interrupt

23.1.13.27 Resume Register (Offset == 0x58)

When transmission underrun or reception overrun occurs, this register should be read to resume normal operation.

Reading the RBR (offset: 0x58) will obtain an indeterminate value.

23.1.13.28 Rx FIFO Count Register (Offset == 0x5C)

The Rx FIFO COUNT register represents the number of data bytes in the Rx FIFO. This register is useful when the

number of remaining bytes of a frame received in Rx FIFO is below the set trigger level. When the FIFO is full, the

RXFF_CNTR is 0x10 for FIFO with the size of 16-byte. The 4-byte CRC32 appended to the frame is also received

in Rx FIFO.

Table 236. Rx FIFO Count Register.

Bit Name Type Function 7:5 Reserved - - 4:0 RXFF_CNTR R The number of data bytes in the Rx FIFO.

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23.1.13.29 Last Frame Length Register Low (Offset == 0x60)

The LSTFMLENL register and the LSTFMLENH register store the value for the number of bytes of the last data

frame to be transmitted. The LSTFMLENL register stores the lower 8bits and the LSTFMLENH register stores the

upper bits.

The frame length value does not include any appended CRC bytes. Values from 1 to 213- 1 can be used. To

properly program LSTFMLEN, the CPU must always write the lower value into LSTFMLENL first and then the

upper value into LSTFMLENH.

The upper 3 bits of LSTFMLENH define the number of frames to be transmitted. Programming these 3 bits as all

0’s indicates only one frame with length TXLEN is intended to be transmitted (if Frame-Length Counter method is

applied or DMA mode is selected).

Table 237. Last Frame Length Register Low.

Bit Name Type Function 7:0 LSTFMLENL R/W Last Transmitter Frame Length Low

23.1.13.30 Last Frame Length Register High (Offset == 0x64) Table 238. Last Frame Length Register High.

Bit Name Type Function 7:5 FRM_NUM R/W Number of frames to be transmitted 4:0 LSTFMLENH R/W Last Transmitter Frame Length High

Table 239. Frame Number Decoding Table.

LSTFMLENH Bit7 Bit6 Bit5

Number of Frames intended to transmit

0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8

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23.1.14 SIR Mode

The operation under SIR mode is similar to the UART mode except that data communication takes place in a

slow-speed, half-duplex manner. The method of data transfer is via infrared instead of through a wired path. The

modem control register (MCR) and the Modem Status Register (MSR) are not used.

The following register programming steps are required to receive or transmit data in SIR mode transmissions:

1. Program the prescaler (PSR) register to ensure the prescaler output is approximately 1.843 MHz. The

default PSR value is 0x01.

2. Program the Baud Rate Divisor Latch Least Significant Byte (DLL) and the Baud Rate Divisor Latch Most

Significant Byte (DLM) registers to select the desired communication baud rate for the UART mode.

The baud rate is given by:

f io_irda_uclk Baud rate = PSR x DL x 16

3. Program the Mode Definition Register (MDR) to the SIR mode.

4. Program the LCR register.

● Set character length to 8-bit

● Set number of Stop bits to 1

● Disable Parity 23.1.15 SIR Data Transmission Mode

The following register programming steps are required for data transmission in the SIR mode:

1. Program the FCR register.

● Reset Tx FIFO and Rx FIFO

● Enable FIFO and set trigger level for Tx FIFO and Rx FIFO

2. Program the IER register to enable only the data transmission interrupts.

● Enable the THR Empty interrupt

● Disable the Receiver Line Status interrupt

● Disable the Receiver Data Ready interrupt

3. Program the ACR register bit 7 to select fixed 1.6 µs or 3/16th pulse width and bit 0 to enable data transmission.

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23.1.16 SIR Data Receive Mode

1. Program the FCR register.

● Reset Tx FIFO and Rx FIFO

● Enable FIFO and set trigger level for Tx FIFO and Rx FIFO

2. Program the IER register to enable data reception related interrupts.

● Enable Data Ready interrupt

● Disable THR Empty

3. Write a 1 to the ACR register bit 1 to enable data reception.

23.1.17 FIR Mode 23.1.17.1 FIR Data Transmission Mode

The following register programming steps are performed to enable transmission in the FIR mode:

1. Write a 6 to the PSR register. This divides 48-MHz input clock by 6 and generates 8-MHz internal clock for

the FIR mode of operation. Set DLL and DLM registers to 0x0.

2. Program the Mode Definition register (MDR) to:

● Select the FIR mode.

● Enable/disable the software control on the 1.6 µs SIP pulse.

● Select the frame closing method (frame-length method or set–EOT bit method)

● Enable/disable DMA mode of operation

3. Program the PLR register to:

● Select the number of preambles PLR [1:0]. The default value is 16.

4. If the frame-length method is selected for frame closing, program the TXLENL and TXLENH registers for the

frame length. In multi-frame transmission, LSTFMLENL and LSTFMLENH should also be properly set.

5. Program the FCR register to:

● Reset Tx FIFO

● Select the Tx FIFO trigger level

6. CPU writes a part of the frame (for a bigger frame) or the whole frame (a small frame such as a supervisory

frame) in the Tx FIFO. This step is optional.

7. Program the FMIIER register to enable only the transmitter-related interrupts and disable the remaining

interrupts. Enable the following:

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For programmed I/O mode

● Transmitter FIFO below threshold level interrupt enable (FMIIER [1])

● Transmitter underrun interrupt enable (FMIIER [3])

● Frame has sent interrupt enable (FMIIER [5])

For DMA mode

● Transmitter underrun interrupt enable (FMIIER [3])

● Frame has sent interrupt enable (FMIIER [5])

8. Program the FMLSIER register to enable only the transmitter-related interrupts and disable the remaining

interrupts.

9. Write a 1 to the ACR [0] bit to enable data transmission.

23.1.17.2 FIR Data Receive Mode

The following register programming steps are performed to receive in the FIR mode:

1. Program the Mode Definition Register (MDR) to:

● Select the FIR mode

● Enable/disable DMA mode of operation

2. Program the MRXLENL and MRXLENH registers for maximum receive-frame length value. The

MRXLENL register stores the lower eight bits and the MRXLENH register stores the remaining upper bits.

If the intended maximum receive-frame length is n, program the MRXLENL and MRXLENH registers to

be n + 4.

3. Program the FCR register to:

● Reset Rx FIFO

● Select the Rx FIFO trigger level

4. Program the FMIIER register to enable only the receiver-related interrupts and disable the remaining

interrupts. Enable the following:

For programmed I/O mode

● Rx threshold interrupt (FMIIER [0] bit)

● The Rx FIFO overrun interrupt (FMIIER [2] bit)

● The received end of the frame interrupt (FMIIER [4] bit)

5. Write a 1 to the ACR [1] bit to enable data reception.

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For DMA mode

● Status FIFO threshold interrupt disable (FMIIER [0])

● Status FIFO timeout interrupt disable (FMIIER [1])

● Status FIFO overrun interrupt disable (FMIIER [2])

6. Program the FMLSIER register to enable only the receiver-related interrupts and disable the remaining

interrupts.

7. Write a 1 to the ACR [1] bit to enable data reception.

This completes the programming of the registers for data reception, now the FTUART010 is ready to receive data.

The device decodes the serial data, converts it from serial data to parallel data and stores the data bytes in the Rx

FIFO. When the stored data in the Rx FIFO reaches the set threshold level, the device interrupts the CPU. When

the CPU is interrupted, it reads the FMIIR to identify the source of the interrupt.

In PIO mode, when the source of the interrupt is the FMIIR [0] bit and not the FMIIR [4] bit, the CPU goes to the

threshold mode.

When the source of the interrupt is the FMIIR [4] bit, not the FMIIR [0] bit, the CPU reads RXFF_CNTR to

determine how many bytes (including 4-byte CRC32) related to the received frame should be read out.

If the source of the interrupt is the FMIIR [2] bit, then an overrun has occurred while receiving data and the CPU

will need to service the overrun. Please refer to section 23.1.11.5 FIFO Overrun in FIR mode.

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24 Synchronous Serial Port Controller (SSP/I2S/AC97)


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25 DC Characteristics Absolute Maximum Ratings Table 240. Absolute Maximum Ratings.

Symbol Parameter Rating Unit VCC Core power supply -0.3 to 3.6 V VIN18 Input voltage of 1.8v I/O -0.3 to 2.1 V VIN3 Input voltage of 3.3V I/O -0.3 to 3.63 V VIN3 Input voltage of 3.3V I/O with 5V tolerance -0.3 to 5.5 V

TSTG Storage temperature -40 to 150 ℃ Recommended Operating Conditions Table 241. Recommended Operating Conditions.

Symbol Parameter Min. Typ. Max. Unit V2 Core power supply 1.08 1.2 1.32 V V1 Power supply of 3.3V I/O 3.0 3.3 3.6 V VCC3Alive Power supply of 3.3V I/O 3.0 3.3 3.6 V VCC12Alive Power supply of 1.8V I/O 1.08 1.2 1.32 V VCC12A Power supply of 1.8V I/O 1.08 1.2 1.32 V VCC12I Power supply of 1.8V I/O 1.08 1.2 1.32 V VIN3 Input voltage of 3.3V I/O with 5V tolerant 0 3.3 5.25 V

Commercial junction operating temperature 0 25 115 ℃ Tj

Industrial junction operating temperature -40 25 125 ℃ I/O Pad Capacitance Table 242. I/O Pad Capacitance.

Symbol Parameter Condition Min. Typ. Max. Unit CIN Input capacitance - 3.2 pF COUT Output capacitance - 3.2 pF CBID Bi-directional capacitance - 3.2 pF

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26 AC Characteristics AC Timing for SDRAM/SMC Interface Table 243. AC Timing for SDRAM/SMC Interface.

Pin Name Output Driving Capability

Max. Output Load

Max. Output Delay

Min. Input Setup Time

Min. Input Hold Time Unit

X_sdclk (Typical period : 10 ns) X_memaddr[24:0] 24mA 60 pF 5.2 - - ns X_memdata[31:0] 24mA 60 pF 5.2 2.5 0.2 ns X_sdram_cke 24mA 30 pF 5.2 - - ns X_sdram_ras_b 24mA 30 pF 4.5 - - ns X_sdram_cas_b 24mA 30 pF 4.5 - - ns X_sdram_cs_b[3:0] 24mA 30 pF 4.5 - - ns X_sdram_we_b 24mA 30 pF 4.5 - - ns X_sdram_dqm[3:0] 24mA 30 pF 4.5 - - ns

AC Timing for Ethernet MAC MII Interface Table 244. AC Timing for Ethernet MAC MII Interface.

Pin Name Max. Output Load

Max. Output Delay



X_tx_clk (Typical period : 40 ns) - - - - X_txd [3:0] *[4] 25 - - ns X_tx_en *[4] 25 - - ns X_rx_clk (Typical period : 40 ns) - - - - X_rxd [3:0] - - 10 - ns X_rx_dv - - 10 - ns X_rx_er - - 10 - ns X_mdc (Typical period : 400 ns) - - - - X_mdio *[4] 300 10 0.2 ns

[4] * The chip-to-PHY / PHY-to-chip fly time must be less than 7.5 ns.

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AC Timing for AMBA Bus Interface Table 245. AC Timing for AMBA Bus Interface.


Max. Output Delay



X_hclkout (Typical period : 20 ns) - - - - X_hm[9:5]_hbusreq 9 0.2 ns X_hm[9:5]_hlock 9 0.2 ns X_hm[9:5]_hgrant 4mA 9 X_hsplit[9:1] 9 0.2 ns X_hmaster[3:0] 4mA 9 X_hmastlock 4mA 9 ns X_hs[22-21,19-17,15,13]_hsel 4mA 9 ns X_hready 4mA 9 10 0.2 ns X_hdata[31:0] 4mA 10 9 0.2 ns X_haddr[31:0] 4mA 9 9 0.2 ns X_htrans[1:0] 4mA 9 9 0.2 ns X_hresp[1:0] 4mA 9 9 0.2 ns X_hwrite 4mA 9 9 0.2 ns X_hburst[2:0] 4mA 9 9 0.2 ns X_hsize[2:0] 4mA 9 9 0.2 ns X_hreset_b 4mA 9 ns

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AC Timing for USB2.0 T&MT Interface Table 246. AC Timing for USB2.0 T&MT Interface.


Max. Output Delay



X_u_clk (Typical period : 33 ns) - - - - X_u_data[15:0] 4mA 16 10 0.2 ns X_u_rxval - - 10 0.2 ns X_u_rxact - - 10 0.2 ns X_u_rxerr - - 10 0.2 ns X_u_txrdy - - 10 0.2 ns X_u_linesta[1:0] - 5 0.2 ns X_u_txval 4mA 10 - - ns X_u_validh 4mA 10 10 0.2 ns X_u_vctload_b 4mA 10 - - ns X_u_vctl[3:0] 4mA 10 - - ns X_u_xcvrsel 4mA 10 - - ns X_u_termsel 4mA 10 - - ns X_u_susp_b 4mA 10 - - ns X_u_opmode[1:0] 4mA 10 - - ns X_u_usbrst 4mA 10 - - ns X_u_vbus 10 0.2 ns X_sof 4mA 10 - - ns

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